Chapter 4 Conclusion and Future Work
4.1 Conclusion…
Conclusion and Future Work
4.1 Conclusion
In this work, we have fabricated and characterized a novel p-type AcM double-gated poly-Si NW transistors featuring an independent double-gated configuration. Thanks to the ultra-thin channel thickness of 20nm, the AcM devices can still be turned off under all operation modes, despite a high doping concentration is contained in the channel. Moreover, as compared with the IM counterparts, some intriguing characteristics are revealed. As the AcM devices are on, the carriers flow mainly through the whole channel, thus the current level is significantly larger than that of the IM ones in which the conduction is mainly through the induced inversion layer near the channel interface. From the TCAD simulation results, distribution of the carriers in the channel and the operation mechanisms of the two types of devices are analyzed. Unlike the IM device whose channel body is essentially depleted when the device is turned on, the quasi-neutral region of the AcM device gradually expands from the channel center to the interfaces with increasing gate overdrive.
For the subthreshold characteristics, due to the additional EOT contributed by the surface depletion region, the AcM devices exhibit worse SCEs than the IM devices, resulting in severer SS degradation and Vth roll-off. Moreover, the variation of electrical parameters is also severer for the AcM devices due to the higher EOT and high channel doping concentration, representing another major
- 26 -
issue for the AcM devices. Fortunately, these problems for the AcM devices would be ameliorated with a thinner channel thickness and DG operation. Our analysis and experimental results pointed out that the bias condition applied to the back gate would also affect the fluctuation in device characteristics.
On the other hand, from the transconductance characteristics and simulation results, for the AcM devices, the influence of the gate coupling effect is different from the IM devices. The greater Gm enhancement with the DG operation relative to SG modes for the AcM devices can be attributed to the quicker lowing in barrier height and the larger amount of holes as compared with the IM devices. Moreover, the peak value of Gm ratio shows dependence on the channel length. That’s because the DG mode has higher immunity to the SCEs than the SG mode. Moreover, from the simulation results, the electric field at the surfaces of the IM device is larger than that of the AcM device at the same gate overdrive. For the AcM devices, the conduction is through the whole channel and thus the carriers inherently suffer less from the scattering of the surface roughness and the interface traps, as we can see that the Gm degradation in high gate overdrive regime is more severe for the IM device.
4.2 Future Work
In this study, we’ve successfully fabricated the p-type AcM double-gated poly-Si NW devices and compared their electrical characteristics with those of the IM devices with undoped channels. One of our initial goals is to perform in-situ doped deposition for preparing the poly-Si films so the device’s S/D and channel have the same doping type and level. But being limited by the available techniques, such goal is not achieved in this work. This topic, however, deserves
- 27 -
future effort to achieve. Besides, effects of the doping concentration in the channel and the channel thickness remain not so clear and should be further investigated in the future.
- 28 -
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- 34 -
Figure Captions
(a) (b)
Fig. 2.1. (a) 1st gate definition and (b) lateral etching of poly-Si for NW channels.
(c) (d)
Fig. 2.1. (c) α-Si deposition followed by SPC and (d) implantation of BF2+
at a dose of 5 × 1014 cm-2.
(e) (f)
Fig. 2.1. (e) Drive-In at 900oC for 30 min and (f) S/D implantation using BF2+
at a dose of 5 × 1015 cm-2.
- 35 -
(g) (h)
Fig. 2.1. (g) S/D and NW channels definition and (h) n+ poly-Si for 2nd gate.
(a) (b)
Fig. 2.2. (a) Layout and (b) cross-section view of the double-gated device.
a b
Channel Length
Channel Thickness
Gate Oxide Channel Width
- 36 -
(a)
(b)
Fig. 2.3. TEM images of (a) an IM device and (b) an AcM device.
- 37 -
(a)
(b)
Fig. 2.4. SEM images for grain size of (a) an IM device and (b) an AcM device.
- 38 -
Fig. 3.1. Transfer characteristics of the IM device for (a) 2m channel length and (b) 0.7m channel length.
- 39 - and (b) 0.7m channel length.
- 40 -
DG SG-2 SG-1
T h re s h o ld Vo lta g e (V)
0 1 2 3 4
T h re s h o ld Vo lta g e (V )
-4 -3 -2 -1 0 AcM device
IM device VD = -0.5V
L = 0.7m 5 samples
Fig. 3.3. Threshold voltage of the three operation modes for 0.7m for both devices.
- 41 -
Fig. 3.4. Ion characteristics of the (a) IM device and (b) AcM device.
- 42 -
Fig. 3.5. Schematic illustrating the existence of an un-gated region for the current path from S/D to channel in the SG-1 mode, resulting in an extra series resistance.
- 43 - channel length and (b) 0.7m channel length.
- 44 -
Fig. 3.7. Total resistance as a function of channel length for (a) IM device and (b) AcM device.
- 45 -
Channel Length (m)
0 1 2 3 4 5 6
R
channel( M )
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VD = -0.2V VD = -0.3V VD = -0.4V
|Vg-Vth| = 4V DG mode
IM devices
AcM devices
Fig. 3.8. Channel resistance (RTOT-RS/D) as a function of channel length for both devices.
- 46 - channel depth with varying gate overdrive for the IM device.
- 47 -
Fig. 3.10. Simulation results of (a) electrical potential and (b) hole density along channel depth with varying gate overdrive for the AcM device.
- 48 -
Fig.3.11. SS characteristics of the three operation modes for (a) IM and (b) AcM devices.
- 49 -
Channel Length (m)
0 1 2 3 4 5 6
T h resh o ld Vo lt ag e (V)
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
AcM devices IM devices DG mode VD = -0.5V
Fig. 3.12. Threshold voltage as a function of channel length for the two types of devices.
Fig. 3.13. Location of the conductive channel layer(s) inside the IM and AcM devices under DG mode of operation at Vg=Vth. Unlike the IM devices, the current is mainly conducted through the central Si channel and the surface depletion regions result in an additional gate dielectric for the AcM devices.
Channel Channel Depletion layer
T
oxeChannel T
oxeChannel
IM Device AcM Device
- 50 - gate overdrive for the AcM device.
Fig. 3.15. Schematic illustrating that the EOT for the AcM devices will change with varying gate bias, which would affect the thicknesses of the depletion regions and the central conductive layer.
AcM Device SG mode
Channel Channel Depletion layer
T
oxeChannel T
oxeChannel
gate overdrive↑
- 51 - gate dielectric of the surface depletion region.
Vg-Vth
Fig. 3.17. EOT of the additional gate dielectric as a function of the gate bias.
Additional gate dielectric
∫ ( ) ∙
∫ ( )
- 52 -
Col 1 vs Col 2 - Col 9
DG SG-2 SG-1
S u b th re s h o ld S w in g ( m V /d e c )
0 200 400 600 800
IM devices
VD = -0.5V L = 1m 10 samples
(a)
DG SG-2 SG-1
S u b th re s h o ld S w in g ( m V /d e c )
0 200 400 600 800
AcM devices
VD = -0.5V L = 1m 10 samples(b)
Fig. 3.18. SS characteristics of the three operation modes for the (a) IM and (b) AcM devices with L= 1m.
- 53 -
Fig. 3.19. Simulation results of (a) threshold voltage and (b) subthreshold swing as a function of channel thickness and the channel doping concentration for IM and AcM devices.
- 54 -
Fig. 3.20. Simulation results of hole density along channel depth with varying (a) channel thickness and (b) channel doping concentration for the AcM devices.
- 55 -
Fig. 3.21. Illustration of the conductive channel and depletion regions of AcM devices at Vg=Vth under SG mode with a positive or negative back-gate bias.
Since the drain current is constant as Vg=Vth, thickness of the conductive channel is roughly a constant, so does the sum of thickness of the two (front- and back-side) depletion regions.
AcM device (p-type) - SG mode
T
oxeChannel T
oxeChannel
Depletion layer Channel Channel
- 56 - devices under SG-2 mode with varying 1st gate bias.
- 57 -
Fig. 3.23. (a) SS-vs.-Vth and (b) distribution of SS measured from 20 IM devices under SG-2 mode with varying 1st gate bias.
- 58 -
Fig. 3.24. Simulated Vth as a function of channel thickness and back-gate bias for AcM devices.
- 59 -
Fig. 3.26. Potential barrier height as a function of gate overdrive under the three operation modes for the (a) IM device and (b) AcM device. For the AcM device, the barrier height for DG mode is not only lower than those for SG modes but also decreases more quickly with increasing gate overdrive.
- 60 -
Fig. 3.27. Simulation results of electrical potential along the channel depth under DG and SG modes with the same gate overdrive of 1V for the AcM device.
Depth in Silicon (nm)
SG modes with the same gate overdrive of 1V for the AcM device.- 61 -
|Vg - Vth| (V)
0.0 0.5 1.0 1.5 2.0
G
Mr a ti o
1 2 3 4 5
0.7 m 1m 2 m 5 m
AcM devices
VD = -0.5V
Fig. 3.29. Gm ratio for the AcM devices with different channel lengths. As the channel length gets smaller, the peak value gradually becomes larger.
- 62 -
- 63 -
|Vg - Vth| (V)
0 1 2 3 4 5
N o rm a li ze d T ra n s c o n d u c ta n c e
0.0 0.2 0.4 0.6 0.8 1.0 1.2
AcM device IM device
VD = -0.5V L= 2m DG mode
Fig.3.31. Normalized transconductance Gm/Gm.max as a function of gate overdrive for the two types of devices. The Gm degradation in high gate overdrive regime is obviously more severe for the IM device.
- 64 -
Vita
姓 名 ： 吳俊鵬 Jiun-Peng Wu 性 別 ： 男
出 生 ： 西元 1986 年 10 月 28 日 出 生 地 ： 台灣 新竹市
住 址 ： 新竹市延平路一段261巷8弄18號 學 歷 ：
國立交通大學電子工程研究所 2009 年 9 月 ~ 2011 年 3 月
國立交通大學電子工程學系 2005 年 9 月 ~ 2009 年 6 月
國立新竹高級中學 2002 年 9 月 ~ 2005 年 6 月
新竹市立光華國民中學 1999 年 9 月 ~ 2002 年 6 月
新竹市立東門國民小學 1993 年 9 月 ~ 1999 年 6 月
論 文 題 目 ：
具獨立雙閘極之 P 型聚集模式多晶矽奈米線電晶體的製作與特性分析
Fabrication and Characterization of P-Type Accumulation-Mode Independent Double-Gated Poly-Si Nanowire Transistors
- 65 -
Publication List
[1] Jiun-Peng Wu, Wei-Chen Chen, Horng-Chih Lin, and Tiao-Yuan Huang,
“Fabrication and characterization of a p-type junction-free double-gated poly-Si nanowire transistor,” Int. Electron Devices and Materials Symp.
(IEDMS), Nov 18-19, 2010.
[2] Jiun-Peng Wu, Horng-Chih Lin, Zer-Ming Lin and Tiao-Yuan Huang,
“Fabrication and characterization of a p-type accumulation-mode independent double-gated poly-Si nanowire transistor,” submitted to IEEE Electron Device Lett., 2011.