Chapter 1 Introduction
1.2 Motivation
The spontaneous polarization of a ferroelectric material is mainly due to dipoles that can switch directions under the influence of an electric field. The nonvanishing electrical polarization is a result of the non-centrosymmetric crystal structure. Bulk silicon does not possess ferroelectric properties because it is of the diamond structure with centrosymmetry. No net dipolar polarization is produced by the displacement of lattice ions in the crystal. Therefore, tremendous efforts have been made to integrate non-silicon-based ferroelectric films, such as lead zirconate titanate (PZT)[2][3], with the mature silicon-based memory technology to realize FeRAM. However, the interface reactions between PZT and the Si substrate, which results in mobile ions and low data retention time[4][5][6] make it difficult to obtain a good ferroelectric/Si interface. Contamination of the Si integrated circuit (IC) fabrication line by metal ions in a non-Si based ferroelectric is also a major concern.[2][7] The development of silicon-based ferroelectric-like thin films will realize an IC-compatible FeRAM technology.
At the nanometer scale, the ratio of the numbers of atoms on the surface and in the bulk of a material increases rapidly. Interfacial properties of a nanostructured material could, therefore, enable new functional devices.[8][9] In this regard, self-assembled mesoporous silica (MS)[10][11] is attractive for its extremely large internal surface area and controllable nanoporous structure. There is provided a silicon-based ferroelectric memory material comprising a mesoporous silica (MS) with a plurality of nanopores thereon, and the arrays of nanocrystalline (nc) silicon (or germanium) quantum dots attached to the inner walls of the nanopores of the mesoporous silica by the surface bonds contributing to ferroelectricity.
In this thesis, we report that interface of nc-Si/MS exhibits a novel ferroelectric-like polarization switching effect which could potentially be developed into a fully silicon-based FeRAM technology.
Fig 1.1 MOS memory tree
SiO2
Fig. 1.2 Conventional flash memory
SiO2
SiO2
SOURCE 90nm DRAIN
2-4nm
10-16nm 5-8nm 3-4nm SiO2
SiO2
SOURCE 90nm DRAIN
2-4nm
10-16nm 5-8nm 3-4nm
Fig. 1.3 Nanocrystal memory
Table. 1.1 Performance comparison between volatile memory (DRAM & SRAM) and nonvolatile memory (Flash, FRAM, and PCM) devices. Flash memory exhibits the best performance except the disadvantages of high programming voltage and slow program/erase speed.
Reference
1. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe´, and K. Chan, Appl.
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2. C. Y. Chang, and S. M. Sze ULSI DEVICES, Wiley: New York, 2000; p. 448.
3. C. Kittel Introduction to Solid State Physics, Wiley: New York, 1996; p. 393.
4. P. C. J. Trevor, C. Y. Chang, and Y. M. L. Joseph, IEEE Electron Devices Lett.
2006, 27, 217.
5. T. Li, S. T. Hsu, B. D. Ulrich, D. R. Evans, Appl. Phys. Lett. 2005, 86, 123513.
6. T. Li, S. T. Hsu, B. D. Ulrich, L. Stecker, D. R. Evans, and J. J. Lee IEEE Electron Devices Lett. 2002, 23, 339.
7. K. J. Choi, M. Biegalski, Y. L. Li, A. Sharan, J. Schubert, R. Uecker, P. Reiche, Y.
B. Chen, X. Q. Pan, V. Gopalan, L. Q. Chen, D. G. Schlom, and C. B. Eom, Science 2004, 306, 1005.
8. C. H. Ahn, K. M. Rabe, and J. M. Triscone Science 2004, 303, 488.
9. H. Yamada, Y. Ogawa, Y. Ishii, H. Sato, M. Kawasaki, H. Akoh, and Y. Tokura, Science 2004, 305, 646.
10. H. Y. Fan, K. Yang, D. M. Boye, T. Sigmon, K. J. Malloy, H. F. Xu, G. P. López, and C. J. Brinker, Science 2004, 304, 567.
11. D. Y. Zhao, P. D. Yang, N. Melosh, J. G. Feng, B. F. Chmelka, and G. D. Stucky, Adv. Mater. 1998, 10, 1380.
Chapter 2 Basic Theory about ferroelectric memory
2.1 Ferroelectric theory 2.1.1Ferroelectricity
Ferroelectricity only occurs in some noncentrosymmetric crystal structures.
Ferroelectric crystals exhibit electric dipole moments even in the absence of an external electric field. This spontaneous polarization is caused by the two thermodynamically stable positions of constituent ions in the crystal and its direction can be changed by applying an external field. In the ferroelectric state, the center of the positive charge of the crystal does not coincide with the center of negative charge, as shown in the Fig. 2-1.
Many perovskite type (ABO3) materials are the commonly used ferroelectrics.
The crystal structure of the perovskite such as BaTiO3 (BTO) is shown in Fig. 2-2.
The Ti+4 ion is displaced at the center of the cubic, while the Ba+2 located at the corner of the cube, and the O-2 is at the face center.
The obvious feature of ferroelectric materials is the response of the polarization (P) to external electric field (E). The plot of polarization versus electric field (P–E) for the ferroelectric state is referred to the hysteresis loop, as illustrated in Fig.2-3. However, the polarization can not increase without limit, it will reach a saturation polarization Ps,which corresponds to the maximum degree of domain orientation possible for that material. The coercive field EC is the reverse field to remove the polarization to zero and further increases in the reverse field lead to saturation of P in the opposite direction. At E= 0, some of the polarization will be lost, but the remnant polarization Pr is retained. The ferroelectric materials would undergo a crystallographic phase transformation from higher temperature paraelectric phase into a lower temperature
ferroelectric phase. The temperature of the cubic to tetragonal or orthorhombic to rhombohedral transformation is known as the Curie point or Curie temperature, Tc. Ferroelectric materials that possess a low Curie temperatures close to the range of device operation are undesirable in reliability issues than those with high Curie temperatures, because ferroelectric materials with high Tc are less susceptible to Pr and Ec degradation. Since the response time of the ferroelectric dipole moment is the order of nanoseconds, non-volatile random access memory called 1T-1C type FeRAM (ferroelectric random access memory) can be realized using ferroelectric capacitors, in which two states of “0” and “1” in the binary logic are represented by the direction of the spontaneous polarization. As shown in Fig2-4[1].
ig. 2.1 The origin of ferroelectricity of perovskite materials: Dipole created by the lative displacement of the sublattices of the cations and oxygen.
ig. 2.2 The perovskite structure of BaTiO3. F
re
F
Fig. 2.3 The typical hysteresis loop (polarization to electric field) of ferroelectric materials.
ig. 2.4 The two stable polarization state of ferroelectric materials like PZT can be defined as “0” and “1” for 1T-1C type FeRAM.
F
2.1.2 Ferroelectric Field Effect Transistors
For the current progress of emerging nonvolatile memories such as
RAM( chalcogenide random access memory), FeRAM and MRAM( magnetic random The
commer terial of the capacitor to
ave larger remnant polarization, which is required to produce devices with higher density.
owever, to maintain the minimum switching charge in the scaling ferroelectric apacitoris still the most serious problem for this type of FeRAM to survive in the
ture. Besides, the disadvantage of its destructive read out is undesirable for nlimited read/write cycles and ultra fast operation speed (< 20 ns). The other type
in the transistor, therefore, no
addit is type FeRAM is
C
access memory), FeRAM is the first one in production into the electronic market.
cialized 1T-1C FeRAM needs the ferroelectric ma h
H c fu u
FeRAM consists of a ferroelectric gate dielectric
ional capacitor layer is needed (Fig 2-5 (a)). The basic unit of th
only one transistor, which is much smaller than the capacitor type FeRAM. In this metal/ferroelectric/semiconductor field effect transistor (MFS-FET), the surface potential is dependent on the remnant polarization of ferroelectrics. The data of this device are read by sensing the variation of surface conductivity of the silicon rather than the switching polarization state, which is seen in the1T-1C type FeRAM. The 1-T FeRAM has the following advantages compared to the 1T-1C type FeRAM:
1. Nondestructive readout 2. Lower power consumption
3. Scaling rule is more adaptive and very high integration density 4. Simpler integration process and lower cost
2.1.3 Type of 1-T type FeRAM
The first concept of MFS-FET was proposed from Bell Lab in 1957[2]. However, no such devices have been commercialized, because it is very difficult to obtain the excellent ferro rface. As ferroelectric materials like PZT ,
SBT were e chemical reaction and
inter-diffus the
injection effect would egrade the data retention performance of MFS-FET seriously.
In order to solve the problems of poor interface between ferroelectric and silicon bstrate, many solutions have been proposed so far:
2. M
FETs is the metal- iconductor (MFMIS) structure. This concept was first
electric/semiconductor inte
directly deposited on silicon substrates, th
ion of Pb, Bi, and Si led to very high density of surface traps in ferroelectric/Si interface .The charge trapping and charge
d
su
1. MFIS FET
(Fig 2-5 (b))
:The insulator buffer layer would be inserted between ferroelectric and Si to form a metal/ ferroelectric/insulator/semiconductor (MFIS) gate structure. It is believed that an insulator layer can prevent the problems caused by ferroelectric-semiconductor interface However, this structure causes series capacitance effect so it is difficult to applysufficient voltage on the ferroelectric thin film to switch its saturation polarization state because part of the gate bias drops on the insulator layer.
FMIS FET (Fig 2-5 (c)):
Another structure of ferroelectric-gate ferroelectric-metal-insulator-sem
proposed by Katoh/NEC in 1996[3], where metal was additionally inserted between the ferroelectric and insulator layers as a floating gate. In contrast to MFS- and MFIS-FET, the ferroelectric MFM capacitor size and MIS capacitor size can be independently designed in MFMIS-FET. It is able to adjust the area ratio of
ferroelectric capacitor and insulator capacitor in order to use the saturation polarization of the ferroelectric film effectively (i.e., make the ferroelectric capacitor area small). However, the additional lithography process makes the integration more ulator capacitor area violates the semiconductor scali
Fig. 2.5 Type of 1T-FeRAM: (a) MFS-FET (b) MFIS-FET (c) MFMIS-FET
Fig. 2.6 Schematic diagram of an all-perovskite ferroelec measurement circuit.
complicated, and the larger ins ng-down rule.
3. All Epitaxial Perovskite FET [4][5] (Fig 2-6):
The use of a perovskite semiconductive oxide such as La0.7Ca0.3MnO3(LCMO),
SrRuO3 (SRO) rather than Si ,which are more compatible with common ferroelectrics.
Toreduce the trap density under the gate, use of an epitaxial heterostructure is inevitable.Due to the excellent interface condition, the retention time of this type FeRAM is largely improved. However, the material complexity and the epitaxial process largely raise thefabrication cost.
tric FET and
2.2 Ferroelectric memory
The basic operation me hanism of ferroelectric-gate-controlled devices, such
etal-ferroelectric-insulator-silicon (MFIS) or etal-ferroelectric-metal-oxide-silicon (MFMIS) field-effect transistors (FETs), is
Fig. 2.7.[6][7] When the ferroelectric material is poled towards the gate the transistor is very large. The transistor is programmed to the ‘‘off’’ state. On the other hand, negative charges are induced at the channel when the ferroelectric material is poled toward the channel. The threshold voltage of the transistor is low and the device is programmed to the ‘‘on’’ state. During read operation, the sense amplifier detects the state of the MFMISFET. If there is a large drain current, it is on state; if there is a small drain current, it is off state.
In the previous work, we reported that interface of nc-Si/MS exhibits a novel ferroelectric-like polarization switching effect. The existence of electrical polarization in the nc-Si embedded MS structures can be revealed with polarization-electric field (P-E) measurements (See Fig. 2.8). The remnant polarization (Pr) of Si-O nanostructured layers in the metal-insulator-metal (MIM) configuration were found to be 3.0 μC/cm2 and is much larger than the reported values for iron-passivated porous silicon.[8] The memory window of devices is equal to 2Pr/CFE, where Pr and CFE are
mesurement
c as the m
m
depicted in
electrode, positive charges are induced at the channel. The threshold voltage of
the remnant polarization and capacitance of ferroelectric capacitor, respectively.
Accord
Moreover, ing to the theoretical work by Miller and McWhorter[9], an electrical polarization higher than 0.1 μC/cm2 is sufficient to switch the Si surface potential from depletion to inversion. Ferroelectricity-induced capacitance-voltage (C-V) memory window (ΔV) can be determined from the coercive field (Ec) by ΔV=2Ec.d [10], where d denotes the thickness of ferroelectric films. The coercive field of 700 kV/cm yields C-V hysteresis width of 9 V theoretically for Si-O nanostructured ferroelectrics of 65 nm in thickness, in accordance with measured values of 8 V (See Fig. 2.9). It preliminary manifests the feasibility of our materials in memory applications.
In general, in transistor memory structure, low Pr can ensure positive threshold voltage at the on state and, therefore, low standby currents.[6][7]
increasing (decreasing) the capacitance of gate insulator capacitors (ferroelectric capacitors) increases voltage drop across ferroelectrics, while reducing the polarization filed decreases the depolarization field.[6][7] Our Si-O nanostructured ferroelectric thin films have smaller polarization (3 μC/cm2), a relatively large coercive field (~600 kV/cm), and lower dielectric constant (~4) in comparison with conventional perovskite ferroelectrics. Notably, the leakage current in Si-O nanostructured ferroelectrics was quite low (See Fig. 2.10). Therefore, the Si-O
-VG
nanostructured ferroelectric material was suitable for one-transistor memory application.
Fig. 2.7 Operation mechanism for MFMISFET (or MFISFET).
At high Vth state At low Vth state
Fig. 2.8 The existence of electrical polarization in the nc-Si embedded MS structures can be revealed with polarization-electric field
-1500 -1000 -500 0 500 1000 1500
4
-12 -9 -6 -3 0 3 6 40
60 80 100 120 140 160 180
8 V
Capictance (pF)
Gate voltage
ig. 2.9 C-V hysteresis feature of Si-O nanostructured ferroelectric
m capacitors.
Fig. 2.10 Leakage currents of Si-O nanostructured ferroelectric metal-insulator-metal capacitors.
F
etal-oxide-silicon
-20 -15 -10 -5 0 5 10 15 20
10-10 10-9 10-8 10-7 10-6 10-5
Current Density (A/cm2)
Voltage (V)
Reference:
T. Mikolajick. “ The Future of Nonvolatile Memories”. Non-Volatile Memory Technology Symposium 2002
Ross,I.M: US Patent No.2791760 (1957)
E. Tokumitsu, T. Isobe, T. Kijima and H.Ishiwara Jpn. J. Appl. Phys., 40,
A. G. Schrott and J. A. Misewich 82, 4770 (2003).
5. S. Mathews, R. Ramesh, T. Venkatesan, J. Benedetto SCIENCE, 276, 238(1997)
T. Li, S. T. Hsu, B. Ulrich, H. Ying, L. Stecker, D. Evans, Y. Ono, J. S. Ma, and J.
J. Lee Appl. Phys. Lett. 79, 1661 (2001).
T. Li, S. T. Hsu, B. Ulrich, and D. R. Evans Appl. Phys. Lett. 86, 123513 (2005) Q. Chen, X. Li, Y. Zhang, and Y. Qian, Adv. Mater. 14, 134 (2002).
S. L. Miller and P. J. McWhorter, J. Appl. Phys. 72, 5999 (1992).
J. P. Han, S. M. Koo, C. A. Richter, and E. M. Vogel Appl. Phys. Lett. 85, 1439 1.
2.
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5576(2001)
Appl. Phys. Lett., 4.
5.
6.
7.
8.
9.
10.
(2004)
Chapter 3 Experimental Details
3.1 Preparation of mesoporous silica template
) [1] were deposited on p-type silicon in-coating solution, we first produced
(TEOS), H2O, HCl, and ethanol with a molar ratio of 1:
EOS/P123/H2O/HCl/Ethanol) at 70°C for 90 of triblock
precursor solution was aged at room temperature for 3-6 hours under ambient conditions, it was spin-coated onto the substrates at 3000 rpm for 30 seconds. The
ed as the nanotemplate to synthesize
silica nanotemplate films preparing is shown in Fig. 3.1.
The films of mesoporous silica (MS substrates by spin-coating. To prepare the sp
an acid-catalyzed silica sol-gel by refluxing a mixture of tetraethylorthosilicate
0.008-0.03:3.5-5.0:0.003-0.03:40 (T
minutes. A precursor solution was then made by adding an ethanol solution
copolymer Pluronic P-123 (P123) to the acid-catalyzed silica sol-gel. After the
film was dried at 40-60 °C for 4-6 hours, and then baked at 100-120°C for 3 hours.
The resulting mesoporous silica film was us
three-dimensional array of Si nanocrystals (nc-Si). The flowchart of mesoporous
ig. 3.1 Flowchart of sol-gel procedure for preparing mesoporous silica nanotemplate films.
Aging for 3-6 hours, RT
Spin coating on Si Wafer
Drying at 40
oC and baking at 110
oC
tion ) (Self-assembly aggrega
Addition of triblock copolymer template
MS template preparing flowchart Precursor sol : P123/H2o/HCl
70℃, 90 min
Aging for 3-6 hours, RT
Spin coating on Si Wafer
Drying at 40
oC and baking at 110
oC
tion ) (Self-assembly aggrega
Addition of triblock copolymer template
MS template preparing flowchart Precursor sol : P123/H2o/HCl
70℃, 90 min
F
3.2 Synthesis of Si (or Ge) nanocrystals
nc-Si was grown with a cluster-level inductively coupled plasma chemical vapor eposition (ICPCVD)[2][3] system at a base pressure as low as 10-6 torr. After
ading MS-coated wafers into the chamber, the plasma was formed by exciting a iH4+H2/H2 mixture with a radio-frequency electrical power of 500 W. The gas ixture was kept below 10 mtorr and the substrate temperature maintained at 250 °C uring the entire process. Small size (~4 nm) and large size (~6 nm) nc-Si can be nthesized by using twelve and fifteen cycles of pulsed ICP, with a duty cycle of 1 cond and 3 seconds, respectively. The corresponding cross-sectional transmission lectron microscopy (TEM) images of pure MS film and the MS films embedded with e small- and large-size nc-Si are presented in Fig. 3.2 with the detailed growth arameters summarized in Table 3.1.
The formation of high quality nc-Si inside the nanopores of the MS with pulsed lasma involves several critical steps. First of all, the pure-H2 ICP shall be used to move organic templates of MS matrices lightly to form nucleation sites of Si-OH on e surfaces of nanopores[4] needed for a self-limiting growth reaction (SLR). The LR is the key for atomic layer deposition.[5] Subsequently, ICP-excited SiHn
on the pore surfaces. The adsorbed species eventually react with the nucleation sites f Si-OH via hydrogen-elimination reaction (HER),[4] as illustrated in Fig 3.3. SLR
cooperation with HER precisely governs the conversion of ICP-excited species ound in MS into nc-Si. The number density of nc-Si (or nc-Ge) grown by pulsed lasma can be as high as 2.5×1018cm-3. The resulting number density is about 5-10 mes higher than that grown by steady-state plasma, where only HER is involved uring the growth of nc-Si.
d
species in the form of nanoclusters diffuse into the nanopores of MS, and then absorb
o
The organic contents of MS can be removed in situ by calcinatiion with H2 plasma at a flow rate of 200 sccm for 10 minutes. For device applications, a 15-nm thick SiO2
2
matrix can be accurately controlled and reproducible.
twelve and fifteen cycles of pulse plasma, respectively. The inset shown in film was deposited with ICP CVD underneath and above the nc-Si/MS film. Since all sample preparation processes were conducted sequentially in the high-vacuum environment, the quality and characteristics of the interfaces between nc-Si and MS
Fig 3.2 The cross-sectional TEM images of (a): pure MS film, and nc-Si/MS films with high-density of (b): small-size nc-Si, (c): large-size nc-Si prepared with (b) reveals the lattice fringes of nc-Si. For comparison, the TEM image of nc-Si/MS film grown with steady-state plasma is also shown in (d).
20nm
20nm 20nm
2.46
[210]
(a) (b)
(d) (c)
Conditions of Gas Supply ICP sequence
steady-state plasma steady-state SiH4(1 sccm) + H2(200 sccm) for 15 seconds
Pulsed plasma twelve (fifteen) cycles of
H2step SiH4+ H2 step
15 sec
pulsed SiH4(1 sccm) + H2(200 sccm)/ H 0 sccm) with a duty cycle of 1 second/3 seconds
2(20
Table 3.1 Flow rate and sequence of the ICP deposition cycles used for the preparation of nc-Si/MS film .
3S 1 3S 1
Fig 3.3 (a)The ICP CVD system of nc-Si (nc-Ge) in MS matrices by either pulsed or steady-state ICP 2 layers by stead-state ICP.
(b) Schematic mechanism of 3D Si nanodots formed by pulse ICP process.
which synthesize
and deposit of SiO
H2 SiH4 STEP A STEP B Silica pore-wall Organic template
SiH4+H 2ICP H ICP2
Si
Small size nc-Si in MS
ICP seque ce n H2 SiH4 STEP A STEP B Silica pore-wall Organic template
SiH4+H 2ICP H ICP2
Si
Small size nc-Si in MS
ICP seq n
(a) (b)
ue ce
3.3 Device fabrication
Current-voltage (I-V), capacitance-voltage (C-V) characteristics of nc-Si/MS anostructured films were studied using a metal-oxide-semiconductor (MOS) apacitor structure. The testing devices inv a composite oxide (O) layer of
iO2/nanostructured film/SiO2 stack (See Fig. 3.4).The top electrode pad of the MOS apacitor was made of an aluminum film, 250 nm in thickness and 400-μm in iameter. The back-side of the semiconductor substrate S was coate with a blanket luminum film.
ig. 3.4 The MOS structure with nc-Si/MS films 3.3.1 Capacitance fabrication
n
3.3.2 The fabrication of nc-Si/MS MOSFET
r FeRAM technology, a MOS field-effect
structure. Poly-Si channels on quartz substrates were formed by the green CW ion (CLC) of amorphous silicon islands with thicknesses of 100nm, hich were deposited by low pressure chemical vapor deposition (LPCVD). Gate dielectrics of nc-Si/MS with a thickness of 100 nm together with thermally
eposited poly-Si gates with a thickness of 200 nm, are applied to form self-aligned ansistors. Poly-Si gates and S/D regions were doped with PH3 (5.0x1015cm-2 and 35 keV) and activated by furnace thermal annealing (FA) for 12 h at 580 0C.[6] Fig. 3.5 ows the procedures and key facilities used for the fabrication of the test devices and e pictures of the fabricated devices.
To test the feasibility of nc-Si/MS fo
transistor (MOSFET) was fabricated with a 70-nm nc-Si/MS layer was used in place of the gate dielectrics. A 15-nm thick oxide buffer layer underneath and above the nc-Si/MS film was introduced to inhibit charge transport through the gate dielectric
laser-crystallizat w
d tr
sh th
CW Laser annealing
Fig. 3.5 The green laser-annealing system is formed of epi-like Si layers on quartz substrates and the transistor with poly Si/ SiO2/nc-Si-in-MS/SiO2 gate structure on the epi-like Si layers
Quartz wafer
buffer oxidePoly Si
oxide/(nc-Si/MS)/oxide
buffer oxidePoly Si
gate oxide
3.4 Experiment Setup
The system we used to measure the high ferquence capacitance is Bias emperature Stress measurement system (BTS): Keithley 590 CV analyzer 、
eithley 595 Quasistatic CV meter、Keithley 230 programmable voltage source、
eithley 5951 remote input coupler and computer with ICS software installed and the
eithley 5951 remote input coupler and computer with ICS software installed and the