含自組裝矽量子點之奈米孔洞氧化矽複合材料閘極之非揮發記憶體

全文

(1)國立交通大學光電工程研究所碩士論文. 含自組裝矽量子點之奈米孔洞氧化矽複合材料閘極之非揮發記憶體 Nonvolatile memory with gate of self-assembled nanostructures of silicon quantum-dots in mesoporos silica. 研究生：黃建達指導教授：郭浩中盧廷昌. 教授教授. 中華民國九十七年七月.

(2) 含自組裝矽量子點之奈米孔洞氧化矽複合材料閘極之非揮發記憶體 Nonvolatile memory with gate of self-assembled nanostructures of silicon quantum-dots in mesoporos silica. 研究生：黃建達指導教授：郭浩中盧廷昌. Student: Jian-Da Huang Advisor: Hao-Chung Kuo Tien-Chang Lu. 國立交通大學光電工程研究所碩士論文. A Thesis Submitted to the Institute of Electro-Optical Engineering National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of Master in Electro-Optical Engineering July 2008 Hsinchu, Taiwan. 中華民國九十七年七月.

(3) 含自組裝矽量子點之奈米孔洞氧化矽複合材料閘極之非揮發記憶體學生:黃建達. 指導教授: 郭浩中教授盧廷昌教授. 國立交通大學光電工程研究所碩士班摘要在本篇論文中，利用將零維度矽奈米微晶埋藏於自我組裝奈米孔洞氧化矽模版中，展示了新型態的人工製造類鐵電材料，我們將量測到的極化場歸因於奈米晶粒與二氧化矽模板間非對稱介面鍵結感應電子極矩所產生。我們也將此種材料替換金-氧-半場效電晶體的閘極介電層，展示了高度的潛力應用在矽基非揮發鐵電記憶體。. i.

(4) Nonvolatile memory with gate of self-assembled nanostructures of silicon quantum-dots in mesoporos silica Student: Jian-Da Huang. Advisor: Dr. Hao-Chung Kuo Dr. Tien-Chang Lu. Insitude of Electro-Optical Engineering National Chiao Tung University Abstract In this thesis, a new class of artificially engineered ferroelectric-like materials synthesized by embedding three-dimensional arrays of Si nanocrystals in mesoporous silica matrix was reported. We attribute the measured polarization switching to polar layers lying at the interfaces between one-side bonded Si nanocrystals and mesoporous silica matrix. A metal-oxide-semiconductor field-effect transistor with the ferroelectric-like material in place of the gate dielectrics was fabricated to demonstrate its high potential for the silicon-based nonvolatile random-access memories.. ii.

(5) 誌謝本論文能夠順利完成，首先要感謝我的指導老師郭浩中教授及盧廷昌教授，使我在兩年的研究所學習生涯中，得以培養出獨立研究的能力。特別感謝國家奈米元件實驗室謝嘉民博士給予我細心的指導與鼓勵，讓我知道實驗的方向及效率是影響成果優劣的最重要因素。其次，也要謝謝李柏璁教授及戴寶通博士擔任我的口試委員，提供我不少的寶貴意見。. 感謝奈米元件實驗室工程師游文謙及王昭凱學長在實驗上對我的指導及實驗儀器上的幫助，你們的經驗與指教幫助我度過不少難關。感謝博士班學長們，鈺庭學長、志榜學長在電晶體的製程提供許多的寶貴經驗與意見、怡超學長提供的光學系統與雷射時間、建華學長的機台使用經驗、小朱學長、宗憲學長、小賴學長、清華學長、明華學長、俊榮學長、士偉學長、碩均學長、振昌學長、禮榮學長、輝閔學長、閔安學長的討論與指教，你們的指點幫忙讓我的研究更加順利。感謝和我共同奮鬥的同學們:子維、家銘、pinkie、伯駿、恕帆、柏源、晁恩、承恩、柏孝、及我最大的戰友，士嘉，真的很慶幸能遇見你們這群可愛的朋友，有你們的陪伴，兩年的生活更加多采多姿。也謝謝睿中及所有學弟妹默默地付出，使我能順利的完成研究。祝福你們未來的實驗順利。也要謝謝親愛的映儒，謝謝妳貼心的陪伴與體諒，讓我能夠順利的完成研究。最後，謹將本論文獻給我的父母。謝謝他們辛苦的支持與不斷的鼓勵，使我能順利完成學位。. iii.

(6) Contents Abstract (in Chinese). i. Abstract (in English). ii. 誌謝. iii. Contents. iv. List of Table. vi. List of Figures. vii. Chapter 1 Introduction 1.1 The general background of nonvolatile memory. 1. 1.2 Motivation. 2. 1.3 References Chapter 2 Basic Theory about ferroelectric memory. 6. 2.1 Ferroelectric theory. 7. 2.1.1 Ferroelectricity. 7. 2.1.2 Ferroelectric Field Effect Transistors. 10. 2.1.3 Type of 1-T type FeRAM. 11. 2.2 Ferroelectric memory measurement Chapter 3. 13. Experimental Details. 3.1 Preparation of mesoporous silica template. 18. 3.2 Synthesis of Si (or Ge) nanocrystals. 20. 3.3 Device fabrication. 24. 3.3.1 Capacitance fabrication. 24. 3.3.2 The fabrication of nc-Si/MS MOSFET. 25. 3.4 Experiment Setup Chapter 4. 27. Results and Discussions. 4.1 C-V measurement. 29 iv.

(7) 4.2 I-V characteristics of the ferroelectric memory. 31. 4.3 Discussion. 32. Chapter 5. Conclusions and future work. 5.1 Conclusions. 44. 5.2 Future work. 45. v.

(8) List of Table Table. 1.1 Performance comparison between volatile memory (DRAM & SRAM) and nonvolatile memory (Flash, FRAM, and PCM) devices. Flash memory exhibits the best performance except the disadvantages of high programming voltage and slow program/erase speed………………….….5 Table 3.1 Flow rate and sequence of the ICP deposition cycles used for the preparation of nc-Si/MS film………………………….…………………22. vi.

(9) List of Figures Fig 1.1 MOS memory tree…………………………………………………………….3 Fig. 1.2 Conventional flash memory…………………………………………………..4 Fig. 1.3 Nanocrystal memory………………………………………………………….4 Fig. 2.1 The origin of ferroelectricity of perovskite materials: Dipole created by the relative displacement of the sublattices of the cations and oxygen………….8 Fig. 2.2 The perovskite structure of BaTiO3…………………………………………..8 Fig. 2.3 The typical hysteresis loop (polarization to electric field) of ferroelectric materials……………………………………………………………………..9 Fig. 2.4 The two stable polarization state of ferroelectric materials like PZT can be defined as “0” and “1” for 1T-1C type FeRAM………………………….9 Fig. 2.5 Type of 1T-FeRAM: (a) MFS-FET (b) MFIS-FET (c) MFMIS-FET………12 Fig. 2.6 Schematic diagram of an all-perovskite ferroelectric FET and measurement circuit………………………………………………………..12 Fig. 2.7 Operation mechanism for MFMISFET (or MFISFET)……………………..15 Fig. 2.8 The existence of electrical polarization in the nc-Si embedded MS structures can be revealed with polarization-electric field……………………………15 Fig. 2.9 C-V hysteresis feature of Si-O nanostructured ferroelectric metal-oxide-silicon capacitors……………………………………………..16 Fig. 2.10 Leakage currents of Si-O nanostructured ferroelectric metal-insulator-metal capacitors…………………………………………………………………..16 Fig. 3.1 Flowchart of sol-gel procedure for preparing mesoporous silica nanotemplate films………………………………………………………………………..19 Fig 3.2 The cross-sectional TEM images of (a): pure MS film, and nc-Si/MS films with high-density of (b): small-size nc-Si, (c): large-size nc-Si prepared with twelve and fifteen cycles of pulse plasma, respectively. (b) reveals the lattice fringes of nc-Si.. The inset shown in. For comparison, the TEM image of. nc-Si/MS film grown with steady-state plasma is also shown in (d)………21 Fig 3.3 (a)The ICP CVD system which synthesize of nc-Si (nc-Ge) in MS matrices by either pulsed or steady-state ICP and deposit of SiO2 layers by stead-state ICP. (b) Schematic mechanism of 3D Si nanodots formed by pulse ICP process……………………………………………………………………...23 Fig. 3.4 The MOS structure with nc-Si/MS films……………………………………24. vii.

(10) Fig. 3.5 The green laser-annealing system is formed of epi-like Si layers on quartz substrates and the transistor with poly Si/ SiO2/nc-Si-in-MS/SiO2 gate structure on the epi-like Si layers…………………………………………..26 Fig. 3.6 The schematic diagram of C-V measurement system……………………………27 Fig. 4.1 Schematic drawing illustrating the one-side bonding geometry of Si nanocrystals in porechannels prepared by applying an electric field during the synthesis process (right plot).. A transistor with Al/. SiO2/nc-Si-in-MS/SiO2 gate structure on the epi-like Si layers that was activated by green laser irradiation was illustrated on the left plot………..35 Fig. 4.2 C-V hysteresis characteristics of a MOS capacitor containing the Si-O polar layer of nc-Si/MS capped with a 15-nm thick SiO2 buffer layer on the top and bottom (red-colored curves). For comparison, C-V hysteresis for a MOS capacitor with larger nc-Si to completely fill the porechannels of MS (solid and dashed curves in blue) is also presented.. Solid and dashed. curves indicate the C-V obtained with a voltage sweep from positive to negative and from negative to positive, respectively………………………36 Fig. 4.3 A ferroelectric-like switching with ultralow gate current was demonstrated with a MOSFET structure depicted in Fig. 4.1…………………………….37 Fig. 4.4 Id versus Vd characteristics of a 10μm* 10 μm memory device after writing to the “on” state and “off” states using a gate voltage of 17 V and -17 V, respectively………………………………………………………………38 Fig. 4.5 The retention properties of transistors. The threshold voltage is measured as a function of time after applying writing of +17 and −17 V, respectively. The threshold voltage was measured by sweeping gate voltage from -6 to 6 V..39 Fig. 4.6 The initial state and. the device after writing to the “on” state and “off”. states using a gate voltage of 17 V and -17 V, respectively……………….40 Fig. 4.7 Gate stack of the 1T-FeRAM is modeled by a ferroelectric capacitance (C ) in F. series with the semiconductor capacitance CIS , where C may be generalized to. represent the series combination of an insulating buffer on top of the semiconductor. A gate voltage V induces a polarization P and a voltage VIS across CIS………………………………………………………………………………………………………41. viii.

(11) Fig. 4.8 (a) The MFIS-FET is in its “on” state and the electric field distribution favors electron injection toward the ferroelectric/buffer interface where some electrons are trapped in the dielectric stack and (b) sufficient electron trapping has taken place that results in diminished polarization effect ,the MFIS-FET is in its “off” state…………………………………………..…41. ix.

(12) Chapter 1 Introduction 1.1 The general background of nonvolatile memory With development of the information industry and provision of more applications of the information media, various kinds of memory have increasingly become important. important one.. Among them, the electronic memory is undoubtedly the most. The electronic memories may be functionally categorized into two. types. (Fig. 1.1) One is random access memory (RAM), which possesses an access time down to below 100 ns.. However, the RAM does not provide a permanent. memory function. The other one is non-volatile memory, such as flash memory, which has a permanent memory function, but has an access time greater than 1 ms. Floating-gate memory (Fig. 1.2) can be the most commonly used non-volatile memory and has been utilized in a variety of electronic products. However, as the semiconductor process is developed down to below 70 nanometer, the scalability of the floating-gate memory has met a challenge. It is because that the floating-gate memory can not has superior charging capability and high memory performance any more in case that the dimension of the floating-gate memory is manufactured down to the nano-level. To solve the above-mentioned problems, a nano quantum dot memory(Fig. 1.3) [1]device has been suggested, in which the nano quantum dots existing in a thin film, instead of the poly-silicon floating gate, is used as the floating gate for charge storage. Although many quantum dot memories are made from silicon-based materials and are compatible with the semiconductor processes, the processes of nano quantum dot memory devices are not easy to be controlled, which limits their developments. Furthermore, since the quantum dot memory device is operated in a similar manner with the conventional floating-gate memory, i.e. operated by moving charges, it has. 1.

(13) the disadvantages of relatively large power consumption, long access time and reduced lifetime. For solving this problem, a novel ferroelectric memory has been set forth. Since the ferroelectric memory is not involved with any charge motion and collision during the access process, it has a relatively fast access time (approximately 10-9 sec), a prolonged retention time and a relatively low power consumption, compared with that of the conventional floating-gate memory.(Table 1.1) Further, the ferroelectric memory can have theoretically limitless operation cycles. In spite of the above-mentioned advantages, the ferroelectric memory has encountered with the process compatibility problem for a long time.. 1.2 Motivation The spontaneous polarization of a ferroelectric material is mainly due to dipoles that can switch directions under the influence of an electric field. The nonvanishing electrical polarization is a result of the non-centrosymmetric crystal structure. Bulk silicon does not possess ferroelectric properties because it is of the diamond structure with centrosymmetry. No net dipolar polarization is produced by the displacement of lattice ions in the crystal. Therefore, tremendous efforts have been made to integrate non-silicon-based ferroelectric films, such as lead zirconate titanate (PZT)[2][3], with the mature silicon-based memory technology to realize FeRAM. However, the interface reactions between PZT and the Si substrate, which results in mobile ions and low data retention time[4][5][6] make it difficult to obtain a good ferroelectric/Si interface. Contamination of the Si integrated circuit (IC) fabrication line by metal ions in a non-Si based ferroelectric is also a major concern.[2][7] The development of silicon-based ferroelectric-like thin films will realize an IC-compatible FeRAM technology.. 2.

(14) At the nanometer scale, the ratio of the numbers of atoms on the surface and in the bulk of a material increases rapidly. Interfacial properties of a nanostructured material could, therefore, enable new functional devices.[8][9] In this regard, self-assembled mesoporous silica (MS)[10][11] is attractive for its extremely large internal surface area and controllable nanoporous structure. There is provided a silicon-based ferroelectric memory material comprising a mesoporous silica (MS) with a plurality of nanopores thereon, and the arrays of nanocrystalline (nc) silicon (or germanium) quantum dots attached to the inner walls of the nanopores of the mesoporous silica by the surface bonds contributing to ferroelectricity. In this thesis, we report that interface of nc-Si/MS exhibits a novel ferroelectric-like polarization switching effect which could potentially be developed into a fully silicon-based FeRAM technology.. Fig 1.1 MOS memory tree. 3.

(15) SiO2 Si3N4 SiO2. 8-15nm 10-20nm. Poly-Si SiO2 90nm. SOURCE. 23-42nm 5-7nm DRAIN. Fig. 1.2 Conventional flash memory. 5-8nm. 3-4nm SiO2 SiO2. SOURCE. 90nm. Fig. 1.3 Nanocrystal memory. 4. 10-16nm 2-4nm DRAIN.

(16) Table. 1.1 Performance comparison between volatile memory (DRAM & SRAM) and nonvolatile memory (Flash, FRAM, and PCM) devices. Flash memory exhibits the best performance except the disadvantages of high programming voltage and slow program/erase speed.. 5.

(17) Reference 1.. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe´, and K. Chan, Appl. Phys Lett. 1996, 68, 1377.. 2.. C. Y. Chang, and S. M. Sze ULSI DEVICES, Wiley: New York, 2000; p. 448.. 3.. C. Kittel Introduction to Solid State Physics, Wiley: New York, 1996; p. 393.. 4.. P. C. J. Trevor, C. Y. Chang, and Y. M. L. Joseph, IEEE Electron Devices Lett. 2006, 27, 217.. 5.. T. Li, S. T. Hsu, B. D. Ulrich, D. R. Evans, Appl. Phys. Lett. 2005, 86, 123513.. 6.. T. Li, S. T. Hsu, B. D. Ulrich, L. Stecker, D. R. Evans, and J. J. Lee IEEE Electron Devices Lett. 2002, 23, 339.. 7.. K. J. Choi, M. Biegalski, Y. L. Li, A. Sharan, J. Schubert, R. Uecker, P. Reiche, Y. B. Chen, X. Q. Pan, V. Gopalan, L. Q. Chen, D. G. Schlom, and C. B. Eom, Science 2004, 306, 1005.. 8.. C. H. Ahn, K. M. Rabe, and J. M. Triscone Science 2004, 303, 488.. 9.. H. Yamada, Y. Ogawa, Y. Ishii, H. Sato, M. Kawasaki, H. Akoh, and Y. Tokura, Science 2004, 305, 646.. 10. H. Y. Fan, K. Yang, D. M. Boye, T. Sigmon, K. J. Malloy, H. F. Xu, G. P. López, and C. J. Brinker, Science 2004, 304, 567. 11. D. Y. Zhao, P. D. Yang, N. Melosh, J. G. Feng, B. F. Chmelka, and G. D. Stucky, Adv. Mater. 1998, 10, 1380.. 6.

(18) Chapter 2 Basic Theory about ferroelectric memory 2.1 Ferroelectric theory 2.1.1Ferroelectricity Ferroelectricity only occurs in some noncentrosymmetric crystal structures. Ferroelectric crystals exhibit electric dipole moments even in the absence of an external electric field. This spontaneous polarization is caused by the two thermodynamically stable positions of constituent ions in the crystal and its direction can be changed by applying an external field. In the ferroelectric state, the center of the positive charge of the crystal does not coincide with the center of negative charge, as shown in the Fig. 2-1. Many perovskite type (ABO3) materials are the commonly used ferroelectrics. The crystal structure of the perovskite such as BaTiO3 (BTO) is shown in Fig. 2-2. The Ti+4 ion is displaced at the center of the cubic, while the Ba+2 located at the corner of the cube, and the O-2 is at the face center. The obvious feature of ferroelectric materials is the response of the polarization (P) to external electric field (E). The plot of polarization versus electric field (P–E) for the ferroelectric state is referred to the hysteresis loop, as illustrated in Fig.2-3. However, the polarization can not increase without limit, it will reach a saturation polarization Ps,which corresponds to the maximum degree of domain orientation possible for that material. The coercive field EC is the reverse field to remove the polarization to zero and further increases in the reverse field lead to saturation of P in the opposite direction. At E= 0, some of the polarization will be lost, but the remnant polarization Pr is retained. The ferroelectric materials would undergo a crystallographic phase transformation from higher temperature paraelectric phase into a lower temperature. 7.

(19) ferroelectric phase. The temperature of the cubic to tetragonal or orthorhombic to rhombohedral transformation is known as the Curie point or Curie temperature, Tc. Ferroelectric materials that possess a low Curie temperatures close to the range of device operation are undesirable in reliability issues than those with high Curie temperatures, because ferroelectric materials with high Tc are less susceptible to Pr and Ec degradation. Since the response time of the ferroelectric dipole moment is the order of. nanoseconds, non-volatile random access memory called 1T-1C type. FeRAM (ferroelectric random access memory) can be realized using ferroelectric capacitors, in which two states of “0” and “1” in the binary logic are represented by the direction of the spontaneous polarization. As shown in Fig2-4[1].. Fig. 2.1 The origin of ferroelectricity of perovskite materials: Dipole created by the relative displacement of the sublattices of the cations and oxygen.. Fig. 2.2 The perovskite structure of BaTiO3.. 8.

(20) Fig. 2.3 The typical hysteresis loop (polarization to electric field) of ferroelectric materials.. Fig. 2.4 The two stable polarization state of ferroelectric materials like PZT can be defined as “0” and “1” for 1T-1C type FeRAM.. 9.

(21) 2.1.2 Ferroelectric Field Effect Transistors For the current progress of emerging nonvolatile memories such as CRAM( chalcogenide random access memory), FeRAM and MRAM( magnetic random. access memory), FeRAM is the first one in production into the electronic market. The commercialized 1T-1C FeRAM needs the ferroelectric material of the capacitor to have larger remnant polarization, which is required to produce devices with higher density. However, to maintain the minimum switching charge in the scaling ferroelectric capacitoris still the most serious problem for this type of FeRAM to survive in the future. Besides, the disadvantage of its destructive read out is undesirable for unlimited read/write cycles and ultra fast operation speed (< 20 ns). The other type FeRAM consists of a ferroelectric gate dielectric in the transistor, therefore, no additional capacitor layer is needed (Fig 2-5 (a)). The basic unit of this type FeRAM is. only one transistor, which is much smaller than the capacitor type FeRAM. In this metal/ferroelectric/semiconductor field effect transistor (MFS-FET), the surface potential is dependent on the remnant polarization of ferroelectrics. The data of this device are read by sensing the variation of surface conductivity of the silicon rather than the switching polarization state, which is seen in the1T-1C type FeRAM. The 1-T FeRAM has the following advantages compared to the 1T-1C type FeRAM:. 1. Nondestructive readout 2. Lower power consumption 3. Scaling rule is more adaptive and very high integration density 4. Simpler integration process and lower cost. 10.

(22) 2.1.3 Type of 1-T type FeRAM The first concept of MFS-FET was proposed from Bell Lab in 1957[2]. However, no such devices have been commercialized, because it is very difficult to obtain the excellent ferroelectric/semiconductor interface. As ferroelectric materials like PZT , SBT were directly deposited on silicon substrates, the chemical reaction and inter-diffusion of Pb, Bi, and Si led to very high density of surface traps in the ferroelectric/Si interface .The charge trapping and charge injection effect would degrade the data retention performance of MFS-FET seriously. In order to solve the problems of poor interface between ferroelectric and silicon substrate, many solutions have been proposed so far: 1. MFIS FET (Fig 2-5 (b)): The insulator buffer layer would be inserted between ferroelectric and Si to form a metal/ ferroelectric/insulator/semiconductor (MFIS) gate structure. It is believed that. an. insulator. layer. ferroelectric-semiconductor. can. interface. prevent. the. problems. However,. this. structure. caused causes. by series. capacitance effect so it is difficult to apply sufficient voltage on the ferroelectric thin film to switch its saturation polarization state because part of the gate bias drops on the. insulator layer. 2. MFMIS FET (Fig 2-5 (c)): Another. structure. of. ferroelectric-gate. FETs. is. the. metal-. ferroelectric-metal-insulator-semiconductor (MFMIS) structure. This concept was first proposed by Katoh/NEC in 1996[3], where metal was additionally inserted between the ferroelectric and insulator layers as a floating gate. In contrast to MFSand MFIS-FET, the ferroelectric MFM capacitor size and MIS capacitor size can be independently designed in MFMIS-FET. It is able to adjust the area ratio of. 11.

(23) ferroelectric capacitor and insulator capacitor in order to use the saturation polarization of the ferroelectric film effectively (i.e., make the ferroelectric capacitor area small). However, the additional lithography process makes the integration more complicated, and the larger insulator capacitor area violates the semiconductor scaling-down rule. 3. All Epitaxial Perovskite FET [4][5] (Fig 2-6): The use of a perovskite semiconductive oxide such as La0.7Ca0.3MnO3(LCMO), SrRuO3 (SRO) rather than Si ,which are more compatible with common ferroelectrics. To reduce the trap density under the gate, use of an epitaxial heterostructure is inevitable. Due to the excellent interface condition, the retention time of this type FeRAM is largely improved. However, the material complexity and the epitaxial process largely raise the fabrication cost.. metal. metal ferroelectric. metal. ferroelectric. ferroelectric. insulator. insulator. Si substrate. Si substrate. Si substrate. (a). (b). metal. (c). Fig. 2.5 Type of 1T-FeRAM: (a) MFS-FET (b) MFIS-FET (c) MFMIS-FET. Fig. 2.6 Schematic diagram of an all-perovskite ferroelectric FET and measurement circuit.. 12.

(24) 2.2 Ferroelectric memory mesurement The basic operation mechanism of ferroelectric-gate-controlled devices, such as. the. metal-ferroelectric-insulator-silicon. (MFIS). or. metal-ferroelectric-metal-oxide-silicon (MFMIS) field-effect transistors (FETs), is depicted in Fig. 2.7.[6][7] When the ferroelectric material is poled towards the gate electrode, positive charges are induced at the channel.. The threshold voltage of the. transistor is very large. The transistor is programmed to the ‘‘off’’ state.. On the. other hand, negative charges are induced at the channel when the ferroelectric material is poled toward the channel. The threshold voltage of the transistor is low and the device is programmed to the ‘‘on’’ state. sense. amplifier. detects. the. state. During. read. of the MFMISFET.. operation,. the. If there is a large. drain current, it is on state; if there is a small drain current, it is off state. In the previous work, we reported that interface of nc-Si/MS exhibits a novel ferroelectric-like polarization switching effect. The existence of electrical polarization in the nc-Si embedded MS structures can be revealed with polarization-electric field (P-E) measurements (See Fig. 2.8).. The remnant polarization (Pr) of Si-O. nanostructured layers in the metal-insulator-metal (MIM) configuration were found to be 3.0 μC/cm2 and is much larger than the reported values for iron-passivated porous silicon.[8] The memory window of devices is equal to 2Pr/CFE, where Pr and CFE are. 13.

(25) the remnant polarization and capacitance of ferroelectric capacitor, respectively. According to the theoretical work by Miller and McWhorter[9], an electrical polarization higher than 0.1 μC/cm2 is sufficient to switch the Si surface potential from depletion to inversion.. Ferroelectricity-induced capacitance-voltage (C-V). memory window (ΔV) can be determined from the coercive field (Ec) by ΔV=2Ec.d [10], where d denotes the thickness of ferroelectric films.. The coercive field of 700. kV/cm yields C-V hysteresis width of 9 V theoretically for Si-O nanostructured ferroelectrics of 65 nm in thickness, in accordance with measured values of 8 V (See Fig. 2.9).. It preliminary manifests the feasibility of our materials in memory. applications. In general, in transistor memory structure, low Pr can ensure positive threshold voltage at the on state and, therefore, low standby currents.[6][7]. Moreover,. increasing (decreasing) the capacitance of gate insulator capacitors (ferroelectric capacitors) increases voltage drop across ferroelectrics, while reducing the polarization filed decreases the depolarization field.[6][7]. Our Si-O nanostructured. ferroelectric thin films have smaller polarization (3 μC/cm2), a relatively large coercive field (~600 kV/cm), and lower dielectric constant (~4) in comparison with conventional perovskite ferroelectrics.. Notably, the leakage current in Si-O. nanostructured ferroelectrics was quite low (See Fig. 2.10).. 14. Therefore, the Si-O.

(26) nanostructured ferroelectric material was suitable for one-transistor memory application.. -VG. +VG. Metal ++++ + +. Metal ---- - -. ---- - -. + +++ + +. oxide Source +++++++ Drain p-Si. oxide Source. VD. p-Si. Drain VD. At low Vth state. At high Vth state. Fig. 2.7 Operation mechanism for MFMISFET (or MFISFET).. 2 kHz 1 kHz. 2. Polarization (μC/cm ). 8 4 0. -4 -8 -1500 -1000 -500 0 500 1000 1500 Electric field (kV/cm). Fig. 2.8 The existence of electrical polarization in the nc-Si embedded MS structures can be revealed with polarization-electric field. 15.

(27) 180. Capictance (pF). 160 140 120 100. 8V. 80 60 40 -12. Fig.. 2.9. -9. -6. -3 0 Gate voltage. C-V hysteresis feature of metal-oxide-silicon capacitors.. 3. 6. Si-O. nanostructured. ferroelectric. -5. Current Density (A/cm2). 10. -6. 10. -7. 10. -8. 10. -9. 10. -10. 10. -20 -15 -10. -5 0 5 Voltage (V). 10. 15. 20. Fig. 2.10 Leakage currents of Si-O nanostructured ferroelectric metal-insulator-metal capacitors.. 16.

(28) Reference: 1.. T. Mikolajick. “ The Future of Nonvolatile Memories”.. Non-Volatile. Memory Technology Symposium 2002 2.. Ross,I.M: US Patent No.2791760 (1957). 3.. E. Tokumitsu, T. Isobe, T. Kijima and H.Ishiwara Jpn. J. Appl. Phys., 40, 5576(2001). 4.. A. G. Schrott and J. A. Misewich Appl. Phys. Lett., 82, 4770 (2003).. 5.. 5. S. Mathews, R. Ramesh, T. Venkatesan, J. Benedetto. SCIENCE,. 276,. 238(1997) 6.. T. Li, S. T. Hsu, B. Ulrich, H. Ying, L. Stecker, D. Evans, Y. Ono, J. S. Ma, and J. J. Lee Appl. Phys. Lett. 79, 1661 (2001).. 7.. T. Li, S. T. Hsu, B. Ulrich, and D. R. Evans Appl. Phys. Lett. 86, 123513 (2005). 8.. Q. Chen, X. Li, Y. Zhang, and Y. Qian, Adv. Mater. 14, 134 (2002).. 9.. S. L. Miller and P. J. McWhorter, J. Appl. Phys. 72, 5999 (1992).. 10. J. P. Han, S. M. Koo, C. A. Richter, and E. M. Vogel Appl. Phys. Lett. 85, 1439 (2004). 17.

(29) Chapter 3 Experimental Details 3.1 Preparation of mesoporous silica template The films of mesoporous silica (MS) [1] were deposited on p-type silicon substrates by spin-coating.. To prepare the spin-coating solution, we first produced. an acid-catalyzed silica sol-gel by refluxing a mixture of tetraethylorthosilicate (TEOS),. H2O,. HCl,. and. ethanol. with. a. molar. ratio. of. 1:. 0.008-0.03:3.5-5.0:0.003-0.03:40 (TEOS/P123/H2O/HCl/Ethanol) at 70°C for 90 minutes. A precursor solution was then made by adding an ethanol solution of triblock copolymer Pluronic P-123 (P123) to the acid-catalyzed silica sol-gel. After the precursor solution was aged at room temperature for 3-6 hours under ambient conditions, it was spin-coated onto the substrates at 3000 rpm for 30 seconds. The film was dried at 40-60 °C for 4-6 hours, and then baked at 100-120°C for 3 hours. The resulting mesoporous silica film was used as the nanotemplate to synthesize three-dimensional array of Si nanocrystals (nc-Si). The flowchart of mesoporous silica nanotemplate films preparing is shown in Fig. 3.1.. 18.

(30) MS template preparing flowchart Precursor sol : P123/H2o/HCl 70℃, 90 min. Addition of triblock copolymer template. Aging for 3-6 hours, RT. Spin coating on Si Wafer. Drying at 40oC and baking at 110oC (Self-assembly aggregation ) Fig. 3.1 Flowchart of sol-gel procedure for preparing mesoporous silica nanotemplate films.. 19.

(31) 3.2 Synthesis of Si (or Ge) nanocrystals nc-Si was grown with a cluster-level inductively coupled plasma chemical vapor deposition (ICPCVD)[2][3] system at a base pressure as low as 10-6 torr.. After. loading MS-coated wafers into the chamber, the plasma was formed by exciting a SiH4+H2/H2 mixture with a radio-frequency electrical power of 500 W. The gas mixture was kept below 10 mtorr and the substrate temperature maintained at 250 °C during the entire process. Small size (~4 nm) and large size (~6 nm) nc-Si can be synthesized by using twelve and fifteen cycles of pulsed ICP, with a duty cycle of 1 second and 3 seconds, respectively.. The corresponding cross-sectional transmission. electron microscopy (TEM) images of pure MS film and the MS films embedded with the small- and large-size nc-Si are presented in Fig. 3.2 with the detailed growth parameters summarized in Table 3.1. The formation of high quality nc-Si inside the nanopores of the MS with pulsed plasma involves several critical steps. First of all, the pure-H2 ICP shall be used to remove organic templates of MS matrices lightly to form nucleation sites of Si-OH on the surfaces of nanopores[4] needed for a self-limiting growth reaction (SLR). The SLR is the key for atomic layer deposition.[5]. Subsequently, ICP-excited SiHn. species in the form of nanoclusters diffuse into the nanopores of MS, and then absorb on the pore surfaces. The adsorbed species eventually react with the nucleation sites of Si-OH via hydrogen-elimination reaction (HER),[4] as illustrated in Fig 3.3. SLR in cooperation with HER precisely governs the conversion of ICP-excited species bound in MS into nc-Si.. The number density of nc-Si (or nc-Ge) grown by pulsed. plasma can be as high as 2.5×1018cm-3. The resulting number density is about 5-10 times higher than that grown by steady-state plasma, where only HER is involved during the growth of nc-Si. 20.

(32) The organic contents of MS can be removed in situ by calcinatiion with H2 plasma at a flow rate of 200 sccm for 10 minutes. For device applications, a 15-nm thick SiO2 film2 was deposited with ICP CVD underneath and above the nc-Si/MS film. Since all sample preparation processes were conducted sequentially in the high-vacuum environment, the quality and characteristics of the interfaces between nc-Si and MS matrix can be accurately controlled and reproducible.. 2.46. [210]. 20nm. (a). 20nm. (b). 20nm. (c). (d). Fig 3.2 The cross-sectional TEM images of (a): pure MS film, and nc-Si/MS films with high-density of (b): small-size nc-Si, (c): large-size nc-Si prepared with twelve and fifteen cycles of pulse plasma, respectively. The inset shown in (b) reveals the lattice fringes of nc-Si. For comparison, the TEM image of nc-Si/MS film grown with steady-state plasma is also shown in (d).. 21.

(33) Conditions of Gas Supply. ICP sequence H2 step SiH4+ H2 step. steady-state plasma. steady-state SiH4(1 sccm). 15 sec. + H2(200 sccm) for 15 seconds Pulsed plasma. twelve (fifteen) cycles of pulsed SiH4(1 sccm) +. 3S. 1 3S. 1. H2(200 sccm)/ H2(200 sccm) with a duty cycle of 1 second/3 seconds. Table 3.1 Flow rate and sequence of the ICP deposition cycles used for the preparation of nc-Si/MS film.. 22.

(34) Silica pore-wall. H2 ICP. STEP A. Organic template Small size nc-Si SiH4+H 2 ICP in MS. Si. STEP B H2. (b). (a). SiH4. ICP sequence. Fig 3.3 (a)The ICP CVD system which synthesize of nc-Si (nc-Ge) in MS matrices by either pulsed or steady-state ICP and deposit of SiO2 layers by stead-state ICP. (b) Schematic mechanism of 3D Si nanodots formed by pulse ICP process.. 23.

(35) 3.3 Device fabrication 3.3.1 Capacitance fabrication Current-voltage (I-V), capacitance-voltage (C-V) characteristics of nc-Si/MS nanostructured films were studied using a metal-oxide-semiconductor (MOS) capacitor structure. The testing devices involve a composite oxide (O) layer of SiO2/nanostructured film/SiO2 stack (See Fig. 3.4).The top electrode pad of the MOS capacitor was made of an aluminum film, 250 nm in thickness and 400-μm in diameter. The back-side of the semiconductor substrate S was coated with a blanket aluminum film.. Al Al 15nm oxide nc-Si/MS 90nm 15nm oxide p-type Si Al. 0.8 mm. Fig. 3.4 The MOS structure with nc-Si/MS films. 24.

(36) 3.3.2 The fabrication of nc-Si/MS MOSFET To test the feasibility of nc-Si/MS for FeRAM technology, a MOS field-effect transistor (MOSFET) was fabricated with a 70-nm nc-Si/MS layer was used in place of the gate dielectrics. A 15-nm thick oxide buffer layer underneath and above the nc-Si/MS film was introduced to inhibit charge transport through the gate dielectric structure. Poly-Si channels on quartz substrates were formed by the green CW laser-crystallization (CLC) of amorphous silicon islands with thicknesses of 100nm, which were deposited by low pressure chemical vapor deposition (LPCVD). Gate dielectrics of nc-Si/MS. with a thickness of 100 nm together with thermally. deposited poly-Si gates with a thickness of 200 nm, are applied to form self-aligned transistors. Poly-Si gates and S/D regions were doped with PH3 (5.0x1015cm-2 and 35 keV) and activated by furnace thermal annealing (FA) for 12 h at 580 0C.[6] Fig. 3.5 shows the procedures and key facilities used for the fabrication of the test devices and the pictures of the fabricated devices.. 25.

(37) CW Laser annealing 50um. a-Si. buffer oxide Quartz wafer. poly-Si. poly gate oxide/(nc-Si/MS)/oxide Poly Si. a-Si. buffer oxide. buffer oxide. Quartz wafer. Quartz wafer G. RIE dry etching PR poly gate gate oxide Poly Si. buffer oxide Quartz wafer. Implantation. S. poly gate nc-Si Poly Si. buffer oxide Quartz wafer. D. S. S. D poly gate nc-Si Poly Si. buffer oxide. D. Quartz wafer. 50um. Fig. 3.5 The green laser-annealing system is formed of epi-like Si layers on quartz substrates and the transistor with poly Si/ SiO2/nc-Si-in-MS/SiO2 gate structure on the epi-like Si layers. 26.

(38) 3.4 Experiment Setup The system we used to measure the high ferquence capacitance is Bias Temperature Stress measurement system (BTS): Keithley 590 CV analyzer 、 Keithley 595 Quasistatic CV meter、Keithley 230 programmable voltage source、 Keithley 5951 remote input coupler and computer with ICS software installed and the I-V measurement we used HP 4156A. Fig 3.6 shows the schematic diagram of C-V measurement system.. Keithley 230 programma ble voltage source. Shielding Box. Microsco pe Probe 2. Keithley 595 Quasistatic CV meter Keithley 590 CV analyzer. Probe 1. Probe Station. Keithley 5951 remote input coupler. Fig. 3.6 The schematic diagram of C-V measurement system.. 27.

(39) References 1.. D. Zhao, P. Ya ng, N. Melosh, J. Feng, B. F. Chmelka, and G. D. Stucky, Adv. Mater. 10, 1380 (1998).. 2.. J. M. Shieh, K. C. Tsai, and B. T. Dai, Appl. Phys. Lett. 81, 1294 (2002).. 3.. J. H. Wu, J. M. Shieh, B. T. Dai, and Y. S. Wu, Electrochemical and Solid-State. 4.. Letters 7 (6), G128 (2004).. 5.. ö. Dag, G. A. Ozin, H. Yang, C. Reber, and G. Bussie`re, Adv. Mater. 11, 474 (1999).. 6.. Y. J. Lee, and S. W. Kang, Electrochemical and Solid-State Letters, 6 (5), C70 (2003).. 7. Y. T. Lin, C. Chen, J. M. Shieh, Y. J. Lee, C. L. Pan, C. W. Cheng, J. T. Peng, and C. W. Chao, Appl. Phys. Lett. 88, 233511 (2006).. 28.

(40) Chapter 4 Results and Discussions 4.1 C-V measurement The capacitor test samples were prepared by spin coating a 90-nm thick MS nanotemplate layer on p-type silicon substrate. Si nanocrystals were thereafter synthesized in the MS templates by using the high-density inductively coupled plasma (ICP) method.[1][2] During the synthesis, we applied a negative voltage of 40 V at 300 kHz on the substrate. This creates preferential growth of nc-Si on the bottom of the pore-channels with schematic shown in Fig. 4.1. The resulting one-side bonded silicon nanocrystals yield polar oriented layers of Si-O bonds.. Typical. capacitance-voltage. (C-V). characteristic. of. an. metal-oxide-semiconductor (MOS) structure with a SiO2/nc-Si-in-MS/SiO2 stack on a p-type silicon substrate and with a top circular Al pad, 400 μm in diameter, is presented in Fig. 4.2. The thickness of the nc-Si-in-MS and one oxide buffer layer is about 90 nm and 15 nm, respectively. We found two key features in this C-V measurement. First, a clockwise hysteretic loop (see the red-colored hysteretic curve in Fig. 4.2) appears in the MOS capacitor.[3][4] Note that charging (discharging) of QDs by electrons (holes) via a tunneling process can shift the flat-band voltage to a more (less) positive value.[5] This shall leads to a counter-clockwise[6] C-V loop. 29.

(41) when a positive-to-negative-to-positive voltage sweep is carried out, which contradicts with what we had observed. Secondly, the leakage current through the SiO2/nc-Si-in-MS/SiO2 stack of our samples is extremely low with a magnitude of 1.0×10-7A/cm2 at 1×106 V/cm, indicating a very low tunneling current in our samples. The ferroelectric-like nature of the clockwise C-V hysteretic loop on p-type Si substrate distinguishes clearly from that was observed with larger Si quantum dots in the same size of nanoporous MS shown by the blue-colored curves in Fig. 4.2. By growing larger Si nanodots to completely fill the cross sections of pore channels, a centrosymmetric bonding structure is achieved. The resulting C-V characteristic reveals a counter-clockwise loop. Therefore we attribute the observed clockwise C-V hysteretic curve of our MOS capacitor with one-side bonded nc-Si/MS to an electrical polarization layer.[7] Depending on the direction of the applied electric field, the built-in dipole field of the sample would either enhance or screen the external field, resulting in the observed C-V hysteretic loop with red-color shown in Fig. 4.2. A polarization-induced C-V memory window (ΔV) as large as 11.5 V was obtained.. According to the theoretical work by Miller and McWhorter,[8] an electrical polarization higher than 0.1 C/cm2 is sufficient to switch the Si surface potential from depletion to inversion. Ferroelectricity-induced C-V memory window (ΔV) can be related to the coercive field (Ec) with ΔV=2Ec.d,[7] where d denotes the thickness of 30.

(42) ferroelectric films. The C-V memory window was calculated to be about 12.6 V with a measured coercive field[9][10] of 700 kV/cm (see Fig. 2.8). This agrees reasonably well with the result shown in Fig. 4.2.. 4.2 I-V characteristics of the ferroelectric memory To test the feasibility of nc-Si/MS for FeRAM technology, a MOS field-effect transistor (MOSFET) with a 70-nm nc-Si/MS layer in place of the gate dielectrics was fabricated as illustrated on Fig. 4.1. A 15-nm thick oxide buffer layer underneath and above the nc-Si/MS film was introduced to inhibit charge transportation through the gate structure. The MOSFET with a channel length (L) of 10 μm and a channel width (W) of 10 μm was fabricated on a laser-crystallized layer of 100 nm in thickness[11] on quartz substrate. Fig. 4.3 shows the drain currents Id as a function of gate voltage Vg. The Vg was varied from -17 V to 17 V with an increment of 0.1 V while the drain voltage VD was kept constant at 0.1 V. As the Vg changed from −17 V to +17 V, the device switches from the “off” state to the “on” state with the turn-on threshold voltage at 2.2 V. On the contrary, as the Vg changed from +17 V to −17 V, the device switched from the “on” state to the “off” state with a turn-off threshold voltage of -5.2 V, yielding a memory window of about 7.4 V.[4][12] Notice that after writing the “off” state, the drain current Id is about 2.5×10−13 A at Vg=0 V. In the “on” state, the ID is about 1.34×10−5 A with a gate voltage of 0 V. The contrast ratio of the “on” to the 31.

(43) “off” state is larger than 7 orders.. Fig. 4.4 shows Id versus Vd characteristics of a 10μm* 10 μm memory device after writing to the “on” state and “off” states using a gate voltage of 17 V and -17 V, respectively. Small gate voltages of -2, -1.5, -1, and -0.5 V and a drain voltage of 0.1 V were applied to prevent any unwanted writing during reading. Drain currents of 0.36 pA, 0.19 pA, 0.14pA and 0.43 pA were measured at Vg of -2 V, -1.5 V, -1V and -0.5 V, respectively, after the device has been written to the “off” state. In contrast, drain currents of 1μA, 2μA, 4μA and 6μA were measured at of -2V, -1.5V,-1V and -0.5V, respectively, after the device was written to the “on” state. Clearly, the “on” to “off” state current ratios differ in magnitude by 7 orders, which is consistent to the versus measurement shown in Fig. 4.3. Fig. 4.5 shows the retention properties of transistors. The threshold voltage is measured as a function of time after applying writing of +17 and −17 V, respectively. The threshold voltage was measured by sweeping gate voltage from -6 to 6 V. As illustrated in Fig. 4.6.. 4.3 Discussion Two major causes of the short data retention time in FeRAM are: 1) depolarization field and 2) finite gate leakage current.[12][13] 1. Depolarization field. 32.

(44) The depolarization field is intrinsic in the ferroelectric layer. That is, the direction of. the electric field in the ferroelectric film is opposite to that of the polarization.. For the gate stack of a MFIS structure shown in Fig4.7 [13], a depolarization field always exists due to the finite compensating charge of the insulator and semiconductor. The relationship between depolarization field and the oxide capacitance can be expressed as following equation: Edp = PC F /[ε (C IS + C F )]. The CISis the capacitance of the insulator layer, and the CF and P is the capacitance and the polarization of the ferroelectrics. From the equation we can see that CIS is not infinity. There is always a finite depolarization field. This depolarization field is in the direction of reducing the polarization in the ferroelectric and tends to reduce the memory retention time. So it is suggested that in order to get a smaller depolarization field, the larger ratio of CIF/CF is necessary. Since our nc-Si/MS nanostructured material intrinsically has a low dielectric constant, the depolarization field shall not be a problem. 2. Gate leakage current and charge trapping The gate leakage current and trapping of carriers through the MFIS gate dielectric stack is another major cause of the reduced retention time. Fig. 4.8 [13] illustrates the situation where the MFIS gate stack has just been programmed such that the. 33.

(45) ferroelectric polarization induces Si-channel to inversion in the p-type semiconductor. Therefore the MFIS-FET is “on” state. This ferroelectric polarization attracts electron injection from both the gate electrode and the semiconductor side. This electron injection is followed by trapping in the gate dielectric stack, leading to local charge compensation and gradually diminished the effect of polarization. Thus, the memory retention is no longer observed after a long time. The retention time of a FeRAM device, in which the remnant polarization is Pr, leakage current I, and a trapping probability of α, can be estimated with. τ = Pr Iα .[12] Figure 4.3 shows a very low leakage current with applied voltages of 17 V. The leakage current may not affect the retention property seriously.. 34.

(46) Al SiO2. ---- - - - - - - -. S. P. ++++ ++. nc-Si/MS. +VG E. ++++++. SiO2. ---- ---. Si SiO2. D. VD. epi-like Si Quartz. Fig. 4.1 Schematic drawing illustrating the one-side bonding geometry of Si nanocrystals in porechannels prepared by applying an electric field during the. synthesis. process. (right. plot).. A. transistor. with. Al/. SiO2/nc-Si-in-MS/SiO2 gate structure on the epi-like Si layers that was activated by green laser irradiation was illustrated on the left plot.. 35.

(47) Large nc-Si. Capacitance (pF). 40 Small nc-Si 30 20. 11.5 V. 10 0 -25. -20. -15. -10. -5. 0. 5. Gate bias (V). Fig. 4.2 C-V hysteresis characteristics of a MOS capacitor containing the Si-O polar layer of nc-Si/MS capped with a 15-nm thick SiO2 buffer layer on the top and bottom (red-colored curves).. For comparison, C-V hysteresis for a MOS. capacitor with larger nc-Si to completely fill the porechannels of MS (solid and dashed curves in blue) is also presented.. Solid and dashed curves. indicate the C-V obtained with a voltage sweep from positive to negative and from negative to positive, respectively.. 36.

(48) 5 1E-5. Drain current ID(A). 1E-7. 3. 1E-8. W/L=10μm/10μm. 1E-9 1E-10. 2. 1. Gate current Ig(pA). 4. 1E-6. 1E-11 0. 1E-12 1E-13 -20. -15. -10. -5. 0. 5. 10. 15. -1 20. Gate voltage VG(V). Fig. 4.3 A ferroelectric-like switching with ultralow gate current was demonstrated with a MOSFET structure depicted in Fig. 4.1.. 37.

(49) 1E-5. read at Vg=-1V. On-state. Drain current ID (A). 1E-6. read at Vg=-2V. 1E-7. read at Vg=-0.5V read at Vg=-1.5V. 1E-8 1E-9 1E-10 1E-11. Off-state. 1E-12 1E-13 0.00. 0.02. 0.04. 0.06. 0.08. 0.10. Drain voltage VD (V). Fig. 4.4 Id versus Vd characteristics of a 10μm* 10 μm memory device after writing to the “on” state and “off” states using a gate voltage of 17 V and -17 V, respectively.. 38.

(50) 0.5 0.0 -0.5. Vth(V). -1.0 -1.5. OFF state ON state. -2.0 -2.5 -3.0 -3.5. 1. 2. 10. 10. 3. 10. Time(sec). Fig. 4.5 The retention properties of transistors. The threshold voltage is measured as a function of time after applying writing of +17 and −17 V, respectively. The threshold voltage was measured by sweeping gate voltage from -6 to 6 V.. 39.

(51) 1E-5. Drain current ID (A). 1E-6 1E-7 1E-8 1E-9 1E-10. W/L=10μm/10μm. 1E-11. Initial ON state(stress Vg=-17V) OFF state(stress Vg= 17V). 1E-12 1E-13 -6. -4. -2. 0. 2. 4. 6. Gate voltage VG(V). Fig. 4.6 The initial state and. the device after writing to the “on” state and “off”. states using a gate voltage of 17 V and -17 V, respectively.. 40.

(52) Fig. 4.7 Gate stack of the 1T-FeRAM is modeled by a ferroelectric capacitance (C ) in F. series with the semiconductor capacitance CIS , where C may be generalized to. represent the series combination of an insulating buffer on top of the semiconductor. A gate voltage V induces a polarization P and a voltage VIS across CIS. (a). (b). Fig. 4.8 (a) The MFIS-FET is in its “on” state and the electric field distribution favors electron injection toward the ferroelectric/buffer interface where some electrons are trapped in the dielectric stack and (b) sufficient electron trapping has taken place that results in diminished polarization effect ,the MFIS-FET is in its “off” state. 41.

(53) Reference: 1. A. T. Cho, J. M. Shieh, J. Shieh, Y. F. Lai, B. T. Dai, F. M. Pan, H. C. Kuo, Y. C. Lin, K. J. Chao, and P. H. Liu, Electrochem. Solid-State Lett. 2005, 8, G143. 2. J. M. Shieh, Y. F. Lai, W. X. Ni, H. C. Kuo, C. Y. Fang, J. Y. Huang, and C. L. Pan, Appl. Phys. Lett. 2007, 90, 051105. 3. C. Y. Chang, T. P. C. Juan,and Joseph Y. M. Lee Appl. Phys. Lett. 2006, 88, 072917. 4. T. Li, S. T. Hsu, B. D. Ulrich, L. Stecker, D. R. Evans, and J. J. Lee IEEE Electron Devices Lett. 2002, 23, 339. 5. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe´ , and K. Chan Appl. Phys. Lett. 1996, 68, 1377. 6. D. N. Kouvatsos, V. Ioannou-Sougleridis, and A. G. Nassiopoulou Appl. Phys. Lett. 2003, 82, 397. 7. J. P. Han, S. M. Koo, C. A. Richter, and E. M. Vogel Appl. Phys. Lett. 2004, 85, 1439. 8. S. L. Miller and P. J. McWhorter J. Appl. Phys. 1992, 72, 5999. 9. T. P. C. Juan, C. Y. Chang, and J. Y. M. Lee, IEEE Electron Devices Lett. 2006, 27, 217. 10. C. Y. Chang, T. P. C. Juan, and J. Y. M. Lee Appl. Phys. Lett. 2006, 88, 072917.. 42.

(54) 11. J. M. Shieh, C. Chen, Y. T. Lin, and C. L. Pan Appl. Phys. Lett. 2008, 92, 063503 12. T. Li, S. T. Hsu, B. D. Ulrich, and D. R. Evans Appl. Phys. Lett. 2005, 86, 123513. 13. T. P. Ma,and J. P. Han IEEE Electron Devices Lett. 2002, 23, 386.. 43.

(55) Chapter 5 Conclusions and future work 5.1 Conclusion By inductively coupled plasma chemical vapor deposition (ICPCVD), we dispersed three-dimensional dispersed Si nanocrystals (NCs) within the mesoporous silica films. ICP makes reactive species own highly mobile and bond with pore-wall well,. therefore,. efficiently. construct. 3D. Si. NCs/silica. arrays.. Material. characterizations indicated that the nanocrystals formed non-centrosymmetric bonding with the host silica matrix with highly stable interface structures, which exhibited the dipole effect at one-side bonded surfaces of Si nanocrystals with mesoporous silica matrix. The polar structure is verified by optical sum-frequency generation and P-E measurement. A remnant polarization of Pr = 5 μ C cm 2 (saturated polarization Ps = 8 μ C cm 2 ) and a polarization-induced C-V memory window (ΔV) of 15V were achieved. A MOS field-effect transistor was fabricated with a nc-Si/MS layer in place of the metal gate. Our device shows a clear polarization-induced memory window of 7.4V with very low gate leakage and high ratio of the “on” state to the “off” state, thus promises for better FeRAM nonvolatile memory devices.. 44.

(56) 5.2 Future works In this thesis, the gate structure was poly Si, the activation temperature may be cause the ferroelectric-like structure some damage. Therefore, we could use the Al gate and use the green laser activation. These process are low temperature so that preventing thermal damage about the ferroelectric-like structure.. 45.

(57)