k MS
using the high-density inductively coupled plasma
creates preferential growth of nc-Si on the bottom of
oriented layers of Si-O bonds.
2 -MS/SiO2 stack on a p-type silicon substrate and with a top circular Al pad, 400 μm in diameter, is
resented in Fig. 4.2. The thickness of the nc-Si-in-MS and one oxide buffer layer is bout 90 nm and 15 nm, respectively. We found two key features in this C-V measurement. First, a clockwise hysteretic loop (see the red-colored hysteretic curve
Fig. 4.2) appears in the MOS capacitor.[3][4] Note that charging (discharging) of Ds by electrons (holes) via a tunneling process can shift the flat-band voltage to a more (less) positive value.[5] This shall leads to a counter-clockwise[6] C-V loop
4.1 C-V measurement
The capacitor test samples were prepared by spin coating a 90-nm thic
nanotemplate layer on p-type silicon substrate. Si nanocrystals were thereafter synthesized in the MS templates by
(ICP) method.[1][2] During the synthesis, we applied a negative voltage of 40 V at 300 kHz on the substrate. This
the pore-channels with schematic shown in Fig. 4.1. The resulting one-side bonded silicon nanocrystals yield polar
Typical capacitance-voltage (C-V) characteristic of an metal-oxide-semiconductor (MOS) structure with a SiO /nc-Si-in
p a
in Q
when a positiv ed out, which ad observed. Secondly, the leakage current through the SiO2/nc-Si-in-MS/SiO2 stack of our samples is extremely low with a magnitude of 1.0×10-7A/cm2 at 1×106 V/cm, indicating a very low tunneling current in our samples.
The ferroelectric-like nature of the clockwise C-V hysteretic loop on p-type Si substrate distinguishes clearly from that was observed with larger Si quantum dots in the same size of nanoporous MS shown by the blue-colored curves in Fig. 4.2. By growing larger Si nanodots to completely fill the cross sections of pore channels, a centrosymmetric bonding structure is achieved. The resulting C-V characteristic reveals a counter-clockwise loop. Therefore we attribute the observed clockwise C-V hysteretic curve of
According to the theoretical work by Miller and McWhorter,[8] an electrical polarization higher than 0.1 C/cm2 is sufficient to switch the Si surface potential from depletion to inversion. Ferroelectricity-induced C-V memory window (ΔV) can be related to the coercive field (Ec) with ΔV=2Ec.d,[7]where d denotes the thickness of
e-to-negative-to-positive voltage sweep is carri contradicts with what we h
our MOS capacitor with one-side bonded nc-Si/MS to an electrical polarization layer.[7] Depending on the direction of the applied electric field, the built-in dipole field of the sample would either enhance or screen the external field, resulting in the observed C-V hysteretic loop with red-color shown in Fig. 4.2. A polarization-induced C-V memory window (ΔV) as large as 11.5 V was obtained.
ferroelectric films. The C-V memory window was calculated to be about 12.6 V with a measured coercive field[9][10] of 700 kV/cm (see Fig. 2.8). This agrees reasonably well with the result shown in Fig. 4.2.
4.2 I-V characteristics of the ferroelectric memory
To test the feasibility of nc-Si/MS for FeRAM technology, a MOS field-effect transistor (MOSFET) with a 70-nm nc-Si/MS layer in place of the gate dielectrics was fabricated as illustrated on Fig. 4.1. A 15-nm thick oxide buffer layer underneath and above the nc-Si/MS film was introduced to inhibit charge transportation through the gate structure. The MOSFET with a channel length (L) of 10 μm and a channel width (W) of 10 μm was fabricated on a laser-crystallized layer of 100 nm in thickness[11]
on quartz substrate. Fig. 4.3 shows the drain currents Id as a function of gate voltage Vg. The Vg was varied from -17 V to 17 V with an increment of 0.1 V while the drain voltage VD was kept constant at 0.1 V. As the Vg changed from −17 V to +17 V, the device switches from the “off” state to the “on” state with the turn-on threshold voltage at 2.2 V. On the contrary, as the Vg changed from +17 V to −17 V, the device switched from the “on” state to the “of
d g D
f” state with a turn-off threshold voltage of -5.2 V, yielding a memory window of about 7.4 V.[4][12] Notice that after writing the
“off” state, the drain current I is about 2.5×10−13 A at V =0 V. In the “on” state, the I is about 1.34×10−5 A with a gate voltage of 0 V. The contrast ratio of the “on” to the
“off” state is larger than 7 orders.
Fig. 4.4 shows I versus V characteristics of a 10μm* 10 μm memory device after writing to the “on” state and “off” states using a gate
d d
voltage of 17 V and -17 V, a drain voltage of 0.1 V were applied to prevent any unwanted
respectively. Small gate voltages of -2, -1.5, -1, and -0.5 V and
writing during reading. Drain currents of 0.36 pA, 0.19 pA, 0.14pA and 0.43 pA were measured at Vg of -2 V, -1.5 V, -1V and -0.5 V, respectively, after the device has been written to the “off” state. In contrast, drain currents of 1μA, 2μA, 4μA and 6μA were measured at of -2V, -1.5V,-1V and -0.5V, respectively, after the device was written to the “on” state. Clearly, the “on” to
“off” state current ratios differ in magnitude by 7 orders, which is consistent to the versus measurement shown in Fig. 4.3. Fig. 4.5 shows the retention properties of transistors. The threshold voltage is measured as a function of time after applying writing of +17 and −17 V, respectively. The threshold voltage was measured by sweeping gate voltage from -6 to 6 V. As illustrated in Fig. 4.6.
4.3 Discussion
Two major causes of the short data retention time in FeRAM are: 1) depolarization field and 2) finite gate leakage current.[12][13]
1. Depolarization field
The depolarization field is intrinsic in the ferroelectric layer. That is, the direction of the electric field in the ferroelectric
C C PC
E = +
film is opposite to that of the polarization.
For the gate stack of a MFIS structure shown in Fig4.7 [13], a depolarization field always exists due to the finite compensating charge of the insulator and semiconductor. The relationship between depolarization field and the oxide capacitance can be expressed as following equation:
F IS F
dp /[ε( )]
depolarization field shall not be a problem.
2. Gate leakage current and charge trapping The gate leakage current and trapping of
[13] illustrates the IS gate stack has just been programmed such that the The CISis the capacitance of the insulator layer, and the CF and P is the capacitance and the polarization of the ferroelectrics. From the equation we can see that CIS is not infinity. There is always a finite depolarization field. This depolarization field is in the direction of reducing the polarization in the ferroelectric and tends to reduce the memory retention time. So it is suggested that in order to get a smaller depolarization field, the larger ratio of CIF/CF is necessary. Since our nc-Si/MS nanostructured material intrinsically has a low dielectric constant, the
carriers through the MFIS gate dielectric stack is another major cause of the reduced retention time. Fig. 4.8
situation where the MF
ferr
The retention time of a FeRAM device, in which the remnant polarization is Pr, lea
oelectric polarization induces Si-channel to inversion in the p-type semiconductor.
Therefore the MFIS-FET is “on” state. This ferroelectric polarization attracts electron injection from both the gate electrode and the semiconductor side. This electron injection is followed by trapping in the gate dielectric stack, leading to local charge compensation and gradually diminished the effect of polarization. Thus, the memory retention is no longer observed after a long time.
kage current I, and a trapping probability of α, can be estimated with
P Ir
τ = α .[12] Figure 4.3 shows a very low leakage current with applied voltages of
17 V. The leakage current may not affect the retention property seriously.
Fig. 4.1 Schematic drawing illustrating the one-side bonding geometry of Si nanocrystals in porechannels prepared by applying an electric field during the synthesis process (right plot). A transistor with Al/
SiO2/nc-Si-in-MS/SiO2 gate structure on the epi-like Si layers that was activated by green laser irradiation was illustrated on the left plot.
SiO2
---25 -20 -15 -10 -5 0 5 0
10 20 30
40
Small nc-Si Large nc-SiGate bias (V)
Capacitance (pF)
11.5 V
Fig. 4.2 C-V hysteresis characteristics of a MOS capacitor containing the Si-O polar layer of nc-Si/MS capped with a 15-nm thick SiO2 buffer layer on the top and
ca an in fro
bottom (red-colored curves). For comparison, C-V hysteresis for a MOS pacitor with larger nc-Si to completely fill the porechannels of MS (solid d dashed curves in blue) is also presented. Solid and dashed curves dicate the C-V obtained with a voltage sweep from positive to negative and
m negative to positive, respectively.
ig. 4.3 A ferroelectric-like switching with ultralow gate current was demonstrated
-20 -15 -10 -5 0 5 10 15 20
1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
-1 0 1 2 3 4 5
W/L=10μm/10μm
Gate current Ig(pA) Drain current ID(A)
Gate voltage VG(V)
F
with a MOSFET structure depicted in Fig. 4.1.
Fig. 4.4 emory device after writing to the “on” state and “off” states using a gate voltage of 17 V and -17 V, respectively.
0.00 0.02 0.04 0.06 0.08 0.10
1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6
1E-5 read at Vg=-0.5V
read at Vg=-1V
read at Vg=-1.5V
Off-state On-state
Drain current ID (A)
Drain voltage VD (V) read at Vg=-2V
Id versus Vd characteristics of a 10μm* 10 μm m
Fig. 4.5 The retention properties of transistors. The threshold voltage is measured as a function of time after applying writing of +17 and −17 V, respectively. The threshold voltage was measured by sweeping gate voltage from -6 to 6 V.
101 102 103
-3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5
Vth(V)
Time(sec) OFF state ON state
-6 -4 -2 0 2 4 6 1E-13
1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
W/L=10μm/10μm Drain current ID (A)
Gate voltage VG(V)
Initial
ON state(stress Vg=-17V) OFF state(stress Vg= 17V)
Fig. 4.6 The initial state and the device after writing to the “on” state and “off”
states using a gate voltage of 17 V and -17 V, respectively.
Fig. 4.7 Gate stack of the 1T-FeRAM is modeled by a ferroelectric capacitance (CF) in series with the semiconductor capacitance CIS , where C may be generalized to represent the series combination of an insulating buffer on top of the semiconductor. A gate voltage V induces a polarization P and a voltage VIS
across CIS
Fig. 4.8 (a) The MFIS-FET is in its “on” state and the electric field distribution favors electron injection toward the ferroelectric/buffer interface where some electrons are trapped in the dielectric stack and (b) sufficient electron trapping has taken place that results in diminished polarization effect ,the MFIS-FET is in its “off” state.
(a) (b)
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Chapter 5 Conclusions and future work
5.1 Conclusion
By inductively coupled plasma chemical vapor deposition (ICPCVD), we dispersed three-dimensional dispersed Si nanocrystals (NCs) within the mesoporous
lica films. ICP makes reactive species own highly mobile and bond with pore-wall ell, therefore, efficiently construct 3D Si NCs/silica arrays. Material characterizations indicated that the nanocrystals formed non-centrosymmetric
onding with the host silica matrix with highly stable interface structures, which xhibited the dipole effect at one-side bonded surfaces of Si nanocrystals with mesoporous silica matrix. The polar structure is verified by optical sum-frequency
eneration and P-E measurement. A remnant polarization of si
w
b e
g Pr =5μC cm2 (saturated
olarizatio
p nPs=8μC cm2) and a polarization-induced C-V memory window (ΔV) of 15V were achieved. A MOS field-effect transistor was fabricated with a nc-Si/MS yer in place of the metal gate. Our device shows a clear polarization-induced emory window of 7.4V with very low gate leakage and high ratio of the “on” state to the “off” state, thus promises for better FeRAM nonvolatile memory devices.
la m
5.2 Future
the gate structure was poly Si, the activation temperature may be cause the ferroelectric-like structure some damage. Therefore, we could use the Al gate and use the green laser activation. These process are low temperature so that preventing thermal damage about the ferroelectric-like structure.