Motivation

Chapter 1 Introduction

1.1 Motivation

As IC technology grows up rapidly, the focus of the modern VLSI design moves from single functional block to system-level integration and single chip solution.

Because the demand of electronic product function increases, many different functional blocks are integrated into single chip, leading to increase the design complexity of system-on-chip (SoC). In the complex SoC design, it needs the various clock signals to meet the different functional block requirements. Hence, how to design the various clock generators to provide suitable clock signals for SoC applications becomes an important topic.

The design for realizing clock generator can be partitioned into analog and all-digital design approaches. Traditionally, the clock generators are realized by analog approach. However, as supply voltage decreases, both gain and frequency range need to be traded off in voltage-controlled oscillator (VCO) which is the most important block in analog clock generator. In addition, due to serious leakage current problem, it is hard to design a charge-pump circuit that is the essential block in analog clock generator in more advanced process technology. Thus it needs more design efforts to integrate analog clock generators in SoC with lower supply voltage and advanced process. Moreover, because the analog clock generator employs the passive

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components such as resistor and capacitor to form the loop filter, it induces large area and cost. Furthermore, as technology migrates, the analog blocks in clock generator need to be re-designed, leading to enlarge the design turn around time.

In contrast to analog clock generator, all-digital design approach does not utilize any passive components and use digital design approaches, making it easily be integrated into digital and low-supply voltage systems. Because all-digital clock generator is reusable as a soft intellectual property (IP), it can radically decrease time-to-market for a design and be very suitable for SoC applications as well as system-level integration. As a result, it motivates us to focus on all-digital clock generator design for SoC applications in this dissertation.

Performance and power are always the most important design considerations in SoC design. Because the all-digital clock generator controls timing discretely, the minimum controllable delay resolution should be quite high to achieve low steady-state jitter. In addition, because a large number of clock generators are to be integrated into single chip, each clock generator should have low-power characteristic to further reduce overall power consumption of system. Among the functional blocks of all-digital clock generators, digitally controlled oscillator (DCO) is the kernel module, because it dominates overall performance and power consumption of all-digital clock generator. For example, DCO occupies over 50% power consumption of all-digital clock generator [1], and the delay resolution and operating range affect jitter performance and output frequency range of all-digital clock generator, respectively. According to these design requirements, all-digital clock generators require a high-performance and low-jitter DCO. Thus, before we start to study and design all-digital clock generators, a high-performance and low-power delay cell and

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DCO that can be applied to all kinds of all-digital clock generators for SoC applications should be proposed first.

After we complete the design of a low-power DCO, the follow-up work focuses on all-digital clock generators. There are four important types of clock generators in SoC applications, namely phase-locked loop (PLL), spread-spectrum clock generator (SSCG), delay-locked loop (DLL), and synchronous mirror delay (SMD). The function and application of these clock generators are demonstrated as follows:

z PLL: It is widely used in microprocessor (µp) based and digital system [2]-[4]. It receives reference clock from the external components, for example a quartz crystal, and generates a set of system clock signals with frequency multiplication for system operation.

z SSCG: In SoC applications, the radiated emissions of system should be kept below an acceptable level to ensure the functionality and performance of system and adjacent devices, especially in high-speed serial link and video/display systems [5]. The SSCG can reduce the electromagnetic interference (EMI) effect significantly by the frequency-spreading clock and maintain the system performance [6].

z DLL: In the high-speed serial link and data transmission applications, a DLL-based multiphase clock generator generates the multiphase clocks that can be used to find a better sampling point and process data streams at a bit rate higher than internal clock frequencies to improve overall system performance [7], [8]. In addition, DLL also can eliminate the clock skew

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among different functional blocks due to large wire loading in single chip or among multiple chips.

z SMD: Memory is an essential component of SoC design. In order to eliminate the internal clock skew by wire delay mismatching, memory design needs a synchronous mirror delay (SMD), with low complexity and small area, to quickly provide a small static phase error clock as compared with the external clock [9].

The design for SoC applications not only has to achieve high performance, low power, and low complexity, but it requires high portability to migrate to other processes easily and have a short design turn around time. Hence, this work attempts to implement the proposed all-digital clock generator only with standard cells, making it easily portable to different processes and very suitable for SoC applications.