Chapter 6 All-Digital Synchronous Mirror Delay Design
6.3 The Proposed ADSMD Design
Fig. 6.2(a) illustrates the architecture of the proposed ADSMD which consists of several major functional blocks: a dummy delay line (DDL), a FDL, a MCC, a BDL, a FTDL, a phase detector, and a timing controller, and the circuit of EMDC is shown in Fig. 6.2(b) [52]. As compared with the conventional SMD, a DDL of the proposed delay-matching structure SMD contains an EMDC and a FTDL to compensate the delay of EMDC and FTDL. As a result, the total delay time is Td1 + (Td1 + Td2 +
Td3 + Td4) + (Tck - Td1 - Td2 - Td3 - Td4) + Td2 + (Tck - Td1 - Td2 - Td3 - Td4) + Td3 + Td4 = 2Tck. The locking procedure is divided into coarse and fine locking. The
coarse locking takes two clock cycles as the same as the conventional design, and the maximum phase error is the delay resolution of FDL and BDL. The remaining phase error is further reduced by FTDL controlled by 3-bit fine-tuning control code (FTC).In the fine locking, the FTC is changed every two clock cycles by the timing controller based on UP/DN from phase detector to control the delay of FTDL to align
Driving Buffer
Fig. 6.3: Block diagram and equivalent circuit of DCV.
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phase between external clock (EXT_CLK) and internal clock (INT_CLK). As a result, the entire locking procedure takes 10 clock cycles (2 + 2 x 4).
Typically, the delay resolution of FDL is one AND gate delay which is about several hundred picoseconds depending on the technology. In order to achieve high delay resolution, the proposed FTDL employs a digitally-controlled varactor (DCV)
IB_OUT
Fig. 6.4: Timing waveform (a) without blocking scheme (b) with blocking scheme.
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whose gate capacitance can be changed slightly by the FTC to change the delay of FTDL under different output loading of the driving buffer as shown in Fig. 6.3 [34].
As a result, the overall delay resolution of SMD can be improved from several hundred picoseconds to ten picoseconds.
To increase the input duty cycle range, the proposed SMD utilizes the EMDC to detect the level changing of the outputs of the successive delay cells in FDL [49].
However, based on the system requirements, the length of the FDL and BDL may need to increase to achieve the wide operating frequency range. But, it will induce more than one output of the EMDCs at logic low as the high-frequency clock propagates through the long FDL, implying SMD operation is unstable as shown in Fig. 6.4(a). The proposed blocking edge-trigger scheme uses the blocking signal (BLK), which is set to low level at the second rising edge of IB_OUT to block the clock propagation in FDL to avoid the signal conflict in MCC and ensure the SMD functionality as shown in Fig. 6.4(b).
Fig. 6.5: Microphotography of SMD test chip.
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6.4 Experimental Results
A test chip of the proposed SMD has been fabricated in 0.18µm CMOS process, where chip microphotography is shown in Fig. 6.5. The proposed design is verified by post-layout simulation using HSPICE. Fig. 6.6(a) shows the entire locking process takes ten clock cycles, and the total propagation delay of SMD is adjusted by the FTC every two clock cycles, making the phase error reduced to 15ps at 400MHz. Table 6.2 lists the verification results of phase error under different PVT conditions and input
400MHz, Duty Cycle: 80%
200MHz, Duty Cycle: 20%
200MHz, Duty Cycle: 80%
10 CLOCK Cycles
Phase Error: 15ps
(a)
400MHz, Duty Cycle: 20%
400MHz, Duty Cycle: 80%
200MHz, Duty Cycle: 20%
200MHz, Duty Cycle: 80%
(b)
Fig. 6.6: (a) Timing diagram of the proposed SMD (b) Acceptable Input duty cycle under different frequencies.
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clock frequencies. The proposed SMD can accept wide input duty cycle from 20% to 80% at different input clock frequencies as shown in Fig. 6.6(b). The performance characteristics of the proposed SMD are summarized in Table 6.3.
6.5 Summary
The performance and application scope of the conventional SMD are limited by
the low accuracy phase alignment and the narrow-pulse clock demand. In this chapter, three important design concepts of the proposed SMD are proposed: a high-resolution delay line, a delay-matching structure, and a blocking edge-trigger scheme. The
Table 6.3: ADSMD Performance Summary
Process 0.18µm CMOS
Supply Voltage (V) 1.8
Operation Range (MHz) 200 ~ 400 Input Duty Cycle Range (%) 20 ~ 80
Delay Resolution (ps) 10
Phase Error (ps) 18
Lock Time (clock cycles) 10 Power Consumption (mW) 8.7 @400MHz
Area (mm2) 0.08
Table 6.2: Phase Error Under Different PVT Conditions
SS, 1.62V, 125° TT, 1.8V, 25° FF, 1.98V, -40°
200MHz 6ps 11ps 16ps 400MHz 16ps 15ps 18ps
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proposed high-resolution delay line and delay-matching structure reduce the phase error between the external and internal clock, and the proposed blocking edge-trigger scheme extends the input duty cycle range without delay line length limitation. As a result, the proposed SMD can achieve wide duty cycle range and keep small static phase error compared with conventional designs, making it suitable for the clock synchronization in SoC applications.
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Chapter 7
Conclusions and Future Works
7.1 Conclusions
In this dissertation, a systematic all-digital design approach to implement various high performance and low power clock generators, including ADPLL, ADSSCG, ADDLL, and ADSMD, for SoC applications has been presented. The proposed DCO which is the kernel module of all-digital clock generators employs a cascadable structure with coarse and fine-tuning stage to achieve high resolution and wide frequency range at the same time. The coarse-tuning stage utilizes a segmental delay line (SDL) to reduce redundant power, and the proposed hysteresis delay cell (HDC) can reduce the circuit complexity and loading of the fine-tuning stage to further lower down the power consumption.
For the power management system application, the proposed PLL employs a novel 2-level flash TDC to reduce lock-in time with low hardware cost. Besides, in the consumer electronics, microprocessor (µP) based systems, and data transmission circuits, how to reduce the electromagnetic interference (EMI) effect is an important design topic. Based on the proposed RDTM, the spreading ratio of the proposed ADSSCG can be specified flexibly by application demands while keeping the phase tracking capability. With the proposed low-power DCO and auto-adjustment
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algorithm, the overall power consumption can be saved while keeping monotonic delay characteristic.
Double data rate (DDR) memories have been widely used for high-performance system in modern SoC designs to meet required data bandwidth. Because DDR memory controller needs specified clock and control signal to ensure the functionality and performance of data accesses, a tunable phase shift scheme based on all-digital delay locked loop (ADDLL) and digital control phase shifter (DCPS) has been proposed in this work to solve the delay mismatching issue. In addition, memory design utilizes the synchronous mirror delay (SMD) to eliminate the clock skew by wire delay mismatching. The proposed all-digital SMD (ADSMD) uses edge-trigger mirror delay cells to enlarge the input duty cycle range and fine-tuning delay lines with high-resolution delay cell to reduce the static phase error.
The proposed all-digital clock generators not only use the proposed DCO/delay cell and several design techniques to enhance performance and reduce power consumption, but also can be realized by standard cells in standard CMOS processes, making it easily portable to different processes as a soft intellectual property (IP). As a result, the proposed all-digital clock generators are very suitable for SoC applications as well as system-level integration.
7.2 Future Works
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The proposed DCO employs a cascadable structure with coarse and fine-tuning stage to achieve high resolution and wide frequency range at the same time. However, this structure has several drawbacks. First, the controllable range of each stage should be larger than the delay step of the previous stage to ensure it does not have any dead zone larger than the LSB resolution of DCO. Thus, it needs over design to meet this design constraint, leading to increase power and area. Second, the non-monotonic problem will happen when DCO control code switch cross over different tuning stages. The non-monotonic problem may induce stability issue and large jitter.
Recently, many researchers proposed the phase interpolation approach to implement a monotonic DCO design [53]-[56]. However, the phase interpolator is not only hard to obtain precise timing, but also has large power consumption. As a result, a new DCO structure should be proposed to overcome these design issues.
Furthermore, as the operating frequency of clock generator increases, we should pay more attention to several design considerations to ensure the performance and functionality. First, because the tolerance of the duty cycle variation becomes small, the clock generator should embed a duty cycle corrector (DCC) to maintain the duty cycle of clock generator output. Second, in order to achieve high operating frequency, the clock generator may utilize advanced process to implement the high-performance design. It will encounter many non-ideal design issues, such as large leakage current and heavy wire loading as chip area increased. Thus, how to design a nano-meter clock generator will be a great challenge. Third, because the design of SoC becomes more complex, the clock generator needs high immunity to PVT variations to ensure the performance and functionality. In the previous work, it only proposed a compensated solution for supply voltage variation [53]. To have more robust clock generator for high-frequency SoC applications, how to increase the immunity to PVT
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variations is an important research topic in the future. In addition to these design issues, the low-power design techniques, such as voltage-domain partition and dynamic voltage scaling, can be applied in the all-digital clock generator to further reduce power consumption.
As IC technology grows up rapidly, the computing systems and high-speed serial links require very high communications bandwidth. Currently, the data rate of serial links is higher than 5Gb/s [5], [57]. Besides, only the data signal is transmitted to save cost, and the receiver must be capable of recovering the clock and data from the received serial-data stream in the serial-data-transmission systems. Thus, the high data rate clock and data recoveries (CDR’s) which can recovery received data and clock is very important and essential for such applications.
Many high-speed CDR’s that based on PLL/DLL architecture have been proposed [58]-[60]. However, how to design and implement a high-speed CDR using all-digital approach is still a challenge. Thus, our future research will be focused on the high-speed and all-digital CDR design.
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