Chapter 3 Fast Lock-In All-Digital Phase-Locked Loop Design
3.4 Time-to-Digital Converter
3.4.1 TDC Overview
Time-to-digital converters have been widely used for measurement system, temperature sensor, and communication system [23]-[25]. Because TDC can convert the time information to digital code, it is an essential component for the interface of analog and digital signals. Many approaches have been proposed to implement a TDC [1], [23]-[25]. The counter-based TDC uses a high-frequency clock or multi-phase clock to sample the timing interval and convert to multiples of period of
D
F/F
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high-frequency sampling clock as shown in Fig. 3.5 [1]. The design concept of counter-based TDC is very straightforward, but the power consumption is very high due to the high-frequency counter design.
Another approach is the flash TDC that is analogous to flash analog-to-digital converters for voltage amplitude encoding and operate by comparing a signal edge to various reference edges all displaced in time [23], [24]. The elements that compare the input signal to the reference are usually flip-flops. In the single delay chain flash TDC shown in Fig. 3.6 (a), each buffer produces a delay equal to t. Suppose it is desired to determine the period of input clock using the eight buffers converter in Fig.
3.6 (b). Each flip-flop compares the displacement in time of the delayed the first rising edge to the first falling edge of input clock. The thermometer-encoded output indicates the value of delay time of buffer; assuming the flip-flops are given sufficient time to resolve. The drawback to this implementation is that the resolution can not be smaller than a single gate delay. In addition, when the frequency of the input clock is low, it will require numbers of flip-flops and buffers to cover large clock period, leading to suffer large power consumption and hardware cost.
In order to enhance resolution, the flash converter can be constructed with a Vernier delay line as shown in Fig. 3.7 [25]. This architecture achieves a resolution of t1- t2, where t1 >t2. However, the power and area issues still need to be resolved when the sampled clock with low frequency.
Because the proposed TDC-based ADPLL uses TDC to lock the input clock frequency coarsely, the high resolution is not the design target of the TDC. In contrast,
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how to lower the power and circuit complexity of TDC is more important design issue for the fast lock-in ADPLL application.
3.4.2 The Proposed 2-Level Flash TDC
As mentioned in the previous subsection, the single level flash TDC needs a large of flip-flops, leading to increase power consumption and design cost. In contrast to single level type, the proposed 2-level flash TDC takes only 12 D-flip-flops (8+4) as shown in Fig. 3.8, thus it has lower hardwire complexity and power consumption.
There are several functional blocks, namely a 1st level flash TDC, a 2nd level flash TDC, a delay selection multiplexer, and a period calculator. The 1st level flash TDC consists of 4 large delay cells whose delay time is eight times of small delay cell (8t) and 4 D-flip-flops. In contrast to the 1st level flash TDC; the 2nd level flash TDC has only 8 small delay cells and D-flip-flops. The small delay cells used in the 1st and 2nd level flash TDC’s remain the same as those for DCO coarse-tuning stage.
D F/F
Fig. 3.8: The proposed 2-level flash TDC architecture.
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When the TDC is enabled, Ref_N is sent to the 1st level flash TDC, and the input signal will propagate through the 4 large delay cells. When the first falling edge of Ref_N arrives, the outputs of the large delay cells will be sampled by D-flip-flops and selects one of large delay cell outputs for the 2nd level flash TDC. All outputs of D-flip-flops (Q1 [3:0]) are also sent to the thermometer-to-binary converter to generate the 1st level flash TDC output (L1_SEL). Then the 2nd level flash TDC generates the delay selection signal (L2_SEL) based on the sampled delay outputs (Q2 [7:0]). The outputs of the 1st and 2nd level flash TDC section are thermometer code type that can be used to generate selection signals easily. After both L1_SEL and L2_SEL have been generated, the period calculator can estimate the period of Ref_N based on these values. The conversion equation can be given as
Tr=(L1_SEL×8+L2_SEL)×2 (3.2)
where Tr is the period of Ref_N. For example, as shown in Fig. 3.9, if the period equals to 36 times of delay cell delay time, L1_SEL and L2_SEL should be 2 and 2 respectively. In order to reduce lock-in time, the TDC only measures half period of Ref_N, and the calculated value should be shifted left to obtain the period of Ref_N.
The TDC takes only two reference clock cycles to complete lock-in operation. From
2 Clock Cycles
Fig. 3.9: Simulation of 2-level flash TDC.
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the simulation results with 0.13µm CMOS standard cell library, the TDC resolution equals delay time of one delay cell (165ps), and the frequency error is 3.3% at 200MHz in the lock-in state.
In the proposed TDC-based ADPLL architecture, the frequency of Ref_N is the same as the frequency of DCO divided by M (DCO_M) as frequency locked. The delay time of coarse-tuning stage in DCO equals Tr divided by N. In order to reduce the hardware complexity of division, we propose a novel method to approximate this division operation results. This simplified operation can be divided into two steps.
First, if the value of division ratio (M) is the power of two, this division operation is only a shift-right operation. If not, we extract the value of power of two of MSB in M (MS) and ML (M+1). Second, the division ratio will be shifted right by MS and ML, and then the TDC output equals the average of these two values (TL and TS). For example, if M=6, MS and ML is 2 and 3 respectively. The average of the shifted
Tracking DCO control code
Average DCO control code
Fig. 3.10: Transient response of binary search ADPLL.
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value (4 and 9) equals 6. As a result, the division can be completed approximately with small hardware cost.