Introduction
1.1 Current Status and Background
Sigma-Delta A/D converters have become popular for high-resolution medium-to-low-speed applications such as digital audio [1][2], voice codec, and DSP chip.
Recently, ADCs have been applied to higher bandwidth signals, and low power designs are frequently emphasized. For example, in ×DSL [3][4] applications, signals up to several MHz must be handled. Since significantly increasing the sampling rate is difficult, designers either seek to increase the order or the cascade stages [5][6], or employ multi-bit quantization [7][8], or both, in order to achieve the required dynamic range. DAC linearity can be improved due to process technology advances, making the multi-bit architecture more popular.
The modulator design is a complex and time consuming process because many coupled design parameters must be determined. Coming up with an acceptable design is very difficult with increasing design specification demands, previously described. Even an acceptable design may not be the best one. We propose an optimization approach to increase automation and reduce complexity in the ADCs design.
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1.2 Motivation and Aims
To propose the design optimization for many structures of ΣΔ modulators, we need a complete set of important nonideality models and the power consumption model. Some issues concerning ΣΔ
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modulator noise and error modeling appeared in [1][2][9]. The performance of the ADCs is usually expressed in terms of SNR and SNDR. Circuit designers must take into consideration the nonidealities and decide the circuit and system parameters to meet the desired specifications. A design optimization procedure is proposed
in [10] to meet design specifications while minimizing power consumption. However, it didn’t consider the nonlinear distortions, so that the effectiveness of the proposed design optimization is limited. In this work, we discuss all the important nonlinear distortions, and incorporate relevant distortion powers into the optimization process in order to achieve more realistic designs.
In a ΣΔ modulator, common causes for harmonic distortions are nonlinear finite-OTA-gain, settling error, nonlinear capacitances, quantizer nonlinearity, nonlinear switch resistance and unit-DAC mismatch. Operational amplifiers (op-amps) are the critical part of the modulators and its nonidealities such as nonlinear finite-OTA-gain may produce distortions significantly.
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The nonlinear finite-OTA-gain distortion is caused by the gain variation of op-amp.
Currently, there are two major approaches for selecting op-amp DC-gains. The first approach is ad hoc based [11-13], which usually suggests setting DC-gain at a sufficiently large value, e.g. 70 dB, so that nonlinear distortion can be small enough. This can be too conservative, since the DC-gain can actually be smaller for certain applications. The other approach for selecting op-amp DC-gain requires intensive simulations and subsequent computations [9][14-15]. In this approach, time-consuming Spice simulation is first used to identify the nonlinear DC-gain curve of a specific op-amp design, and then magnitude of distortion is computed from the nonlinear curve identified. If the computed distortion is too large or too conservative (too small), the op-amp design has to be modified so that DC-gain can be adjusted. Then, one needs to carry out the aforementioned simulation and computation again. This iterative process would continue until a suitable DC-gain is determined. So the existing approaches are either not accurate enough or not time-efficient.
In this paper we propose an accurate and efficient approach for selecting op-amp DC-gain.
An essential first step in our method is the creation of a general model for nonlinear op-amp DC-gain curves. The importance of this nonlinear DC-gain model is that it eliminates the
need for time-consuming Spice simulations described above. Then, the nonlinear DC-gain curve model can be employed to analytically derive the nonlinear distortion which appears at SDM output. Since the nonlinear distortion model is expressed in terms of DC-gain and other SDM parameters, it can be used to accurately compute the minimum required op-amp DC-gain such that the nonlinear distortion is kept under a tolerable value. The nonlinear DC-gain curve model and the nonlinear distortion model are verified by transistor level simulations. Their application to sigma-delta modulators is verified by behavior simulations.
Currently, the major approaches about SDM high-level optimization used MATLAB Simulink and related power models by simulated annealing or generic algorithm [16-17] to find abestparameters combination. Although they used different algorithm to reduce the searching time, it still spent much time in behavior simulation. In existing approaches, the optimization result can’t indicate each noise power and the power consumption of each device (ex: op-amp, switch, decoder, etc), so designer is hard to analyze and correct the system. Differing with these approaches employ behavioral simulators to explore the design space, in order to find out the best combination of ΣΔ ADC architecture and circuit parameters. We proposed an optimization design for ΣΔ ADC based on analytic all typical architecture noise and power consumption with general math models. So that our model can list all noise power and each device power consumptions after each optimization. Designer can obtain the parameter they want and know how to correct the result. More importantly, our analytical models don’t have behavior simulation, so our optimization time is not dependent on system cycles, but relate to CPU clock. It will make faster than other optimization design.
In this paper, we propose an optimization algorithm based on analytical models of noises, nonlinear distortions, and power consumptions. This algorithm searches the parameter space for a design parameter combination which meets signal to noise plus distortion ratio (SNDR)
requirement while minimizing power consumption. Main purposes of this paper are to propose a complete and general set of noise, nonlinear distortion and power models on all typical architecture.