This work is organized as follows. In Chapter 2 and Chapter 3, systematic studies of fundamental theory and various architectures of ΣΔ modulator are presented first. In Chapter 4, we discuss about different architecture of non-idealities noise and distortion models of SDM. In Chapter 5, we create of a general model for nonlinear op-amp DC-gain curves. In Chapter 6, we can be employed to analytically derive the nonlinear distortion which appears at SDM output by nonlinear DC-gain curve model and we use behaving and transistor level simulation to verify our model. We discuss the design optimization between MODEL-BASED and SIMULATION-BASED in Chapter 7. A design optimization scheme is proposed in Chapter 8. It essentially combines system and circuit level designs, and optimizes all design parameters at the same time. The optimization scheme is verified in Chapter 9, and various issues are discussed. Conclusions and future works are presented in Chapter 10.
2
Fundamental Theorems of Sigma-Delta Modulators
Before we establish the error models of ΣΔ modulators, several important theorems and concepts must be known, such as Nyquist sampling theorem, quantization error and the two most critical techniques in a modulator: oversampling and noise shaping. All topologies of modulators are based on these two techniques. There also have some parameters we must to understand, such as OSR, SNR, and SNDR …etc. This chapter starts from fundamental theorems, and introduces several topologies of
ΣΔ ΣΔ
ΣΔ modulators.
We will illustrate quantization error and analyze quantization noise in an ideal A/D converter and then derives the peak signal-to-noise ratio. The resolution of an A/D converter is determined by signal-to-noise ratio, which is a very important specification in an A/D converter.
2.1 Nyquist Sampling Theorem
In an analog-to-digital converter, the analog signal from external environment must be converted to discrete-time signal by sampling. However, the sampling rate (fs) and signal bandwidth (fB) must follow the Nyquist sampling theorem in (2.1):
fS≧2fB （2.1）
The sampling rate must be higher or equal to twice of signal bandwidth in order to prevent from aliasing. We will illustrate the phenomenon of aliasing by Fig. 2.1. Fig. 2.1(a) and (b) are the spectrums of signal and sample function respectively; from fig. 2.1(c), when sampling rate is twice higher than signal bandwidth, the signal after sampling has no aliasing and it can be perfectly reconstructed by using low pass filters. However, in Fig.
2.1(d), when the sampling rate is lower than twice of signal bandwidth, aliasing will appear in the signal after sampling. The signal having aliasing is difficult to reconstruct to original signal, like Fig. 2.1(e).
(a)
(b)
(c)
(d)
(e)
Fig. 2.1 (a) Original signal spectrum (b) Sample function when fs > 2fB (c) Signal spectrum that＇ sampled by (b) (d) Sample function when fs < 2fB (e) Signal spectrum that sampled by (d)
2.2 Quantization noise and Peak SNR
We can get a discrete-time signal by sampling a continuous-time signal, and this sampled signal can be converted to digital signal. Quantization will appear in this process, the basic concept of quantization is to classify the original signal to different levels according to its level to determine the bit number of this signal, as shown in Fig. 2.2.
Fig. 2.2 Quantization process
It will have quantization error even in an ideal analog-to-digital converter. As shown in Fig .2.3, we convert the digital signal B to analog signal V1 by a D/A converter, and then the signal V1 is subtracted by input signal Vin. The result is the quantization error VQ, as in (2.2) [18].
VQ=Vin–V1 （2.2）
Fig. 2.3 Quantization error caused by A/D converter
The range of quantization error is limited in ±VLSB/2 (as in Fig. 2.4), and we assume the
probability density function of quantization error is uniformly distributed between ±VLSB/2 and its mean is zero, as shown in Fig. 2.5. From this assumption, we can easily get the quantization noise power VQ(rms)2 in (2.3).
VQ(rms)2 =
∫
−∞∞x2⋅fQ(x)⋅dx=∫
−VLSB/2 ⋅From (2.3) we can know the quantization noise power is proportional to square of VLSB, and VLSB can be represented as in (2.4). Therefore, we can say that the quatization noise will reduce by increasing quantization bit number.
VLSB = B 2
FS （2.4）
FS=Full scale = Vref+－Vref- B：Quantization bit number
Assume that input signal is sinusoidal, expressed as Vin(t) = A sinωt, so the input signal power Vin(rms)2 is as （2.5）. In （2.5）, we define the amplitude of input signal is the full scale of reference voltage, and from (2.3), (2.4) and (2.5), the peak SNR(Peak Signal-to-Noise Ratio) can be derived as in (2.6).
(2.6) is the result obtained by Nyquist sampling rate. From (2.6), we can know that each
additional bit number in quantizer increases 6dB in SNR. In Nyquist A/D converters, increasing the resolution of quantizer (decrease VLSB) while reducing the quantization noise is a general method to reach higher SNR, but this method is sensitive to mismatches of analog device. Therefore, the general Nyquist A/D converter is not easily to implement with high resolution.
2.3 Techniques of Sigma-Delta Modulator
ΣΔ A/D converters are based on oversampling and noise shaping to reach high resolution.
Oversampling means the sampling rate is much higher than Nyquist rate, about 8~512 times in general applications. The goal of oversampling is to expand quantization noise to wider range. It can reduce the quantization noise in signal bandwidth and increase the DR (Dynamic range) of input signal. Noise shaping is a technique that moves noise to high frequency, which is done by using discrete time filter and feedback technique. After noise shaping, the noise in high frequency can be filtered out by a digital filter [19].
2.3.1 Oversampling Technique
First, we made the assumption that quantization noise is a uniform distribution in sampling spectrum so its mean is zero and is a white noise [20]. The system in Fig. 2.6 just has oversampling function and does not have noise shaping effect. If a A/D converter is sampled in Nyquist rate, then the quantization noise is uniform distributed between ±fB ; if it is sampled by oversampling technique, then quantization noise is uniform distributed between± fS2/2s, which is much larger than fB. As shown in Fig. 2.7, if the signal bandwidth is between ±fB, then quantization noise in this bandwidth will be reduced by using oversampling technique, which will raise PSNR significantly.
Fig. 2.6 Sampling system
Fig. 2.7 Noise distribution after sampling
In the condition of oversampling, the PSD (Power Spectrum Density) of quantization noise is as Se2(f) in Fig. 2.7 and can be represented as:
From (2.7) we can estimate the quantization noise in 2fB after oversampling
PQ =
∫
−B ⋅ =In (2.8), we define a parameter OSR (Oversampling Ratio) as OSR =
Finally, we can get PSNR from (2.5) and (2.8)
PSNR = 10 log（
Q signal
P
P ）= 6.02B + 1.76 + 10 log（OSR） （2.10）
From (2.10), we can find that doubling OSR will increase 3dB in PSNR, which is about 0.5 bit increase in resolution. Although oversampling can reduce quantization noise, it is
difficult to reach high SNR when using a low bit quantizer. For example, if we need a 16bit A/D converter, then SNR must be equal to 98dB, if the signal bandwidth is 20KHz, then the sampling rate must equal to 2 × 109 × 20KHz, it is impossible to implement. Because at such high frequency, quantization noise is no longer a white noise, it is correlated with input signal. So there is not only oversampling technique, we must add noise shaping technique also, if we want to achieve high resolution.
2.3.2 Noise Shaping
From Fig. 2.8(a), we can derive output Y(z) as (2.11) Y(z) =
and define Signal Transfer Function STF and Noise transfer function NTF as STF (z)=
where H(z) is the transfer function of a discrete time filter. There have two important meanings in (2.12), (2.13). If we want to obtain highest SNR, STF must be equal to 1, that means the input signal can transfer to output without attenuating; and NTF (z) must be equal to 0, because the quantization noise will not affect output SNR.
In order to make NTF (z) be a high pass filter, so at DC(z = 1), NTF must be 0, and z = 1 is a pole of H(z), so the transfer function H(z) of the discrete filter is as
H(z) = 1 Z
1
− = 11 Z 1
Z
−
−
− （2.14）
Substitute (2.14) into (2.12) and (2.13), we can get STF (z) =
z
1 （2.15）
NTF (z) = z
1− （2.16） 1
And we substitute z with fs
f j2
e
π
, then we can plot STF(f)2 and NTF(f) 2 in frequency domain, as Fig. 2.9. We can find NTF(f)2 also increases with frequency, and STF(f)2 is always equal to 1, if we choose signal bandwidth in low frequency, then we can get highest signal power and lowest noise power, from this figure we see that quantization noise is moved to higher frequency significantly, this is the noise shaping effect.
2 TF(f) N
2 TF(f) S
Fig. 2.9 Noise shaping
After noise shaping, we can filter out the noise in high frequency by using digital filter, and we will illustrate its architecture more detail in the next chapter.
3
Architectures of Sigma-Delta Modulator
Before we introduce various architectures of ΣΔ modulators, we must to realize the basic architecture of a general A/D converter. Fig. 3.1 is a complete block diagram of a A/D converter [18], and we can divide it into two different parts. First part is the modulator. The main function of this part is doing oversampling and noise shaping to the input analog signal. Second part is the decimation filter. The main function of this part is to remove noise in high frequency and down sampling the sampling frequency to base band frequency.
ΣΔ ΣΔ
ΣΔ
Fig. 3.1 Block diagram of ΣΔ A/D converter
First, the input signal Xin(t) pass an Anti-aliasing filter, the 3dB frequency of this filter is about few times of Nyquist frequency, so signal and noise out of Nyquist frequency is filtered roughly, and this signal goes into the ΣΔ modulator after goes through a S/H circuit. However, in the circuits implement situation, the sample and hold function is included in the circuits of modulator, so the signal Xc(t) will pass this modulator and produces a high speed data code Xdsm(n), because of noise shaping, the quantization noise will appear in high frequency. Finally, we must filter the noise in high frequency and reduce the sampling frequency to Nyquist frequency by a decimator, and passes the digital signal to
ΣΔ
the output [18].
In this chapter, we will focus on the architectures of ΣΔ modulator, because that the noise model and optimal method is focus on this part, we must understand the theorem, benefits and drawbacks of each kinds of ΣΔ modulators. In addition, the implement of decimator is very typical [21][22]. In today’s technology, DSP processors are also used to replace decimators, so we will introduce this part roughly.
3.1 First-Order Sigma-Delta Modulator
We recall that H(z) in (2.14) is 1 1Z 1
Z
−
−
− , substitute it into Fig. 2.8, then we can get a first-order modulator; Analyze transfer function H(z) from time-domain, it indicates that output signal m(t) is obtained by adding the delayed input signal n(t-1) and the delayed output signal m(t-1), so we can express a complete first-order
ΣΔ
ΣΔ modulator as Fig. 3.2.
Fig. 3.2 First-order ΣΔ modulator
H(z) in Fig. 3.2 is indicated the effects of delay and accumulation, this is equivalent with an integrator in circuit design, so the three circuits components of ΣΔ modulator are integrator, quantizer and DAC in the feedback path.
A first order ΣΔ modulator’s output can represent as
Y(z) = z-1X(z) + (1－z-1)E(z) （3.1）
From (3.1) we can find the signal transfer function is as a delay function, and noise transfer function is as a high pass filter, moves the noise to high frequency. In order to derive PSNR of first order modulator, we must get the magnitude of NTF(z) and STF(z) in the frequency domain, so we substitute z with , and get
ΣΔ
From (2.5) and (3.5), if we have the maximum signal power, then PSNR is as (3.6)
PSNR = 10 log(
From (3.6), we find that each octave of OSR, PSNR will increase 9dB, increase 1.5 bit in resolution. Compare (3.6) with (2.10) that only has oversampling effect; we can find that 1st order noise shaping increases the performance of ΣΔ modulator.
3.2 Single-Loop Second-Order Sigma-Delta Modulator
When the discrete time filter in Fig. 2.8 is replaced by two cascade integrator, then it is a second order modulator, output of the first integrator is only connecting with the input of the second integrator, it is shown in Fig. 3.3
ΣΔ
Fig. 3.3 Single loop second order ΣΔ modulator
Then the output of it can easily be derived as
Y(z) = z-2X(z) + (1－z-1)2E(z) （3.7）
where STF and NTF is as
STF(z) = z-2 （3.8）
NTF(z) = (1- z-1)2 （3.9）
Using the same method in (3.3) (3.4), we can obtain
STF(f) =1 （3.10）
= 6.02B + 1.76－12.9 + 50 log(OSR) （3.13）
In the single loop second order architecture, each octave of OSR can increase PSNR by 15 dB, it is equivalent to 2.5 bit in resolution. If we compare (3.13), (3.11) with NTF(f) =1 that without noise shaping, as Fig. 3.4, we can find that in our needed signal bandwidth, the quantization noise is highest when NTF(f) =1, and that with second order noise shaping is smallest among this figure [18].
NTF
2 fS
Fig. 3.4 Comparison of noise shaping techniques
3.3 Single-Loop High Order Sigma-Delta Modulator
Fig. 3.5 is a single loop high order ΣΔ modulator, from the derivation in Section 3.1 and Section 3.2, we can get the quantization noise PQ in signal bandwidth is as
PQ = 2L 1
L 2 2
LSB )
OSR ( 1 1 L 2 12
V +
+ ⋅
⋅ π
，L：order （3.14）
and its PSNR is
PSNR = 6.02B＋1.76－10 log(
1 L 2
L 2
+
π )＋(20L＋10) log(OSR) （3.15）
In the application of high order ΣΔ modulator, (6L+3)dB increases in SNR when OSR is octave, so PSNR can be raised by increasing the order of the system, especially at large oversampling ratio. But sometimes in high order architecture, the performance will be
worsen than result predicted by (3.13), because of the stability problem, it will make less effective noise shaping function, so the quantization noise will not be suppressed completely.
Fig 3.5 Single-loop high order ΣΔ modulator
3.4 Interpolative Sigma-Delta Modulator
Interpolative is a kind of high order ΣΔ modulator, it changes connection of some stages, adds some feedforward paths and feedback paths in order to suppose more aggressive noise shaping effect, Fig. 3.6 is a four-order interpolative architecture ΣΔ modulator [23].
1 1
z 1
z
−
−
− 1
1
z 1
z
−
−
− 1
1
z 1
z
−
−
− 1
1
z 1
z
−
−
−
Fig. 3.6 Four-order interpolative architecture
This architecture also has stability problem, when the order L increases, each integrator produces one pole, and when the order is higher, poles of this system will also increase, and it will cause unstable situation, so the range of integrator gain will be limited; if the range of integrator gain is small, oscillation will appear in the circuits. Another is the considerations of clock control, when we use SC (switched-capacitor) to implement the integrator, each
integrator needs two clocks to control its operation, and we will need more clock to control the integrator when the order of system increases, it will produce more problems.
3.5 MASH Architecture
MASH (Multi-stage noise shaping) architecture is also called cascade architecture, which is a method that cascades several low order loops modulator in order to get high order noise shaping effect. The fundamental ideal of MASH is delivering quantization noise of front stage to input of next stage, and combining the digital outputs of all the stages with proper transfer function in digital domain, only the quantization noise of last stage will appear at the output, and the orders of NTF is the same with total orders in the cascade modulator.
Fig 3.7 is a three-order cascade
ΣΔ
ΣΔ modulator, its is the combination of a second-order and first-order ΣΔ modulator, so also called 2-1 cascade architecture.
−1
Z
−1
Z Z−1
Fig. 3.7 2-1 architecture MASH ΣΔ modulator
From Fig. 3.7, we can derive the first stage output Y1(z) can be represented as
Y1(z) = z-2X1(z) + (1－z-1)2E1(z) （3.16）
Output of second stage Y2(z) is as
Y2(z) = z-1X2(z) + (1－z-1)E2(z) （3.17）
and overall output of MASH Y(z) is as
Y(z) = H1(z)Y1(z) + H2(z)Y2(z) （3.18）
and we can say that second stage input X2(z) is almost the same with E1(z), in order to eliminate first stage quantization noise E1(z), from (3.16) ~ (3.18), we can define the error cancellation functions H1(z) and H2(z) as
H1(z) = z-1 （3.19）
H2(z) = (1－z-1)2 （3.20）
From (3.16)~(3.20), E1(z) can be eliminated, and second stage quantization noise E2(z) is shaped by third-order noise shaping function, and the MASH output Y(z) is as
Y(z) = z-3X1(z) + (1－z-1)3E2(z) （3.21）
The most significant advantage of this architecture is that stability is not an issue, because it is composed by several low-order systems, and the quantization noise will not be amplified stage by stage, so its stability is good. Most important, the noise shaping function is equivalent as high order modulator, so it is popular in recent publications [4][6].
However, there also have some drawbacks of this topology; it is sensitive to the circuits＇
imperfections, such as finite DC gain of OTA, variance of integrator gain due to capacitor mismatch and non-zero switch resistance. These are all practical considerations when we design a MASH architecture modulator [3].
ΣΔ
ΣΔ
3.6 Multi-bit Quantizer Sigma-Delta Modulator
The demands of high resolution and high bandwidth ADC are more and more in recent years. In a high signal bandwidth, OSR of ΣΔ ADC can’t be too high, and the peak SNR of a modulator with such limited OSR can’t satisfy of high resolution applications, if we use higher order architecture, then the performance will degrade due to instability. So the most general method to increase performance is to use multibit quantizer. The most
ΣΔ
obvious advantage of using multibit quantizer is that the distance between quantizer level VLSB in (2.4) is much smaller due to increasing of B, and according to (2.3), the power of quantization noise is attenuated. Fig. 3.8 is the results of theoretical peak SNR of ΣΔ modulator versus oversampling ratio, with different order and quantizer bits, it is noted that peak SNR of the same OSR is increase 6 dB with each additional bit number in quantizer, and at low OSR, low order higher bit number architecture has equivalent performance as high order architecture. This result is usable for high bandwidth applications, and the power consumption of digital circuit in ΣΔ modulator is reduced due to lower sampling rate [24].
160
0 50 100 150 200 250 300
20 40 60 80 100 120
O2B1 O2B2 O2B3 O3B1 140
OSR
SNR
Fig. 3.8 SNR vs. OSR with different quantizer bit number
Because of using multi-bit quantizer, so we also need to use multi-bit DAC(Digital-to Analog Converter) to transfer the digital output to analog signal, and feed it back to integrator. The most significant disadvantage is the non-linearities introduced by multi-bit DAC can degrade the performance of ΣΔ converter, like Fig. 3.9. It is a linear model of multi-bit modulator, where E(Q) and E(D) represent the quantization noise and feedback DAC noise respectively. The values of these capacitor elements in DAC will not equal to ideal values that we need, it is due to process variation, typical value of mismatch
ΣΔ
in modern CMOS technology is about 0.05% ~ 0.5%. In recent years, so many researches are make efforts on reduce DAC noise due to mismatch, such as trimming [19], Dynamic element matching (DEM)[8][25], although trimming is effective, but it has a expensive production step. So, DEM becomes more and more popular because of its efficiency and cheaper cost.
Fig. 3.9 Multi-bit architecture
3.7 Multi-bit Sigma-Delta Modulator use DEM Technique
Dynamic element matching is a different approach to decrease the DAC noise, it is used to improve the linearity of pure DACs [26], but now it is most used in inner DAC of multi-bit modulator. A DAC with DEM technique is illustrated in Fig. 3.10, bits thermometer code is put into the element selection logic block, and the function of element selection logic is try to select DAC elements in such way let the errors introduced by DAC average to zero for several operation periods. Because the DEM block is located in feedback loop, so its delay must be very small prevent to degrade the performance of
ΣΔ 2B
ΣΔ converter, therefore the algorithm used in the DEM block must be simple. There are several techniques of DEM, such as Randomization [27], Clocked Averaging (CLA) [26], Individual Level Averaging (ILA) [28], Data Weighted Averaging (DWA) [29], Randomization is the first approach to use DEM technique in ADC, and DWA offers a good performance to reduce DAC error, in this section, an overview introduction of these two algorithms will be presented, and the operation
ΣΔ
principle of them will be explained.
1 2B−
1 2 2B
2B
Fig. 3.10 A B-bit DAC with DEM technique
3.7.1
Randomization Technique
The main operation principle of randomization is that the element selection logic performs as a randomizer. In each clock period, the randomizer selects DAC elements randomly to generate the output of DAC. If the randomizer is ideal, then the DAC noise will become uncorrelated with each other. Simulation results show that randomization DEM technique reduces the noise floor from DAC error by several dB, but it still be a white noise in low frequency. Fig. 3.12 is the output spectrum of a second-order ΣΔ modulator with a 0.1%
capacitor mismatch, it is notable that the noise floor of randomization DEM is lower than that without any calibration technique in the feedback DAC.
3.7.2
Data Weighted Averaging (DWA)
DWA is a efficiently method to reduce DAC mismatch noise, it uses one register to
DWA is a efficiently method to reduce DAC mismatch noise, it uses one register to