A case statement implies parallel encoding. Use a case statement to select one of several alternative statement sequences based on the value of a condition. The condition is checked against each choice in the case statement until a match is found. Statements associated with the matching choice are then executed. The case statement must include all possible values for a condition or have a default choice to be executed if none of the choices match. The following examples infer multiplexors using a case statement. Refer to “Multiplexors” on page 61 for additional information about using multiplexors with the Actel architecture.
VHDL synthesis tools automatically assume parallel operation without priority in case statements. However, some Verilog tools assume priority, and you may need to add a directive to your case statement to ensure that no priority is
assumed. refer to the documentation provided with your synthesis tool for information about creating case statements without priority.
4:1 Multiplexor
The following examples infer a 4:1 multiplexor using a case statement.
VHDL
--4:1 Multiplexor library IEEE;
use IEEE.std_logic_1164.all;
entity mux is
port (C, D, E, F : in std_logic;
S : in std_logic_vector(1 downto 0);
mux_out : out std_logic);
end mux;
architecture my_mux of mux is begin
mux1: process (S, C, D, E, F) begin case s is
when “00” => muxout <= C;
when “01” => muxout <= D;
when “10” => muxout <= E;
when others => muxout <= F;
end case;
end process mux1;
end my_mux;
Verilog
//4:1 Multiplexor
module MUX (C, D, E, F, S, MUX_OUT);
input C, D, E, F;
input [1:0] S;
output MUX_OUT;
reg MUX_OUT;
always @(C or D or E or F or S) begin
case (S)
2'b00 : MUX_OUT = C;
2'b01 : MUX_OUT = D;
2'b10 : MUX_OUT = E;
default : MUX_OUT = F;
endcase end endmodule
Figure 2-13 · Multiplexor Using a Case Statement
C
F
MUX_OUT D
E MUX
S(1:0)
Datapath
12:1 Multiplexor
The following examples infer a 12:1 multiplexor using a case statement.
VHDL
-- 12:1 mux library ieee;
use ieee.std_logic_1164.all;
-- Entity declaration:
entity mux12_1 is port
(
mux_sel: in std_logic_vector (3 downto 0);-- mux select A: in std_logic;
B: in std_logic;
C: in std_logic;
D: in std_logic;
E: in std_logic;
F: in std_logic;
G: in std_logic;
H: in std_logic;
I: in std_logic;
J: in std_logic;
K: in std_logic;
M: in std_logic;
mux_out: out std_logic -- mux output );
end mux12_1;
-- Architectural body:
architecture synth of mux12_1 is begin
proc1: process (mux_sel, A, B, C, D, E, F, G, H, I, J, K, M)
begin
case mux_sel is
when "0000" => mux_out<= A;
when "0001" => mux_out <= B;
when "0010" => mux_out <= C;
when "0011” => mux_out <= D;
when "0100" => mux_out <= E;
when "0101" => mux_out <= F;
when "0110" => mux_out <= G;
when "0111" => mux_out <= H;
when "1000" => mux_out <= I;
when "1001" => mux_out <= J;
when "1010" => mux_out <= K;
when "1011" => mux_out <= M;
when others => mux_out<= '0';
end case;
end process proc1;
end synth;
Verilog
input [3:0] mux_sel;
input M;
// create a 12:1 mux using a case statement
always @ ({mux_sel[3:0]} or M or L or K or J or H or G or F or E or D or C or B or A) begin: mux_blk
case ({mux_sel[3:0]}) // synthesis full_case parallel_case 4'b0000 : mux_out = A;
Case X Multiplexor
The following Verilog example infers a multiplexor using a don’t care case x statement. Actel does not recommend using don’t care case x statements in VHDL. VHDL synthesis tools do not typically support the don’t care value as well as Verilog tools.
Verilog
//8 bit 4:1 multiplexor with don't care X, 3:1 equivalent mux module mux4 (a, b, c, sel, q);
input [7:0] a, b, c;
input [1:0] sel;
output [7:0] q;
reg [7:0] q;
Datapath
always @ (sel or a or b or c) casex (sel)
2'b00: q = a;
2'b01: q = b;
2'b1x: q = c;
default: q = c;
endcase endmodule
Decoders
Decoders are used to decode data that has been previously encoded using binary or another type of encoding. The following examples infer a 3-8 line decoder with an enable.
VHDL
library IEEE;
use IEEE.std_logic_1164.all;
entity decode is
port ( Ain : in std_logic_vector (2 downto 0);
En: in std_logic;
Yout : out std_logic_vector (7 downto 0));
end decode;
architecture decode_arch of decode is begin
process (Ain) begin
if (En='0') then
Yout <= (others => '0');
else
case Ain is
when "000" => Yout <= "00000001";
when "001" => Yout <= "00000010";
when "010" => Yout <= "00000100";
when "011" => Yout <= "00001000";
when "100" => Yout <= "00010000";
when "101" => Yout <= "00100000";
when "110" => Yout <= "01000000";
when "111" => Yout <= "10000000";
when others => Yout <= "00000000";
end case;
end if;
end process;
end decode_arch;
Verilog
module decode (Ain, En, Yout);
input En;
input [2:0] Ain;
output [7:0] Yout;
reg [7:0] Yout;
always @ (En or Ain)
else
case (Ain)
3'b000 : Yout = 8'b00000001;
3'b001 : Yout = 8'b00000010;
3'b010 : Yout = 8'b00000100;
3'b011 : Yout = 8'b00001000;
3'b100 : Yout = 8'b00010000;
3'b101 : Yout = 8'b00100000;
3'b110 : Yout = 8'b01000000;
3'b111 : Yout = 8'b10000000;
default : Yout = 8'b00000000;
endcase end
endmodule
Counters
Counters count the number of occurrences of an event that occur either randomly or at uniform intervals. You can infer a counter in your design. However, most synthesis tools cannot infer optimal implementations of counters higher than 8-bits. If your counter is in the critical path of a speed and area critical design, Actel recommends that you use the SmartGen Core Builder to build a counter. Once generated, instantiate the SmartGen counter in your design. Refer to
“SmartGen Counter” on page 71 for examples of SmartGen counter instantiation. The following examples infer different types of counters.
8-bit Up Counter with Count Enable and Asynchronous Reset The following examples infer an 8-bit up counter with count enable and asynchronous reset.
VHDL
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity counter8 is
port (clk, en, rst : in std_logic;
count : out std_logic_vector (7 downto 0));
end counter8;
architecture behav of counter8 is
signal cnt: std_logic_vector (7 downto 0);
begin
process (clk, en, cnt, rst) begin
if (rst = '0') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then if (en = '1') then
cnt <= cnt + '1';
end if;
end process;
count <= cnt;
end behav;
Verilog
module count_en (en, clock, reset, out);
parameter Width = 8;
input clock, reset, en;
Datapath
output [Width-1:0] out;
reg [Width-1:0] out;
always @(posedge clock or negedge reset) if(!reset)
out = 8'b0;
else if(en)
out = out + 1;
endmodule
8-bit Up Counter with Load and Asynchronous Reset The following examples infer an 8-bit up counter with load and asynchronous reset.
VHDL
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity counter is
port (clk, reset, load: in std_logic;
data: in std_logic_vector (7 downto 0);
count: out std_logic_vector (7 downto 0));
end counter;
architecture behave of counter is
signal count_i : std_logic_vector (7 downto 0);
begin
process (clk, reset) begin
if (reset = '0') then
count_i <= (others => '0');
elsif (clk'event and clk = '1') then if load = '1' then
count_i <= data;
else
count_i <= count_i + '1';
end if;
end if;
end process;
count <= count_i;
end behave;
Verilog
module count_load (out, data, load, clk, reset);
parameter Width = 8;
input load, clk, reset;
input [Width-1:0] data;
output [Width-1:0] out;
reg [Width-1:0] out;
always @(posedge clk or negedge reset) if(!reset)
out = 8'b0;
else if(load) out = data;
endmodule
8-bit Up Counter with Load, Count Enable, Terminal Count and Asynchronous Reset The following examples infer an 8-bit up counter with load, count enable, terminal count, and asynchronous reset.
Verilog
module count_load (out, cout, data, load, clk, en, reset);
parameter Width = 8;
input load, clk, en, reset;
input [Width-1:0] data;
output cout; // carry out output [Width-1:0] out;
reg [Width-1:0] out;
always @(posedge clk or negedge reset) if(!reset)
out = 8'b0;
else if(load) out = data;
else if(en) out = out + 1;
// cout=1 when all out bits equal 1 assign cout = &out;
endmodule
N-bit Up Counter with Load, Count Enable, and Asynchronous Reset The following examples infer an n-bit up counter with load, count enable, and asynchronous reset.
VHDL
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity counter is
generic (width : integer := n);
port (data : in std_logic_vector (width-1 downto 0);
load, en, clk, rst : in std_logic;
q : out std_logic_vector (width-1 downto 0));
end counter;
architecture behave of counter is
signal count : std_logic_vector (width-1 downto 0);
begin
process(clk, rst) begin
if rst = '1' then
count <= (others => '0');
elsif (clk'event and clk = '1') then if load = '1' then
count <= data;
elsif en = '1' then count <= count + '1';
end if;
end if;
end process;
q <= count;
Datapath
end behave;