Contacting the Customer Technical Support Center

Highly skilled engineers staff the Technical Support Center from 7:00 A.M. to 6:00 P.M., Pacific Time, Monday through Friday. Several ways of contacting the Center follow:

Email

You can communicate your technical questions to our email address and receive answers back by email, fax, or phone.

Also, if you have design problems, you can email your design files to receive assistance. We constantly monitor the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request.

The technical support email address is tech@actel.com.

phone number and your question, and then issues a case number. The Center then forwards the information to a queue where the first available application engineer receives the data and returns your call. The phone hours are from 7:00 A.M. to 6:00 P.M., Pacific Time, Monday through Friday. The Technical Support numbers are:

650.318.4460 800.262.1060

Customers needing assistance outside the US time zones can either contact technical support via email (tech@actel.com) or contact a local sales office. Sales office listings can be found at www.actel.com/contact/offices/index.html.

A

ACT 3 I/O68 Actel

web site87

web-based technical support87 Addition33

Arithmetic Operator33

Shift Register Implementation34 Assumptions5

B

Behavioral Simulation10

BREPTH68

C

Capturing a Design10 Case Statement25

,

61 Adding Directive61

CLKBUF69

CLKINT69

Coding Dual Architecture73 Instantiating74

RTL73 Structural73

Combinatorial/Sequential Module Merging55 Combining Logic53

,

Component Size48 Width48 Contacting Actel

customer service 87 electronic mail87 telephone88

web-based technical support87 Conventions5

Document5 Naming, Verilog7 Naming, VHDL6 Counter30

–

8-Bit, Count Enable, Asynchronous Reset30 8-Bit, Load and Asynchronous Reset31

8-Bit, Load, Count Enable, Terminal Count and Asynchronous Reset32

Instantiation71

Recommendations30

,

71 Critical Path Logic Reduction51 Customer service87

D

Data Shift36 Datapath24

–

Arithmetic Operator33 Counter30

Decoder29

Equality Operator35 If-Then-Else24 Multiplexor25 Relational Operator34 Shift Operator36 Decoder29

Design Creation/Verification10 Behavioral Simulation10 EDIF Netlist Generation10 HDL Source Entry10

Structural Netlist Generation10 Structural Simulation10 Synthesis10

Design Flow

Design Creation/Verification10 Design Implementation10 Programming11

System Verification11 Design Implementation10

Place and Route10 Timing Analysis10 Timing Simulation11 Design Layout10 Design Partitioning58 Design Synthesis10 Designer

DT Analyze Tool10 Place and Route10 Timing Analysis10 Device Programming11 DFPC Cell68

Division33 D-Latch13

–

with Asynchronous Reset22 with Data and Enable20

Index

Document Assumptions5 Conventions5 Organization5

Document Conventions5 Don’t Care28

DT Analyze10

Dual Architecture Coding73 Instantiating74

RTL73 Structural73

Dual Port SRAM76

,

78 Duplicating Logic56

E

Edge-Triggered Memory Device13 EDIF Netlist Generation10 Electronic mail87

,

88 Equality Operator35

F

Fanout

High Fanout Networks69

,

71 Reducing56

FIFO80

–

Behavioral Implementation80 Register-Based80

SmartGen Implementation84 Structural Implementation84 Finite State Machine37

–

Combinational Next State Logic37 Combinational Output Logic37 Mealy38

Moore41 One Hot38

Sequential Current State Register37 Structure37

Flip-Flop13

–

19 See Also Register

Positive Edge Triggered13 with Asynchronous Preset15 with Asynchronous Reset14

with Asynchronous Reset and Clock Enable19 with Asynchronous Reset and Preset16 with Synchronous Preset18

with Synchronous Reset17 FSM. See Finite State Machine

G

Gate-Level Netlist10 Generating

EDIF Netlist10 Gate-Level Netlist10 Structural Netlist10 Generics48

–

49 Greater Than34

Greater Than Equal To34

H

HDL Design Flow

Design Creation/Verification10 Design Implementation10 Programming11

System Verification11 HDL Source Entry10

I

If-Then-Else Statement24 Input-Output Buffer44

–

Bi-Directional46 Tri-State44 Instantiating

CLKBUF Driver69 CLKINT Driver69 Counters71 Dual Coding73 FIFO84

QCLKBUF Driver71 QCLKINT Driver71

RAM78

Registered I/Os68

Internal Tri-State Mapping61 Internally Generated Clock69

,

K

Less Than34

Index

Less Than Equal To34

Level-Sensitive Memory Device13 Load Reduction56

Logic Level Reduction51 Loops54

M

Merging Logic Modules55 Module Block Partitioning58 Multiplexor25

,

Case X28 Four to One26

Mapping Internal Tri-State to61 Moving Operators Outside Loops54 Twelve to One27

Multiplication33

One Hot State Machine38 Online Help8

Operators23 Arithmetic33 Equality35 Inside Loops54 Relational34

Removing from Loops54 Shift36

Table of23

P

Parallel Encoding25 Operation61 Parameters48

–

49 Partitioning a Design58

Priority Encoding24 Product Support87

–

88 Product support

customer service87 electronic mail87

,

88 technical support87 web site87

Programming a Device11

Q

QCLKBUF71

QCLKINT71

Quadrant Clock71 Limitations71

R

RAM78

Reducing Fanout56 Reducing Logic

on a Critical Path51 Usage53

Register63

See Also Flip-Flop Asynchronous Preset66

Asynchronous Preset and Clear68 Clock Enabled65

Duplication56

Functionally Equivalent Asynchronous Preset66 Placed at Hierarchical Boundaries58

Recommended Usage63

–

68 Synchronous Clear or Preset64 Register-Based

FIFO80 SRAM75

–

Dual Port76 Single Port75 Registered I/O68

BREPTH68

Related Manuals7 Relational Operator 34

Removing Operators from Loops54 Reset Signals69

,

Resource Sharing53

S

Actel Corporation • 2061 Stierlin Court • Mountain View, CA 94043 • USA

Phone 650.318.4200 • Fax 650.318.4600 • Customer Service: 650.318.1010 • Customer Applications Center: 800.262.1060

Actel Europe Ltd. • River Court, Meadows Business Park • Station Approach, Blackwater • Camberley Surrey GU17 9AB • United Kingdom Phone +44 (0) 1276 609 300 • Fax +44 (0) 1276 607 540

Actel Japan • EXOS Ebisu Building 4F • 1-24-14 Ebisu Shibuya-ku • Tokyo 150 • Japan Phone +81.03.3445.7671 • Fax +81.03.3445.7668 • http://jp.actel.com

Actel Hong Kong • Room 2107, China Resources Building • 26 Harbour Road • Wanchai • Hong Kong Phone +852 2185 6460 • Fax +852 2185 6488 • www.actel.com.cn

5029105-8/07.09 Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com.

Sharing Resources53 Shift

Single Port SRAM75 Size48

SmartGen

Counter Instantiation71 FIFO84

RAM78

SRAM75

–

79 Dual Port76 Register Based75 Single Port75

SmartGen Implementation78 Structural Implementation78 Static Timing Analysis10 Structural Netlist Generation10 Structural Simulation10 Subtraction33

Synthesis10

Reducing Duration of58

T

Technology Independent Coding13

–

49 Technology Specific Coding61

–

86 Timing

Analysis10 Constraints51 Simulation11 Tri-State Mapping61 True/False Operands35

U

Unit Delays10

V

Verilog

Naming Conventions7 Reserved Words7 VHDL

Naming Conventions6 Reserved Words6

W

Web-based technical support87 Width48

在文檔中 VHDL使用手冊 (頁 87-92)