N‐Type  Poly‐Gate

Channel

NC

Oxide Oxide

N‐Type  Poly‐Gate

Channel

Figure 4-14 Band diagram with nanocrystal in trapping layer (top) programming (bot) store.

46 

Chapter 5

Conclusion

In this work, multi-channel gate-all-around non-volatile memory devices have been proposed. The performance of device is improved by Multi-channel structure, and also the strength of nanowires without buried oxide layer is reduced seriously; nevertheless, gate-all-around structure must construct on these stylish nanowires. The profile of nanowires is highly depending on source/drain length due to stress. Decreasing source/drain length is an important parameter to keep nanowires be Gaussian profile, and that is compatible for gate-all-around device fabrication.

On the other hand, the dual gate-all-around (DGAA) structure device is a good candidate for non-volatile memory application compared with single gate-all-around (SGAA), particularly, its high reliability and performance are observed. And depending on types of strained nanowires between SGAA and DGAA, the profiles of nanowires are crucial phenomenon on physical characteristics. The performance enhanced relate to compressive stress DGAA device with strong dielectric strength. Moreover, the retention and endurance only degrade 17% and 26% compared with that of failed tensile stress SGAA devices. Hence, the profiles of nanowires poly-S impact the characteristics of memories intensely. In addition, the design of device can be improved scaling down by advanced lithography, and the performance of

47 

non-volatile memory device is also improved. Simultaneously, the stress effect on the nanowires is reduced, and the complexity of processes is also lower.

This investigation would examine the nanowires poly-Si thin-film-transistor memories on future active matrix liquid crystal display system-on-panel and three-dimension stacked high-density applications.

48 

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