Characteristics Analysis

Figure 4-2 presents top-view of a dual-gate structure nanowires non-volatile memory device, and scanning electron microscopy image confirms channel length is about 2.5 um for each gate (G1 and G2). In addition, the spacing between G1 and G2 is about 1.5 um. Figure 4-3(left) shows the cross-sectional the nanowires channel along of AA’ line transmission electron microscopy image of each nanowire. The poly-Si nanowire channel was surrounded by Oxide/Nitride/Oxide structure and N⁺ poly definitely, that the physical width is 120 nm and the height is 40 nm of rectangular-shape channel.

Figure 4-3(right) is a high-resolution (HR) transmission image that indicates practical ONO structure including the engineered charge trapping layer with nanocrystals which dimensions are about 5 nm; therefore, nanocrystals can be formed by a suitable anneal recipe in Nitride/a-Si/Nitride structure certainly.

Multi-channel devices have excellent characteristics in thin-film-transistor [4-1]. For non-volatile memory application, various devices have been fabricated as table 4-1. Totally, there are four different channel numbers to analysis: (1) S1; (2) M3; (3) M5; (4) M10. Figure 4-4 shows Id-Vg transfer characteristic after programming with positive bias 12 V for 1 ms. The memory windows of all devices increase depending on more channel numbers as

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shown in Figure 4-5, since the channel edge and corner effect enhance electrical field to increase programming efficiency. However, even multi-channel devices have an advantage of large memory windows, but leakage current also increases due to electrical stress in dielectric. For long period operation, reliability issues will occur easily. Thus, the channel numbers must be modified. That leakage current can’t increase too much and enough memory windows exist. These parameters are to be optimized.

Figure 4-6 shows Id-Vg characteristics of Dual Gate-all-around (DGAA) (Lg = 2.5 × 2 um) and Single Gate-all-around (SGAA) devices (Lg = 5.0 × 1 um) in initial and programmed states. Both cells have a few threshold voltage differences with positive pulse 12 V for 1 ms, and the leakage current of DGAA is still suppressed obviously after programming. The channel of DGAA structure is under compressive stress, and the SGAA is at tensile stress. At the tensile region, the higher leakage current of SGAA structure appears, since the dielectric induces more damages than compressive stress. Hence, the type of stain alters dielectric properties that shown in characteristics of the devices.

Figure 4-7 shows program and erase (P/E) characteristics, which exhibits high performance in program and erase operations. Applied positive programming voltages are from 10 V and 14 V, and the negative erasing voltages are also the same level. In low voltage P/E operation, sustained memory window is large enough to distinguish program and erase level. The electrical field will be enhanced by corner effect, increasing the P/E efficiency through FN tunneling mechanism. On the other hand, the SGAA structure fails in specific operation condition of DGAA. The concave-profile isn’t appropriate for film deposition, and it causes the dielectric strength become weaker than Gaussian-profile.

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The result explains SGAA with weaker dielectric breakdown easily. Figure 4-8 shows retention characteristics, and the memory window of DGAA is 83%

maintenance after ten-year; nevertheless, the memory window of SGAA is only 54%. These distinct effects from structure differences due to varied dielectric strength. The electrons loss easily from the charge trapping layer in SGAA structure since the dielectric with tensile stress is difficult to maintain electrons compared with compressive stress. Figure 4-9 indicates endurance characteristics with DGAA and SGAA. The memory window of DGAA is 74%

after 10⁴ cycles, but SGAA structure fails under only 100 times cycles and smaller memory window. As P/E discussed, the tensile stress induces weaker dielectric strength, and the SGAA devices are easy to breakdown after a few numbers of P/E cycles. All these results demonstrate the different strained NWs profiles lead to alter characteristics of devices. The deformed NWs with compressive stress perform a better dielectric deposition and properties to improve the performance of NVM, especially DGAA structure shown better characteristics.

For dual gate-all-around non-volatile memory devices, there are an amount of advantages compared with single-gate structure. The following discussions are just focus on its performance. Figure 4-10 shows the P/E characteristics with various pulse widths at different gate bias conditions. A large memory window of 3 V at a gate bias of 14 V for 100 us can be achieved for dual-gate GAA NWs NVM, so this device can be low power and high speed application. Figure 4-11 indicates excellent P/E speed of various channel length. The dual-gate device can be scaling down further to achieve high-density applications with high performance. Figure 4-12 presents the read

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disturb of the dual GAA NVM device with two read conditions. For gate voltage 1.8 V and drain voltage 0.5 V, the Vth appears stable in programmed and erased states. For more strict condition, drain voltage increasing to 3.0 V, the Vth still maintains stable without voltage shift. The reliability of DGAA is also improved such as retention and endurance. This is contributed by the charge trapping layer engineering due to charge confinement in the deep quantum well. There are additional states in trapping layer to store charge, and it is hard to loss in equilibrium condition. Consequently, this type of non-volatile memory has much attractive for future applications.

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S D

G

Figure 4-1 The three-dimension schematic of a dual gate-all-around non-volatile memory device and its process flows.

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A’

A

Figure 4-2 (left) Top view of a dual-gate nanowires thin-film-transistor non-volatile memory. (right) Scanning electron microscopy image of top view.

Figure 4-3 (left) Transmission electron microscopy cross section image corresponding to figure 4-3(left), in the AA’ direction. (right) High-resolution transmission electron microscopy image.

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Table 4-1 Various non-volatile memory devices with different channel numbers and its scale dimension.