Chapter 2 Characteristic of Cobalt -Silicide Nanocrystals Memories
3.4 Summary
From above-mentioned experiment, it is found that the quality problem of control oxide layer, and it will cause gate injection phenomenon. The hysteresis will be clockwise due to gate injection. The gate injection will make the retention and endurance inferior. The quality of PECVD TEOS oxide is unstable, so it is necessary that the annealing temperature and time are well controlled. Steam oxidation is practicably, too.
Chapter 4
Novel design of Cobalt -Silicide Nanocrystals Structures with Nanosphere Template Technology
4.1 Introduction
It is interesting that the different of the characteristic relate to the arrangement mode of nanocrystals. For obtaining well-order 2-D array nanocrystals, the macromolecule nanosphere template technology will be utilized. First, we deposit a thin metals or semiconductors on the nanosphere template made of polymer. The metals or semiconductors initially tend to cluster together at inter-particle spacing between nanosphere templates. By dissolving the nanosphere template, the periodically arranged semiconductor or metal nanocrystals will be produced. The devices with regular arrangements of nanocrystals will also be made Moreover, the comparison in electrical properties between random and regular arrangements of nanocrystals in space will be characterized.
4.2 Experimental procedures
There are eight steps must be done in proper sequence. The first step, single-crystal 6 inch (100) oriented p-type silicon was cleaned with standard RCA recipes. The
standard RCA clean process was immersed in the HCl bench at 120℃ for 10 minutes (called SCΙ process). Next, the wafers were cleaned with NH4OH at 120℃ for 10 minutes (called SCⅡ process). The last was dipped in HF a few seconds. Second, the wafer was followed by dry oxidation in the atmospheric pressure chemical vapor deposition (APCVD) furnace to form 3.5nm-thick dry SiO2 layer as tunneling oxide.
Third, after the growth of tunnel oxide, the solution with macromolecule nanosphere, methanol and triton will be spun on the substrate with 3.5nm tunnel oxide to form the nano-template, shown as Diagram 4.2-1. Forth, the cobalt will be deposited in the interval of the nanosphere by Dual E-Gun Evaporation System (E-Gun). The deposition rate of the E-Gun was relied on adjustment of the current magnitude by a remote control. Not the rate magnitude but the current magnitude must be more exact because of the deposition thickness of cobalt film was the critical process to determine the size of the nanocrystals and the memory effect. Fifth, the sample was immersed in toluene to purge the macromolecule nanosphere template, and the cobalt dots would be stayed, shown as Diagram 4.2-2. Step six is the thermal treatment, a metal rapid thermal annealing (Metal - RTA) in N2 ambient was performed to form the Co nanocrystals. The total energy of the metal film is reduced when the metal surface area is minimized by forming discrete, roughly spherical nanocrystals. Therefore, the N2 Metal - RTA process transformed the Co layer and a-Si thin film layer to the Co spherical nanocrystals. This mechanism is called “self-assembled”. Next, the TEOS oxide 400Å was deposited on the Co nanocrystals by PECVD with reactant gases of TEOS flow 10 sccm mixed in Hydrogen plasma at 300℃. This step also was the critical process because it was related to retention and endurance characteristics. After this step, the micro-structure of sample was analyzed by Transmission Electron Microscope (TEM). The TEM figures can be more powerful evidence to confirm the shape of the nanocrystals. Finally, the Al electrode 5000Å was patterned and coated
by thermal evaporation coater. The complete experimental procedure for cobalt-silicide nanocrystals is shown in Figure 4.2-3. Subsequently, this metal insulator semiconductor (MIS) structure with Co nanocrystals embedded in dioxide was fabricated, and has prepared for electrical analyses. The Capacitance-Voltage measurement was analyzed the memory effect of the nanocrystal memories by HP4284A Precision LCR Meter.
4.3 Results and discussions
Figure 4.3-1 represents the plan-view of the sample after purge the macromolecule nanosphere template. The triangles of cobalt that be deposited in the interval of the nanosphere was observed clearly. Figure 4.3-2(a) and Figure 4.3-2(b) represents the plan-view of the sample after annealing. It was found that cobalt dots after annealing were not well-separated and the shapes were not perfect, shown as Figure 4.3-2(a).
The problem of cobalt dots was due to the annealing temperature and time. If the annealing temperature and time are well controlled, the shape of nanocrystals can be improved. It could be proved in Figure 4.3-2(b). The well -separated and spherical cobalt nanocrystals deposited on the oxide layer were clearly observed after
regulating the annealing temperature and time. It indicated that the feasibility of this novel method.
The electrical characteristics as illustrated in Figure 4.3-3 and Figure 4.3-4 is the capacitance -voltage (C-V) measurement of the samples annealing at 400℃ 60sec.
The capacitance -voltage characteristics are quite bad. There is almost no hysteresis in the figure, and even the curve is confused. This reason is considered that the cobalt
dots might be damaged when cleaned the macromolecule nanosphere template. The quality of the PECVD TEOS oxide layer was not good enough is a problem. This deficiency would make to some defects and fixed charges in the oxide layer. The memory effect may be improved by steam oxide deposited by PECVD. If the annealing temperature and time are well controlled, the memory effect can be improved, too.
4.4 Summary
As the Figure 4.3-2(b) shown, it was demonstrated that the novel design with macromolecule nanosphere template is feasible. The well-order 2-D array
nanocrystals were obtained. If the annealing temperature and time are well controlled, the shape of nanocrystals can be improved. But the capacitance -voltage
characteristics as illustrated in Figure 4.3-3 and Figure 4.3-4 are quite bad. So many unknown problems are existence. If the experimental conditions such like annealing temperature and time are well controlled, the memory effect will be improved.
However, this experiment still has great contribution for the fundamental research of the nanocrystals nonvolatile memory with macromolecule nanosphere template.
Chapter 5
Conclusions and Suggestion for Future Work
5.1 Conclusions
In this thesis, it focuses on the applications of nanocrystals for the novel
nonvolatile memory devices, and their relevant physical characteristics. Nanocrystals of cobalt silicide and cobalt as the idea of storage unit of memory device are first proposed. Cobalt and cobalt-silicide as the materials for the nanocrystals is the
compatibility with current manufacturing technology of semiconductor industry. From above-mentioned experiment, the structure of cobalt silicide nanocrystals was
fabricated successful. It is found that the cobalt-silicide nanocrystals had diffusion phenomenon in both the tunnel oxide and control oxide in the Dry Oxide/Cobalt/
Amorphous Silicon structure, and it is more serious that the diffusion phenomenon in control oxide than tunnel oxide, The diffusion phenomenon caused the capacitance -voltage characteristics of those three conditions are rather poor, and retention time and endurance are reduced. In order to restrain the diffusion phenomenon, we suggested the other two structures. First one, the Dry Oxide/Cobalt/amorphous Silicon/Silicon Dioxide/ Amorphous Silicon structure is founded that diffusion phenomenon was restrained successfully by the silicon dioxide layer between those two amorphous silicon layers, as seen in this TEM image. In all experimental conditions, it shows that oxidation at 800℃ for ten minutes has better characteristic according to the observable C-V shift. A lower programming voltage of 3V actualize a
significant threshold voltage shift, 0.8V, which is sufficient to be defined as “1” and
“0” by a typical sense amplifier for a memory device. The other one was suggested to avoid the diffusion phenomenon of cobalt silicide. A pronounced capacitance-voltage hysteresis was observed, but the hysteresis was imperfect distinctly. It showed the quality of the PECVD TEOS oxide layer was not good enough. The cobalt
nanocrystals structure had the same problem about the quality of control oxide layer, and it caused gate injection phenomenon. The hysteresis was clockwise. The gate injection will make the retention and endurance inferior. It is necessary that the annealing temperature and time are well controlled to improve the quality. Steam oxidation is practicably, too.
It was demonstrated that the novel design with macromolecule nanosphere template is feasible. The well-order 2-D array nanocrystals were obtained. But the capacitance -voltage characteristic was quite bad. So many unknown problems are existence. If the experimental conditions such like annealing temperature and time are well controlled, the memory effect will be improved.
5.2 Suggestion for Future Work
We hope that the fundamental research of the nanocrystals can be further investigated by series of experiments and analyses, and application on electric element and technology development. Metal nanocrystals have different work
function to select as the memory storage medium such Au, Ag, Pt, W, Co and Ni. The different metals have different work function to lead to the different range of the memory window. It can be find a condition of the process to improve the metal
nanocrystals distribution. The contaminate of the metal will solve by regulating the conditions or replacing the dielectric metals.
The future work of this proposal is to integrate the all kinds of nano-dots (semiconductor, oxidized semiconductor, metal, metal-silicide and magnetic nanocrystals) with the novel nano-wire thin-film transistor. The novel nano-dots embedded in nano-wires nonvolatile memory has not only excellent gate control due to nano-wire channels, but also advantage of nano-dot memory properties. Such novel nano-dots embedded in nano-wires nonvolatile memory is expected to have best performance, including a low operation voltage, low power consumption, a high retention time, a high reliability, and the “multi-bit” memory property.
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Note
Chapter 2:
<2.1> The above-mentioned two steps must be carefully because HCl and NH4OH will cause the react to produce the NH4Cl which will be harmful to health.
<2.2> In this step, both side of the Si wafer all need not adhered the water.
<2.3> The equipment of the APCVD furnace was place at the clean room (class 10) in the National Nano Device Laboratories (NDL). We chose the sixth tube - Dry Oxidation, and set up the parameters about “Dry Oxide 50”. There are some tips we should know, as the process began, we can leave until the “Boat In” step was completed. But we must wait until the vacuum pressure was arrived for the Low pressure chemical vapor deposition (LPCVD) furnace. Before the end of the auto processes about 30 minutes ago, we must be remember come back to confirm all conditions were fine.
<2.4> However, the current and the deposition rate usual were different due to the position of the electron beam aimed at the target may cause the error. So we must be surely the position as the deposition beginning.
<2.5> This step was prepared by the “Co silicidation” tube of the Oxidation and Diffusion Furnaces which belonged to the Nano Facility Center of the National Chiao Tung University in the clean room (class 10k). We can set up the auto
raising temperature to arrive at the setting temperature. When the faceplate was appeared “E”, it meant the end of raising temperature, we just began to calculate the oxidation time. Because we must change “Ni silicidation” tube from medium position to below position, we need inquire for the operator and make an announcement. Until the procedures were complete, we can turn off the power switch to wait the temperature drop about six hours ago. Then, we can change the tubes and wait the condition stability to take about six hours.
The oxidation process was demanded for infusing into the oxygen gas so we need exchange N2 for O2 gas. The gas exchange sequences were list as below.
Oxidation
<2.6> This step was prepared by Metal Rapid Thermal Annealing (Metal-RTA) in the clean room (class 10). To fit the annealing temperature, we must try several times until correcting to our normal temperature. The fitting parameters are shown in as below. It may be different with different thickness or different specific heat. We suggest that the test before experiment is necessary.
Temp. Ramp T-SW Gain D-G I-W,I-C
900℃ 90 50 -60 -6 4196
800℃ 90 20 -50 -5 2997
500℃ 60 20 -50 -5 1026
450℃ 70 20 -50 -5 1426
400℃ 70 40 -50 -5 403
<2.7> The Plasma Enhanced Chemical Vapor Deposition (PECVD) is in the clean room (class 10K). We chose the chamber 2 to deposited TEOS oxide by setting up the recipe “TEOS 400”. As the process was started to the “gas stabilization” condition, we can press “F2” to hold this process until the TEOS flow was stable in the setting value. Before the deposition process began, we always done the clean process to make chamber spotless.
Control Gate
Poly-Si floating gate
Source Drain
Dielectric Dielectric Si-substrate Control Gate
Poly-Si floating gate
Source Drain
Dielectric Dielectric Si-substrate
Figure 1.1-1 The structure of the conventional floating gate nonvolatile memory device. Continuous poly-Si floating gate is used as the charge storage element.
Control Gate Nitride layer
Source Drain
Dielectric Dielectric Si-substrate Control Gate
Nitride layer
Source Drain
Dielectric Dielectric Si-substrate
Figure 1.1-2 The structure of the SONOS nonvolatile memory device. The nitride layer is used as the charge-trapping element.
Poly-Gate
Source Drain
Poly-Gate
Source Drain
Figure 1.1-3 The structure of the nanocrystal nonvolatile memory device. The semiconductor nanocrystals or metal nano-dots are used as the charge storage element instead of the continuous poly-Si floating gate.
Figure 1.1.1-1 The energy band diagrams of the write/erase operation for a nanocrystal NVSM device.
e
-e
-Write
Erase
Gate
Gate
Tunneling oxide Control oxide
nanocrystal
+V
-V
Figure 1.1.2-1 The development of the gate stack of SONOS EEPROM memory devices. The optimization of nitride and oxide films has been the main focus in recent years.
Figure 1.1.3-1 band diagram illustration of different approaches for improving the Jg,programming/erase/Jg,retention ratio.
CS1 01 02 03 04 05 06
Table 2.2.1 Experimental parameters of the Dry Oxide/Cobalt/amorphous Silicon Structure.
Figure 2.2.1 Process flow of the Dry Oxide/Cobalt/amorphous Silicon Structure.
CAOS 01 02 03 04 05 06
Table 2.2.2 Experimental parameters of the Dry Oxide/ Cobalt /amorphous Silicon/ Silicon Dioxide/amorphous Silicon Structure.
tunnel oxide Co
Figure 2.2.2 Process flow of the Dry Oxide/ Cobalt /amorphous Silicon/ Silicon Dioxide/amorphous Silicon Structure.
CAO 01 02 03 04 05 06
Table 2.2.3 Experimental parameters of the Dry Oxide/ Cobalt /amorphous Silicon/TEOS Oxide Structure.
Figure 2.2.3 Process flow of the Dry Oxide/ Cobalt /amorphous Silicon/TEOS Oxide Structure.
.
Figure 2.3.1-1(a) Standard of the Dry Oxide/Cobalt/amorphous Silicon Structure before oxidation.
Figure 2.3.1-1(b) The Dry Oxide/Cobalt/amorphous Silicon Structure after oxidation at 900°C 10min.
Figure 2.3.1-2(a) The C-V hysteresis loop of cobalt-silicide nanocrystals in samples oxidized at 900°C 10min.
Figure 2.3.1-2(b) The C-V hysteresis loop of cobalt-silicide nanocrystals in samples oxidized at 900°C 10min.
-8 -6 -4 -2 0 2 4 6 8
Figure 2.3.1-2(c) The C-V hysteresis loop of cobalt-silicide nanocrystals in samples oxidized at 850°C 10min.
Figure 2.3.1-2(d) The C-V hysteresis loop of cobalt-silicide nanocrystals in samples oxidized at 800°C 10min.
Figure 2.3.2-1 The Dry Oxide/ Cobalt /amorphous Silicon/ Silicon
Dioxide/amorphous Silicon Structure after oxidation at 800°C 10min.
Figure 2.3.2-2(a) The plan-view TEM image of Dry Oxide/ Cobalt /amorphous Silicon/ Silicon Dioxide/amorphous Silicon Structure after 800
°C oxidation.
Figure 2.3.2-2(b) The size distribution of the nanocrystals.
Size of Nanocrystal (nm)
2 4 6 8 10
Number of Nanocrystala
0 10 20 30 40 50
Figure 2.3.2-3(a) The C-V hysteresis loop of cobalt-silicide nanocrystals in
samples oxidized at 800°C 10min with 6V programming voltage.
b6-6
Figure 2.3.2-3(b) The C-V hysteresis loop of cobalt-silicide nanocrystals in samples oxidized at 800°C 10min with 3V programming voltage.
b6-3
Voltage (V)
-3 -2 -1 0 1 2 3
C/ Cox
0.0 0.2 0.4 0.6 0.8 1.0 1.2
(+3V) ~ (-3V)
(-3V) ~ (+3V)
Figure 2.3.2-4 The band diagrams of “write” and “erase” operations of the memory device.
Control gate
+V Write
Si-substrate SiO2
CoSi2
e
-SiO2 e
-CoSi2
Si-substrate Erase
-V Control
gate
Figure 2.3.3-1(a) The C-V hysteresis loop of cobalt-silicide nanocrystals in samples annealing at 800°C 100sec with 8V programming voltage.
CAO 04 e5-8
Voltage (V)
-8 -6 -4 -2 0 2 4 6 8
C/Cox
0.0 0.2 0.4 0.6 0.8 1.0 1.2
(+8V) ~ (-8V)
(-8V) ~ (+8V)
Figure 2.3.3-1(b) The C-V hysteresis loop of cobalt-silicide nanocrystals in samples annealing at 800°C 100sec with 10V programming voltage.
CAO 04 e5-10
Voltage (V)
-10 -5 0 5 10
C/Cox
0.0 0.2 0.4 0.6 0.8 1.0 1.2
(+10V) ~ (-10V) (-10V) ~ (+10V)
Figure 3.1-1 Self-assembled phenomenon of metal nanocrystals.
Thermal treatment
Island
Thin metal film
CO 01 02 03
Table 3.2.1 Experimental parameters of the Dry Oxide/ Cobalt / TEOS Oxide Structure.
Figure 3.2.1 Process flow of the Dry Oxide/ Cobalt /TEOS Oxide Structure.
CO1 01 02 03
Table 3.2.2 Experimental parameters of the Dry Oxide/ Cobalt / TEOS Oxide Structure.
Figure 3.2.2 Process flow of the Dry Oxide/ Cobalt /TEOS Oxide Structure.
-4 -2 0 2 4 0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
C/Cox
Voltage V
for (4V~-4V) rev (-4V~4V)
Figure 3.3.1-1 The C-V hysteresis loop of cobalt nanocrystals in samples annealing at 900°C 60sec with 4V programming voltage.
Figure 3.3.1-2 The band diagrams of “write” and “erase” operations of the memory device.
-8 -6 -4 -2 0 2 4 6 8 0.2
0.4 0.6 0.8 1.0
C/Cox
Voltage V
for (8V~-8V) rev (-8V~8V)
Figure 3.3.2 The C-V hysteresis loop of cobalt nanocrystals in samples oxidized at 900°C 10min with 8V programming voltage.
Diagram 4.2-1 The sample that macromolecule nanosphere template be spun on the substrate.
Diagram 4.2-1 The sample that macromolecule nanosphere template be spun on the substrate.