Organization of the dissertation

1.3 Organization of the dissertation

This dissertation is divided into five chapters. The contents in each chapter are described as follows.

In chapter 1, the potential memory devices about Conventional Flash, SONOS and Nanocrystal memory devices is introduced.

In chapter 2, the study on cobalt silicide (CoSi2) nanocrystal memories technology by three different methods is investigated. First, cobalt silicide nanocrystal was fabricated by one step (to formed nanocrystals and oxidized amorphous silicon to dioxide at the same time) process. Then, the others methods were proposed to improve the diffusion phenomenon of cobalt silicide at the first method. Final, we will discuss and compare with the device characteristics between different methods and conditions.

In chapter 3, the study on Cobalt nanocrystal memory using Dual E-Gun Evaporation System deposited Cobalt thin film is investigated. Then, we will discuss the characteristics between different conditions.

In chapter 4, a new method of fabricating cobalt silicide nanocrystals is introduced.

The nanosphere template technology will be utilized for obtaining well-order 2-D array nano-dots. Moreover, the comparison in electrical properties between random and regular arrangements of nano-dots in space will be characterized.

In chapter 5, the conclusions of all experimental results in this dissertation and suggestions for the future research will be descried in this chapter.

Final, there are some matters needing attention in the experiment.

Chapter 2

Characteristic of Cobalt -Silicide Nanocrystals Memories Structures with Different Fabrication processes

2.1 Introduction

Metal nanocrystal charge storage offers several potential advantages over conventional stacked-gate nonvolatile memory devices include higher density of states around the Fermi level, stronger coupling with the conduction channel, a wide range of available work functions, and smaller energy perturbation due to carrier confinement. The higher density of states makes metal nanocrystals more immune to Fermi-level fluctuation caused by contamination. The metal nanocrystals tend to have more uniform charging characteristics, resulting in tighter control. The wide range of available work functions provides one more degree of design freedom to engineer the tradeoff between write/erase and charge retention because the work function of nanocrystals affects both the depth of the potential well at the storage node and the density of states available for tunneling in the substrate. By aligning the nanocrystals Fermi level to be within the silicon band-gap under retention and above the conduction band edge under erase, a large can be achieved even for very thin tunnel oxides. Because writing is performed by tunneling electrons from the silicon substrate into the nanocrystals thus can always find available states to tunnel into and can have current level similar to, fast write/erase and long retention time can be achieved

simultaneously in metal nanocrystals memories. Metal nanocrystals also provide a great degree of scalability for the nanocrystals size. To enable single-electron or few-electron memories by the Coulomb blockade effect, smaller nanocrystals are preferred. However, for semiconductor nanocrystals, the band-gap of nanocrystals is widened in comparison with that of the bulk materials due to the multidimensional carrier confinement, which reduces the effective depth of the potential well and compromises the retention time. This effect is much smaller in metal nanocrystals because there are thousands of conduction-band electrons in nanocrystals even in charge neutral state. As a result, the increase of Fermi level is minimal for metal nanocrystals of nanometer size.

As the scaling down the size of device in very large scale integrated circuits (VLSI) technology, silicides generally apply to any aspect such as lower contact resistance and fully silicide (FUSI) metal gate [2.1]. Most important of all, some reports indicate that silicide has self-passivating silicon dioxide formed under high oxidation temperature or prolonging heat treatment time [2.2]. At the same time, silicide films tended to agglomerate or form islands under such annealing condition. According to these reason, we employed this phenomenon to manufacture our metal nanocrystals embedded in the SiO2 layer. Furthermore we verified this method could have effect of memory. And this method was one step process that we can form not only the memory storage medium but also the control silicon dioxide. This process can be so simpler low cost fabrication process than traditional nanocrystal memories processes.

However, we wanted to research in the storage characteristics of the Nickel Silicide dots so we studied on some different fabrication processes. In this letter, we proposed a NiSi2 nanocrystal memory device and studied on the memory characteristics of the metal nanocrystal.

2.2 Experimental procedures

2.2.1 The Oxidation of the Dry Oxide/Cobalt/amorphous Silicon Structure

There are five steps must be done in proper sequence. The first step, single-crystal 6 inch (100) oriented p-type silicon was cleaned with standard RCA recipes. The standard RCA clean process was immersed in the HCl bench at 120℃ for 10 minutes (called SCΙ process). Next, the wafers were cleaned with NH4OH at 120℃ for 10 minutes (called SCⅡ process) <2.1>. The last was dipped in HF a few seconds <2.2>.

Second, the wafer was followed by dry oxidation in the atmospheric pressure chemical vapor deposition (APCVD) furnace to form 4.5nm-thick dry SiO2 layer as tunneling oxide <2.3>. Third, after the growth of tunnel oxide, a thin cobalt film and an amorphous silicon film were deposited in proper order on the tunneling oxide layer at the same run by Dual E-Gun Evaporation System (E-Gun). In this procedure, first the Co layer was deposited on the tunneling oxide layer, and then the a-Si layer was covered immediately. The deposition rate of the E-Gun was relied on adjustment of the current magnitude by a remote control. Not the rate magnitude but the current magnitude must be more exact because of the deposition thickness of cobalt film was the critical process to determine the size of the nanocrystals and the memory effect

<2.4>. The cobalt film thickness was deposited about 10Å with deposition rate 0.1Å/sec and operation current range in 50-70uA, the a-Si film thickness was deposited about 200Å with deposition rate 0.2 Å/sec and operation current range in 70-80uA. The fourth step is the thermal treatment, the furnace oxidation processes at

different temperatures and times in the O2 surrounding (50%) <2.5>. The conditions of experimental parameters we set up are shown in Table 2.2.1. The cobalt thin film and the amorphous silicon became to the cobalt-silicide (CoSi2) and silicon dioxide at the same time after thermal oxidation, respectively. In the initial stage of the oxidation, the cobalt would react with little amorphous silicon to become cobalt-silicide, CoSi2,

and then tended to form cobalt-silicide nanocrystals according to previous research.

After this step, the micro-structure of sample was analyzed by Transmission Electron Microscope (TEM). The TEM figures can be more powerful evidence to confirm the shape of the nanocrystals. Finally, step five, the Al electrode 5000Å was patterned and coated by thermal evaporation coater. The complete experimental procedure for cobalt-silicide nanocrystals is shown in Figure 2.2.1. Subsequently, this metal insulator semiconductor (MIS) structure with CoSi2 nanocrystals embedded in dioxide was fabricated, and has prepared for electrical analyses. The Capacitance-Voltage measurement was analyzed the memory effect of the nanocrystal memories by HP4284A Precision LCR Meter.

2.2.2 The Oxidation of the Dry Oxide/Cobalt/amorphous Silicon/Silicon Dioxide/amorphous Silicon Structure

There are six steps must be done in proper sequence. The first step, single-crystal 6 inch (100) oriented p-type silicon was cleaned with standard RCA recipes. The standard RCA clean process was immersed in the HCl bench at 120℃ for 10 minutes (called SCΙ process). Next, the wafers were cleaned with NH4OH at 120℃ for 10

minutes (called SCⅡ process). The last was dipped in HF a few seconds. Second, the wafer was followed by dry oxidation in the atmospheric pressure chemical vapor deposition (APCVD) furnace to form 4.5nm-thick dry SiO2 layer as tunneling oxide.

Third, after the growth of tunnel oxide, a thin cobalt film and an amorphous silicon film were deposited in proper order on the tunneling oxide layer at the same run by Dual E-Gun Evaporation System (E-Gun). In this procedure, first the cobalt layer was deposited on the tunneling oxide layer, and then the amorphous silicon layer was covered immediately. The deposition rate of the E-Gun was relied on adjustment of the current magnitude by a remote control. Not the rate magnitude but the current magnitude must be more exact because of the deposition thickness of cobalt film was the critical process to determine the size of the nanocrystals and the memory effect.

The CoSi2 components were formed 1：2 ratio as Co to a-Si so the thickness of a-Si layer was double of Co layer. The cobalt film thickness was deposited about 10Å with deposition rate 0.1Å/sec and operation current range in 50-70uA, the a-Si film thickness was deposited about 20Å with deposition rate 0.1 Å/sec and operation current range in 70-80uA. Fourth, after the deposition of the Co/a-Si layers, once again a thin silicon-dioxide film and an amorphous silicon film were deposited in proper order on the tunneling oxide layer at the same run by Dual E-Gun Evaporation System (E-Gun). In this procedure, first the SiO2 layer was deposited on the lower a-Si layers, and then the a-Si layer was covered on top immediately. The action of this thin SiO2 layer was resisted the diffusion effect of cobalt silicide. The silicon-dioxide film thickness was deposited about 15Å with deposition rate 0.1Å/sec and operation current range in 50-60uA, the a-Si film thickness was deposited about 220Å with deposition rate 0.2 Å/sec and operation current range in 70-80uA. Step five is the thermal treatment, the furnace oxidation processes at different temperatures and times in the O2 surrounding (50%). There are many conditions we set up are shown in Table

2.2.2. The stacked structure was oxidized to form cobalt-silicide (CoSi2) nanocrystals precipitated and embedded in dioxide, and the other a-Si become SiO2 at the same time. In the initial stage of the oxidation, the cobalt would react with the lower amorphous silicon to become cobalt-silicide, CoSi2, and then tended to form cobalt-silicide nanocrystals according to previous research. After this step, the micro-structure of sample was analyzed by Transmission Electron Microscope (TEM).

The TEM figures can be more powerful evidence to confirm the shape of the nanocrystals. Finally, step six, the Al electrode 5000Å was patterned and coated by thermal evaporation coater. The complete experimental procedure for cobalt-silicide nanocrystals is shown in Figure 2.2.2.

Subsequently, this metal insulator semiconductor (MIS) structure with CoSi2

nanocrystals embedded in dioxide was fabricated, and has prepared for electrical analyses. The Capacitance-Voltage measurement was analyzed the memory effect of the nanocrystal memories by HP4284A Precision LCR Meter.

2.2.3 The Oxidation of the Dry Oxide/Cobalt/amorphous Silicon/TEOS Oxide Structure

There are six steps must be done in proper sequence. The first step, single-crystal 6 inch (100) oriented p-type silicon was cleaned with standard RCA recipes. The standard RCA clean process was immersed in the HCl bench at 120℃ for 10 minutes (called SCΙ process). Next, the wafers were cleaned with NH4OH at 120℃ for 10 minutes (called SCⅡ process). The last was dipped in HF a few seconds. Second, the

wafer was followed by dry oxidation in the atmospheric pressure chemical vapor deposition (APCVD) furnace to form 4.5nm-thick dry SiO2 layer as tunneling oxide.

Third, after the growth of tunnel oxide, a thin cobalt film and an amorphous silicon film were deposited in proper order on the tunneling oxide layer at the same run by Dual E-Gun Evaporation System (E-Gun). In this procedure, first the Co layer was deposited on the tunneling oxide layer, and then the a-Si layer was covered immediately. The deposition rate of the E-Gun was relied on adjustment of the current magnitude by a remote control. Not the rate magnitude but the current magnitude must be more exact because of the deposition thickness of cobalt film was the critical process to determine the size of the nanocrystals and the memory effect. The CoSi2

components were formed 1：2 ratio as Co to a-Si so the thickness of a-Si layer was double of Co layer. The cobalt film thickness was deposited about 8Å with deposition rate 0.1Å/sec and operation current range in 50-70uA, the a-Si film thickness was deposited about 15Å with deposition rate 0.1 Å/sec and operation current range in 70-80uA. The fourth step is the thermal treatment, a metal rapid thermal annealing (Metal - RTA) in N2 ambient was performed to form the CoSi2 nanocrystals <2.6>.

The cobalt thin film and the amorphous silicon became to the cobalt-silicide (CoSi2) only but not formed silicon dioxide. That is the reason we chose the ratio (1：2) as Co to a-Si. Therefore, the N2 Metal - RTA process transformed the Co layer and a-Si thin film layer to the CoSi2 spherical nanocrystals. The conditions of experimental parameters we set up are shown in Table 2.2.3. Fifth, the TEOS oxide 400Å was deposited on the CoSi2 nanocrystals by PECVD with reactant gases of TEOS flow 10 sccm mixed in Hydrogen plasma at 300℃ <2.7>. This step also was the critical process because it was related to retention and endurance characteristics. After this step, the micro-structure of sample was analyzed by Transmission Electron Microscope (TEM). The TEM figures can be more powerful evidence to confirm the

shape of the nanocrystals. Finally, step six, the Al electrode 5000Å was patterned and coated by thermal evaporation coater. The complete experimental procedure for cobalt nanocrystals is shown in Figure 2.2.3. Subsequently, this metal insulator semiconductor (MIS) structure with CoSi2 nanocrystals embedded in dioxide was fabricated, and has prepared for electrical analyses. The Capacitance-Voltage measurement was analyzed the memory effect of the nanocrystal memories by HP4284A Precision LCR Meter.

2.3 Results and discussions

2.3.1 The Material Characteristic and Electrical Characteristics of the Dry Oxide/Cobalt/amorphous Silicon Structure

Figure 2.3.1-1(a) and Figure 2.3.1-1(b) represents typical bright-field, cross-section TEM images. Figure 2.3.1-1(a) shows the standard structure before oxidation. We can see the structure, the cobalt layer and a-Si layer were continuous above the tunnel oxide. In Figure 2.3.1-1(b), a sample after 900℃ dry oxidation is shown. The separated cobalt-silicide nanocrystals were found to distribute in the control oxide randomly. It is found that the cobalt-silicide nanocrystals had diffusion phenomenon in both the tunnel oxide and control oxide. The distribution of

cobalt-silicide nanocrystals is closer to top, it means that the diffusion phenomenon in control oxide is more serious than tunnel oxide, because the quality of tunnel oxide layer formed with dry oxidation in the atmospheric pressure chemical vapor

deposition furnace is better. The variation in morphology of these samples with

different oxidation temperatures is related to the rate of silicide formation. As the a-Si film was oxidized, oxygen may diffuse to the oxide/Si interface to form silicon oxide.

If the CoSi2 nanocrystals were already formed, they may move farther away from the oxide/Si interface. As a result, the selection of oxidation temperature and time are critical for forming nanocrystals. In growing SiO2 film from Si, a film of SiO2 with a thickness of x0 consumes a layer of crystalline Si _c-Si_ about 0.45x0. Therefore, a Si substrate about 3.2 nm thick was oxidized to contribute to about a 7 nm thick SiO2 in addition to the 3 nm thick tunnel oxide. The electrical characteristics as illustrated in Figure 2.3.1-2(a). Figure 2.3.1-2(b). Figure 2.3.1-2(c) and Figure 2.3.1-2(d) are the capacitance-voltage (C-V) measurement of the samples dry oxidized at 900℃. 850℃

and 800℃, respectively. The capacitance-voltage characteristics of those three conditions are rather poor, there is almost no hysteresis in those three figures. This reason is considered that the diffusion effect of cobalt-silicide in oxide layer, as shown in Figure 2.3.1-1(b). The cobalt-silicide nanocrystals diffused close to the top, and easily produced some fatal discharge paths, cause electrons cannot maintain stored in the cobalt-silicide nanocrystals.

2.3.2 The Material Characteristic and Electrical Characteristics of the Dry Oxide/Cobalt/amorphous Silicon/Silicon Dioxide/amorphous Silicon Structure

Figure 2.3.2-1 represents typical bright-field, cross-section TEM images of the sample after 800℃ dry oxidation. As seen in this figure, the well-separated and spherical cobalt-silicide nanocrystals embedded in the silicon dioxide layer were clearly observed. It worthily notices that the diffusion effect of cobalt-silicide

nanocrystals of the dry oxide/cobalt/amorphous silicon/silicon dioxide/amorphous silicon structure was not so serious in the tunnel oxide and still above the tunnel oxide.

It implies the diffusion phenomenon was restrained successfully by the silicon dioxide layer between those two amorphous silicon layers. The lower amorphous silicon layer reacted with cobalt to formed cobalt-silicide, and the top amorphous silicon layer was completely oxidized to server as the control oxide layer. The characteristic is

beneficial for the reliability and the yield of the memory device. Furthermore, Figure 2.3.2-2(a) shows the plan-view TEM image of a sample after 800 °C oxidation. The mean size and aerial density of the cobalt-silicide nanocrystals were measured to be about 4.42nm and 2.3°10¹¹/cm², respectively. The size distribution of the

nanocrystals is shown in Figure 2.3.2-2(b).

The electrical characteristics as illustrated in Figure 2.3.2-3(a) and Figure 2.3.2-3(b) are the capacitance-voltage (C-V) measurement of the samples dry oxidized at 800℃.

It implies the forward and reverse voltage sweep C-V characteristics, indicating the electron charging and discharging effects of the CoSi2 nanocrystals embedded in SiO2.

The bidirectional C-V sweeps were performed from deep inversion to deep

accumulation and in reverse, which exhibited an electron charging effect. When the voltage swept from (+6) to (-6) V and back to (+6) V at the same point, a significant threshold voltage shift of 1V is observed. As the “program” voltage decreased to 3V, a visible threshold voltage shift about 0.8V is observed, too. The goal of capacitance -voltage measurement is to confirm whether there are some traps or nanocrystals in the MOS structure as charge storage. It is perceived that both of the hysteresis is counterclockwise, which is due to injection of electrons from the deep inversion layer and injection of holes from the deep accumulation layer of silicon substrate [2.3]. The result of the C-V shift indicates that the charging effects of CoSi2 nanocrystals are more significant than those of the semiconductor nanocrystals.

Figure 2.3.2-4 shows the band diagrams of “write” and “erase” operations with different gate polarities of the memory device. When the device is written or programmed, the electrons directly tunnel from the silicon substrate through the tunnel oxide, and are trapped in the CoSi2 nanocrystals. On the other hand, when the device is erased, the electrons may tunnel back to the deep accumulation layer of silicon substrate. The control oxide is utilized to prevent the carriers of gate electrode injecting into the CoSi2 nanocrystals by Fowler-Nordheim (F-N) tunneling.

The most important advantage using the metal nanocrystals over their

semiconductor counterparts is that the metal nanocrystals do not bear a voltage drop from gate voltage, which means all the voltages provided from control gate are dropped to tunnel oxide and control oxide. The operating voltage of the memory devices with conventional floating gate or semiconductor nanocrystals embedded in SiO2 is above 7 or 5 V. In our approach to fabricate the CoSi2 nanocrystals embedded in SiO2 by dry oxidation 800°C, a lower programming voltage of 3V realizes a

significant threshold voltage shift of 0.8V. The voltage is sufficient to be defined as

“1” and “0” by a typical sensing amplifier for a memory device.

2.3.3 The Electrical Characteristics of the Dry Oxide/Cobalt/amorphous Silicon/TEOS Oxide Structure

The electrical characteristics as illustrated in Figure 2.3.3-1(a) and Figure 2.3.3-1(b) are the capacitance-voltage (C-V) measurement of the samples annealing at 800℃

100 seconds. It implies the forward and reverse voltage sweep C-V characteristics, indicating the electron charging and discharging effects of the CoSi2 nanocrystals