O RGANIZATION

The thesis includes six chapters which focus on wide power supply range, wide locking range DLL-based clock generator. Following briefly introduces the content of each chapter.

Chapter 2 gives an overview of DLL, including analog DLL and digital DLL.

comparison results are also given in this chapter.

Chapter 3 describes the fundamentals and applications of multiphase DLLs and frequency multipliers.

Chapter 4 introduces the proposed adaptive successive approximation register-controlled search algorithm which avoids harmonic locking in wide-locking range. Simultaneously, a robust and ultra-low voltage design methodology is discussed.

Chap 5 presents a programmable DLL-based clock generator. Base on the

proposed frequency multiplier, the clock generator is suitable for dynamic frequency/voltage scaling which low power application is required. Finally, we will show the implementation of layout, simulation result and performance summary.

Chap 6 presents the conclusion and future work.

CHAPTER 2 AN OVERVIEW OF DELAY-LOCKED LOOP

2.1 T

A

T

D

-L

L

Figure 2.1 Block diagram of conventional DLL

A simplified block diagram of a conventional DLL is shown in Figure 2.1. There are three major parts: (1) phase detector (PD) (2) a variable delay line (3) controller.

The PD compares phase error between reference clock and output clock; meanwhile, it sends output signal to adjust delay time of the delay line. When DLLs achieve locked, ideally, there is no phase error between reference clock and output clock.

Equation (2.1) shows the relationship of reference clock and output clock, where K is an integer, Tref represents the clock period of the reference clock. Td denotes the delay time of delay line.

ref d

K T× = T (2.1)

The design challenge of the DLL is to consider process, voltage, temperature (PVT) variations, clock jitter, power consumption, portability, lock time and so on.

Therefore, different types of DLLs have been proposed to reach some of these objectives. We will briefly introduce and classify these delay-locked loops.

Analog DLLs have advantages of the smaller static phase, good jitter performance, and fine resolution because the delay is varied continuously. However, it suffers from slow locking time and sensitivity to PVT variations, which is not suitable for System on Chip (SoC) environment. On the contrary, the digital DLLs are more robust against PVT variations, providing fast lock time and easy to design. However, the quantization error of the digital DLLs is unavoidable because the delay adjustment is in a discrete manner. Recently, mixed-mode DLL have been proposed in [1]. They can possess both the advantages of analog DLLs and digital DLLs, such as better jitter performance of analog part and fast-lock operations of digital search algorithm.

However, their power consumption is still larger than all-digital DLL, and it is hard to integrate digital and analog blocks simultaneously. We simply classify DLLs in three different types, they are：

(1) Analog DLL Each block processes an analog signal. The advantages are ： low jitter output and higher delay resolution. The disadvantage is lower noise immunity and a longer design cycle.

(2) All Digital DLL Each block processes digital signal. Higher noise immunity ： and portability are the advantages of ADDLL. However, the lower delay resolution and jitter performance are disadvantages in ADDLL in general.

(3) Mixed-mode DLL: Use digital blocks to reach fast coarse tuning lock and fine tuning the phase error in an analog manner. The advantage is that it can reach high delay resolution and fast lock time, but the drawback is it is hard to integrate digital and analog blocks simultaneously.

2.2 D

A

D

-L

L

Figure 2.2 Block diagram of analog DLL

Figure 2.2 illustrates the block diagram of an analog DLL. It consists of a voltage-controlled delay line (VCDL), a phase detector, a charge pump, and a first order loop filter. The reference clock signal propagates through the voltage-controlled delay line. The phase detector compares the phase error between the reference clock and output clock, which is the delay version of VCDL, and produces an up/down signal to the charge pump. The charge pump integrates the phase error, and the loop filter produces a control voltage, Vctrl, to decrease or increase the delay time of the VCDL.

Once the reference clock is aligned with the output clock, the DLL is in the lock state.

2.2.1 Stability Analysis of Delay-Locked Loop [2]

Figure 2.3 Small signal AC model of the analog DLL.

Before starting the stability analysis of ADLL, the small signal AC model shall be introduced first. Figure 2.3 shows this model, the summer stands for phase detector, Icp is the charge pump current, TREF is the period of input reference clock, C is the capacitor value in loop filter, and KVCDL is the gain of VCDL. When loop is in steady-state locked condition, the s-domain transfer function from input to output is

0

From Eq. 2-2, we can easily find that the DLL is a first order system that is inherently stable. Unlike the small-signal AC model for a typical PLL, a minimum of a second order transfer function is required.

Since the transfer function is inherently stable, a wider loop bandwidth can be used. This allows a fast acquisition time, as well as the use of small loop filter capacitors facilitating integration. However, the small-signal AC model is only valid when the loop bandwidth, that is ωN, is much smaller than the phase detector comparison frequency (generally 10:1). Therefore, the following equation should be satisfied for stability consideration.

1 (2.4)

2.2.2 Jitter Analysis of Delay-Locked Loop [3]

Due to the noise of the real world, the output clock edge may have some timing uncertainty or fluctuation, which is called clock jitter. There are many factors will influence clock jitter performance, such as thermal, supply and substrate noise. We describe three major definitions of the jitter below. Suppose Tn is the nth clock period, T is the mean value of the clock period. Also, Figure 2.4 illustrates the long-term

jitter and the cycle-to-cycle jitter.

(1) The absolute jitter or long-term jitter: ΔT_n= T -T _n ,the quantity ΔTn is an

(2) The Cycle jitter: The rms value of the timing error ΔTn

lim 1 (2.7)

(3) The cycle-to-cycle jitter: The rms difference between two consecutive periods

(

)

Figure 2.4 long-term jitter and cycle-to-cycle jitter

2.2.3 Voltage-controlled Delay Line

Delay elements are essential parts for clocking operation in high speed VLSI application. The delay of each delay element is proportional to its RC time constant.

By changing the effective resistance or capacitance, delay elements can adjust their delay time. However, the characteristics of the voltage-controlled delay element are sensitive to supply noise and PVT variations. Here, we will introduce the three common approaches of VCDL. They are current-starved delay line (CSDL), RC-time-constant delay line (RCDL), and differential voltage-controlled delay line (DVCDL).

1. Current-Starved Controlled Delay Line

A basic delay element of CSCDL is shown in Figure 2.5. A simple current mirror can be used to generate two bias voltages. The control voltage Vctrl is applied to a series-connected element which can “current starve” an inverter. Vctrl modulates the ON resistance of pull-down transistor Mn1, and through a current mirror, pull-up transistor Mp1. These variable resistances control the current available to charge or discharge the load capacitance. Large values of Vctrl allow a large current to follow, producing a small delay.

Figure 2.5 The CSDL (a) delay element (b) delay line

2. RC-time-constant Delay Line

The basic delay line of RC-time-constant controlled delay element is shown in

elements. In Figure 2.6 (a), the control voltage (Vctrl) controls the charge current. The transistor Mn1 in essence controls the amount of effective load capacitance “seen” by the driving gate. Large value of Vctrl decreases the resistance of the transistor Mn1, so the effective capacitance at the logic gate output increase, producing a large delay.

Figure 2.6 The RCDL (a) delay element (b) delay line

3. Differential voltage-controlled Delay Line

In order to achieve better common-mode noise rejection, the differential delay element has been introduced in [4] as shown in Figure 2.7. The delay element consists of a pseudo differential amplifier for high-speed operation. Since the strong PMOS latch will decrease the bandwidth of the delay cell, the weak PMOS latch, M3–M4, is adopted to speed up the signal transition of the differential pair, M1–M2 .However, it will slow down the slew rate of the output signal. To improve the driving capability of the delay cell, the PMOS transistors, M5–M6 , in triode are added to increase the driving capability. The PMOS transistors, M7–M8, are used to adjust the delay.

Figure 2.7 The DVCDL (a) delay element (b) delay line

2.2.4 Phase Detector

Phase Detector is a circuit that is response the relationship between reference and feedback signal. Figure 2.8 shows three-state phase detector circuit and Figure 2.9 shows the waveforms in some conditions. Unlike multipliers and XOR gate, three-state PD generates two outputs that are not complementary. When the feedback signal is high and the reference signal is low, then the PD produces positive pulse at down signal, while up signal remains at zero.

Conversely, if reference signal is high and feedback signal is low then positive pulses appear at up signal while down signal is zero. It should be note that, in principle, up and down are never high together in the simulation. The average value of up-down is an indication of phase difference between reference and feedback clock.

Figure 2.8: Three-state phase detector

Figure 2.9: PD responses with (a) reference signal lag feedback signal (b) reference signal lead feedback

The delay time to reset all internal nodes limits the maximum operation frequency of the phase detector. Therefore, a dynamic phase detector [] is proposed to solve this problem as shown in Figure 2.10. The phase detector is composed of two half-transparent (HT) registers. Due to symmetry of circuit and only three gate delay of critical path, this phase detector has less phase offset and can be operated at a higher frequency than the conventional phase detector.

Figure 2.10: (a) The Half-transparent register (b) dynamic PD

Figure 2.11: PD state diagram

In the Figure 2.11, it shows the PD circuit behavior. It has three state diagrams:

UP=1, DOWN=0 (state 1), UP=0, DOWN=0 (state 0), UP=0, DOWN=1 (state 2).

Because the PD is build up from two edge-triggered sequential circuits, we can avoid dependence of the output upon the duty cycle of the inputs. Suppose the circuit is initially in state 0. Then a rising edge on reference signal takes the circuit to state 1, where UP=1, down=0. With state 1 is reached, any more rising edges at reference signal won’t case state change at all. The circuit will remain in this state until a transition occurs on feedback signal, upon which the PD returns to state 0. The switching sequence between state 0 and state 2 is similar. The three-state PD can nominally detect a full range of phase difference, i.e. +2pi,-2pi. A phase difference larger than 2pi is truncated with respect to integer of 2pi. The output of the PD can drive charge pump to produce a controlled voltage for delay line. The charge pump and loop filter will be discussed followed.

2.2.5 Charge Pump and Loop Filter

The simple model of charge pump and loop filter is shown in Figure 2.12. It consists of two matched current sources and function as switch. When the up signal is

when the down signal is high, the down signal turns on the lower switch and discharges the output node Vctrl. Finally, if both up and down signal are low, then net current is zero and output node Vctrl holds the original voltage. Figure 2.13 shows the simplified timing diagram of charge pump.

The loop filter can be either passive or active. In general, a passive filter is simple to design and has better noise performance. The passive filter was shown in Figure 2.14, which may be first-order, second-order, or other high order structure. High order filters take advantages of rejecting out-band noise. However, low order filters result in more stable operations. The choice between high order filters and low order filters depends on the applications and to prevent DLL into unstable state.

Figure 2.12: Simple model of charge pump and loop filter

Figure 2.13: The simplified timing diagram of charge pump

Figure 2.14 Loop filter

2.3 D

D

-L

L

O

Figure 2.15 Block diagram of digital DLL

As the era of System-On-Chip (SoC) coming, people give more attention on digital DLLs since they are easy to port to different process. Recently, due to the fuel crisis, a power-saving issue becomes more and more important. The power of CMOS circuit is determined primarily by equation P=CFV², which decreases quadratic ally with supply voltage. For this reason, the digital DLLs have better power-saving performance since it can operate at lower voltages than analog DLLs.

The conventional digital DLL block is shown in figure 2.15. It consists of three major blocks. They are phase detector (PD), control unit (CU) and digital control delay line (DCDL). The PD detects the phase error between the input clock and the output clock and generates signal to the CU. The CU adjusts the delay line making input clock and output clock in-phase.

We classify four major types of digital DLLs; they are register-controlled, counter-controlled, successive approximation register-controlled, and time measurement controlled DLLs. The following section will describe in detail.

2.3.1 Register-controlled DLL [5]

Figure 2.16 Register controlled DLL

Figure 2.16 shows the block diagram of register-controlled DLL. The n-bit shift register controlled by the output of phase detector. At any time, only on bit of the shift register is active to select a specify delay time of delay line. The phase detector detects the relation between input clock and output clock, and generates left and right signal for shift register to control the amount delay time. When Enable is active, it will enable the shift register, vice versa. The detail operation is described as following. When the

output clock leads the input clock, the phase detector sends left signal to shift register and the high bit in the shift register will be shifted left to increase the delay time to compensate for the delay mismatch. Similarly, when the right is active, the high bit in the shift register will be shifted right to decrease the delay time. When Enable is active, the phase error between the input clock and the output clock is within one unit delay, and the data in the shift register will be held. Under this mechanism, the loop is locked and the phase error will not exceed the unit delay.

Although the control mechanism is quite sample, but when the operating range is increased, the additional delay stages of delay line should be added. Thus, it increases the chip area and power consumption. Beside, the control mechanism is one by one, which means, the more delay stages needs more shift registers to control the delay line.

Thus, it also increases locking time. In the worst case, n-bit shift register needs n/2 locking cycles.

2.3.2 Counter-controlled DLL [6]

Figure 2.17 counter-controlled DLL

Basically, the operating principle of counter-controlled DLL is similar to register-controlled DLL expect the up/down counter substitutes for the shift register to control the delay line. In addition, the binary-weighted delay line is adopted and no longer consists of delay stages with equal delay time. Figure 2.17 shows the block diagram of counter-controlled DLL. The active of up/down counter is base on the output of phase detector. The n-bit control word determiners whether the input signal goes through the delay path or passes it. The most different between register-controlled DLL (RDLL) and counter-controlled DLL (CDLL) is area requirement. For example, compare with the RDLL, if 128 delay stages are required in a RDLL, only 7 delay stages are required in a CDLL. Besides, the 128-bit shift register in a RDLL can be substituted for 7-bit up/down counter. While the operating ranges and delay resolution of RDLL and CDLL are the same, the delay line of RDLL will get larger offset delay time and occupy larger chip area than the CDLL. By using CDLL, the chip area could be reduced while maintaining the same operating range as in a RDLL. However, the CDLL still use to linear approach manner to trace the input clock, thus the locking time of CDLL would not get any improvement as RDLL. In the worst case, with n-bit binary-weighted delay line, the locking time maintains n/2 locking cycles.

2.3.3 Successive Approximation Register-controlled DLL [7]

Figure 2.18 SARDLL

The locking time is an important parameter for digital DLL to evaluate the performance, especially in the high-speed memory applications. The DLLs that mentioned above based on the linear search exhibit the same lock time. The linear search algorithm; however, increases the locking time when frequency is wider. The binary search algorithm may be a better method to reduce the locking time. Figure 2.18 shows the block diagram of binary search (SAR) DLL.

First, the most significant bit (MSB) of the control word is set to 1, and the other bits all are set to 0. The phase detector judge whether the output clock leads the input clock or not. If output clock leads the input clock, the MSB is set to low. If output clock lags the input clock, the MSB remains high and held constant. In this way, the MSB is determined. The operating produce is repeated for the following bit until the least significant bit (LSB) is determined. Figure 2.19 shows an example of the 3-bit binary search algorithm. Assume the final control word is set to “001” and the initial control word is set to “100”. In this example, the output clock leads input clock in the step 1 and step2, and output clock lags input clock in the step 3. Finally the binary searching finds the correct control word “001”.

Figure 2.19 Flowchart of 3-bit binary search algorithm

The SAR DLL is not only reduces the chip area but also shorten the locking time.

In the worst case, with n-bit delay line, the locking time of SAR-DLL is log2(2^(n-1)).

Unfortunately, The SAR controller in the DLL determines the value of each bit of the word in a sequential and irreversible. Therefore, it becomes an open-loop type circuit after lock-in and never against the PVT variation. An improved SAR DLL [8] was proposed to solve this problem by using the counter-controlled control word instead of SAR-controlled. The initial control word of the counter is load from the SAR controller, and then a counter-controlled DLL is started to maintain the environment variation.

2.3.4 Time measurement controlled DLL

Figure 2.20 TMDLL

Another mechanism to reduce the locking time was proposed in [9] as shown in Figure 2.20. The time measurement controlled DLL divide the locking produce into two stages, coarse tuning and phase tracing. The coarse tuning stage is based on the time to digital converter (TDC) circuit as shown in Figure 2.21. The TDC is used in ADPLL or ADDLL to convert timing information directly to the digital code. The TDC usually consist of the delay that is identical or multiple or fractional to the single delay

cell in the delay line or oscillator, the concept is let timing signal to pass this delay then

cell in the delay line or oscillator, the concept is let timing signal to pass this delay then