S IMULATION R ESULT

The proposed all-digital programmable DLL-based frequency multiplier (ADP-DLLFM) is implemented in UMC 90 nm standard CMOS technology. The operation frequency range is from 125MHz – 2.5GHz, and available to synthesize (05X, 1X, 2X, 4X) four different frequency with output duty cycle 50%. Based on the proposed adaptive SAR controller, the ADP-DLLFM can operate properly in wide frequency and voltage range; in addition, the locking step is no more than 28 reference clock cycles. The total power consumption is 710μW at 2GHz with 1.0V power supply, and 4.2μW at 115MHz with 0.3V power supply. Figure 5.27 and Figure 5.27 and Figure 5.28 show when ADP-DLLFM is locked, it can synthesize four different frequency with power supply 1.0V and 0.3V, respectively.

Figure 5.27: Generate four different frequency with 1.0V power supply

Figure 5.28: Generate four different frequency with 0.3V power supply

The total simulation result of chip implementation summary and a comparison result under the UMC 90nm CMOS technology are shown in Table 3.

Table 3 Comparison among previous works

Design ISSCC Category Analog Analog Digital Analog Analog Digital 50% Duty

CHAPTER 6 CONCLUSION AND FUTURE WORK

6.1 C

A novel 125MHz-2.5GHz all-digital DLL-based clock generator is implemented in UMC 90nm CMOS technology. The proposed adaptive SAR algorithm achieves fast lock time and extends the locking range with aid of the frequency-estimation selector. In order to accomplish dynamic frequency/voltage scaling application, the programmable frequency multiplier also be proposed. It takes advantages of the robust, input duty cycle immunity, and low power consumption.

The novel leakage-reduced delay unit is proposed to take advantages of mitigating 10% leakage current, insensitive to PVT variations, and not degrading operating frequency of circuit. The simulation results show the proposed DLL-based clock generator exhibits maximum power dissipation 0.71mW when operate in 500MHz, generating 250MHz, 500MHz, 1GHz, and 2GHz four different frequency at the same time. The presented DLL clock generator can be robustly used in embedded memory applications and portable device.

6.2 F

W

The DLL-base frequency multiplier combines each multiphase to generate multiple clock frequency. Theoretically, it has better jitter performance than PLL because of no jitter accumulation characteristic. However, due to the delay mismatches or PVT variations, the edges of the multiphase output signals are not equally spaced, and it will induce the fixed pattern jitter at the multiplied clock output.

Therefore, a DLL with precise multiphase outputs is necessary. In our future work, we will focus on precise and robust calibration mechanism to compensate the delay mismatch among each delay line.

LEAD

Figure 6.1 ADCGSC clock generator

Figure 6.1 shows the idea of 300mV all-digital DLL-based clock generator with self-calibration (ADCGSC). It includes the proposed clock generator and self-calibration unit. The self-calibration unit reduces the delay mismatch of delay cell, and the clock generator can generate precise and different clock frequency at fast time.

As result, the ADCGSC is suitable for portable devices and medical device.

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