O RGANIZATION OF THE T HESIS

This thesis presents the design of accelerometer with readout circuits, including design flow chart, single-axial accelerometer design, and a micro-power low noise readout circuit. Chapter 2 describes the system specification and the design flow. In chapter 3, a single-axial accelerometer design would be presented. We are going to show what the fabrication flow is, and introduce the accelerometer area design flow under the process constraint. In chapter 4, the front-end circuit with chopper stabilization and correlated double sampling technology is described from architectural level down to detail design. The simulation and measurement results are presented in chapter 5. Chapter 6 concludes dissertation with summary, and suggestion for the future work.

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Chapter 2

Architecture

2.1 System Architecture and Specification

The architecture of the accelerometer with readout circuit is shown in Fig. 2.1, where the fully differential capacitive bridge represents the sensing capacitors of the accelerometer. A₁ is the first stage amplifier, A₂ is the second stage amplifier, and clocking is used for chopper stabilization and correlated double sampling technology.

The design goal is to achieve 12-bit resolution under 1.2V peak to peak output swing with ±4g input sensing range. The bandwidth of the CMOS MEMS accelerometer is up to 100Hz. Design target for the output noise voltage should be less than half the LSB, i.e. 14.6μV/√Hz for 100Hz bandwidth. The sensitivity could be 150mV/g due to

Figure 2.1: Architecture diagram of the accelerometer with readout circuit.

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1.2V_pp with ±4g sensing range. Assume the voltage swing at sensor output is 1mV/g, the voltage gain readout circuit can be obtained as 44 dB.

Considering noise and linearity, the voltage gain of the second stage amplifier is set to be 22dB. The gain of the first stage amplifier with the CDS circuit is 22dB. The input-referred noise is 97.3nV/√Hz. Because low noise circuit design is more easily to be achieved than MEMS design, the noise constraint of readout circuit is set to be one fourth of total noise.

The system specification is shown in table 2.1. In order to achieve 12-bit resolution, the noise constraint is the critical design consideration. The noise comes from the mechanical noise of the accelerometer and the electronic noise of the readout circuit.

Table 2.1: System Specification

Resolution 12-bit Input range ±4g (8g)

Output range ±600mV(150mV/g) Circuit voltage ±0.9V(1.8V)

Bandwidth 100Hz

Input-referred Noise <97.3nV/√Hz

2.2 System Design Flow

A specification-driven accelerometer design flow is proposed in this thesis. The target of this design flow shown in Fig. 2.2 is to achieve 12-bit resolution. To get the

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minimum occupied area of accelerometer under required system performance for sensor and to get the optimized bias current and width of the input MOS for analog front-end. The left part belongs to the accelerometer design flow. The noise constraint comes from the Brownian noise, and is set to be less than 75% the total noise.

The accelerometer could be divided into three parts: spring, sensing fingers and proof mass. In order to minimize the area of the accelerometer, the correlation between geometry parameters and mechanical properties should be found first. The circuit design is to get the optimized bias current and MOS width/length of the input transistors under the noise constraint. The detailed design considerations will be described in the follow sections.

Figure 2.2: Design flow chart of the system.

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Chapter 3

CMOS MEMS Accelerometers

3.1 CMOS MEMS Accelerometer Fabrication

3.1.1 Surface Micromachining

The accelerometer described in this thesis is designed with the 0.18μm CIC (National Chip Implementation Center) CMOS MEMS technology. The process starts with TSMC 0.18μm mixed-signal/RF CMOS process. The process flow is shown in Fig. 3.1(a) incorporates the TSMC 0.18μm 1poly-6metal CMOS process. The micromachining process is performed on the wafer after the standard CMOS process.

The passivation above the microstructure will be removed during CMOS process.

And the passivation layer above the electronic circuits is preserved to protect the devices during the MEMS process. In Fig. 3.1(b), after the CMOS processing, an anisotropic reactive ion etch (RIE) is the first performed to etch away SiO₂ that is not covered by photoresist, resulting in vertical sidewalls. At the final step, the isotropic dry etching shown in Fig. 3.1(c) is used to etch the silicon substrate and release the microstructures.

CIC CMOS MEMS technology requires an additional lithography step, which is different from the process in [4]. The post-process flow is completed by two simple dry etch steps.

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(a)

(b)

(c)

Figure 3.1: Post-CMOS micromachining steps: (a) after completion of CMOS, (b) anisotropic oxide etch, and (c) isotropic silicon etch to release the microstructures.

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Main advantage of this process is that it offers the integration of MEMS and electronics, therefore allows on-chip signal detection, signal processing and control to be implemented. Complex system-on-chips (SOC) can be fabricated at low cost. The integration enhances the performance and functionality of MEMS systems, and reduces the system cost.

However, the structure of CMOS MEMS technology severely limits the device performance. The microstructures have small mass in the order of 10^-9 kg, resulting in low sensitivity to outside force, and several orders of magnitude higher Brownian noise than bulk micromachined devices. In the 10 m thick structures, the devices have low capacitance for sensing. The total capacitance of the designed device is about 100 fF. This leads to the low sensor sensitivity. And the situation of the low sensitivity is further aggravated by the structural curling of the composite surface post -process structures. The multi-layer structural material, composed of metal layers with interleaved dielectric layers, exhibits residual stress gradients that induce structural curling [5]. The different curvatures in different parts of the devices cause mismatches between electrodes, which further reduces the capacitance and capacitance sensitivity.

Also, the CMOS MEMS structures exhibit large lateral mismatch which causes large variable position offset in differential sensing devices.

3.1.2 CMOS MEMS Design Rules

In the process, the design rules are defined by TSMC. All design rules defined in this section are applied to construct the structure of microelectromechanical devices.

To achieve the post process successfully, all design rule errors are not allowed.

Design rule definitions are shown in Fig. 3.2. These definitions are used for the distance constraint of multiple layers. In CMOS process, the passivation (PAD) mask

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defines the removal of silicon-nitride and gives an open-window on the signal pad. To guarantee the oxide etching process in CIC post-process, PAD mask is also necessary to overlap the RLS region, which defines the MEMS etching region. Besides, PAD mask can also help pass some DRC rules on large metal area.

Figure 3.2: Rule definitions.

RLS mask defines the MEMS etching region in post-process, and the design is shown in Table 3.1 and Fig. 3.3. Note that if the expected structural line width or spacing is beyond the limit of lithography (< 4 m) in post process, metal layer can be used as the hard-mask for the purpose of high resolution, but it is not guaranteed to be successful. Using metal layer as the hard-mask may cause polymer around the border, especially when the exposed metal area is large, so the metal layer overlapped with

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the RLS mask must be restricted to 1m and the yield rate of spacing < 4 m is much lower than which of the spacing > 4 m.

Table 3.1: RLS design rule definitions in CMOS MEMS Process

Rule # Description Rule (m)

RLS.W.1 Min. width of RLS A 4m

RLS.METALx.1 Max. overlap of RLS on Metal (If using Metal as hard mask)

RLS.ACTIVE.1 Min. interval from RLS to unsuspended PMOS or NMOS electronic circuits are forbidden in RLS regions.

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Figure 3.3: Examples of the RLS-mask definition.

3.2 CMOS MEMS Accelerometer Design

3.2.1 CMOS MEMS Structure

The geometry of single axial accelerometer and simplified lumped model is shown as Fig. 3.4. The springs, sensing fingers and proof mass build the core structure of the accelerometer. The anchors are used for connecting the sensor structure.

An accelerometer is a force sensor. The external acceleration generates an inertial force on the proof-mass. The inertial force then induces the displacement of the proof mass. With the operation range of the accelerometer, both the spring elastic force and the viscous damping force are linear with the displacement and the velocity of the proof-mass, respectively. The differential equation of displacement and external acceleration of sensor is given:

+ + = (3-1)

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where m is the mass of proof mass, b is the damping coefficient x is the displacement, and k is the stiffness of spring.

(a)

(b)

Figure 3.4: (a) Schematic of accelerometer and (b) lumped parameter model of accelerometer

With the 1^st order approximation, the equation of displacement can be simplified as:

= (3-2)

where n is defined as the natural frequency:

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= (3-3)

At frequencies much lower than the resonant frequency, the sensitivity of the accelerometer is given by:

= =

(3-4)

Based on Eq. 3-4, the resonant frequency of sensor can be defined by the maximum displacement at maximum sensing gravity. For this design consideration, with 4μm comb finger gap process constraint, we set up 1% displacement of the gap under 1g external accelerometer. Because the larger displacement elevates the nonlinearity but the less displacement makes the initial offset voltage of the sensor structure mismatch worse. The resonant frequency is 2.5kHz through the settings.

Figure 3.5 shows the folded-beam spring used in the accelerometer. The spring constant in the x-axis is given by:

= ℎ (3-5)

where N_k is the number of turns, E is the Young’s modulus of elasticity, and l_k, w_k, h are the length, width and height(thickness) of the beam respectively. In the accelerometer design, the beam width is 4 μm, and the beam height is the thickness of the composite structure, which is about 10 μm.

In CMOS MEMS accelerometers, capacitive sensing converts the mechanical displacement into electrical signal. When the proof mass moves in the sensing direction, the gap distances between the rotor and stator fingers change, and the capacitance of the parallel-plate capacitors changes accordingly. The capacitance

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change induces a charge transfer in the capacitors, which generates an AC voltage or an AC current.

Figure 3.5: Multi-turn folded-beam spring.

A capacitive divider provides a voltage-domain description of the sensing process as shown in Fig.3.6. The capacitance of one sensing capacitor increases, while the capacitance of the other capacitor decreases when the proof-mass moves in one direction. Thus, a voltage proportional to the displacement is generated. The sensitivity is limited by the parasitic capacitance which includes the fringe capacitance, the interconnect capacitance, and the input capacitance of the interface circuit.

Figure 3.6: Capacitive sensing by a capacitive divider.

The sensed voltage V_sense is given by:

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= ∙ = ∙ ∙ (3-6)

where C_s is the sensing capacitance of sensor, C_p is the parasitic capacitance at sensor output node, Vm is the voltage swing of modulation signal and x0 is the gap between two fingers. The sensed voltage can be rewritten as a Taylor series as:

= + − + ⋯ (3-7)

The existence of the parasitic capacitance gives rise to the nonlinear terms. When the displacement is sufficiently small, as in the case of accelerometers, the above equation can be approximated by a linear voltage-displacement relationship:

= ∙ ∙ (3-8)

As shown in Fig. 3.7, the CMOS MEMS accelerometer employs a differential capacitive bridge consisting of two differential dividers to realize fully differential sensing. The fully differential topology improves the inference rejection of the sensor with much high common-mode rejection ration (CMRR) and power supply rejection ration (PSRR). The sensed voltage in a differential sensor is as:

= − = ∙ ∙

(3-9)

The sensed signal is an amplitude modulation (AM) signal with the acceleration signal modulated by a high frequency modulation carrier. The sensitivity of the accelerometer is proportional to the amplitude of the modulation carrier, Vm.

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Figure 3.7: Fully differential capacitive sensor.

The accelerometer design flow is shown in Fig. 3.8. With 4μm comb finger gap process constraint, 1% displacement of the gap under 1g external accelerometer, the resonant frequency is about 2.5kHz, and the modulation voltage is 0.3V. The sensing capacitance C_s would be increased to achieve 1mV of the sensitivity of the accelerometer.

Figure 3.8: Accelerometer design flow chart

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The sensing capacitance C_s can be expressed as:

= (3-10)

N is the number of fingers, l is the finger length, x

₀ is the gap between fingers,



air is the dielectric constant of the air, and t is the thickness of each finger. From Eq. 3-9 and Eq. 3-10, the larger area of comb fingers, the higher voltage swing at sensor output node with fixed parasitic capacitor.

A direct consequence of air damping is the thermal-mechanical noise, a random force generated by the Brownian motion of ambient molecules. It is normally called Brownian noise. For accelerometers, the power spectral density (PSD) of the Brownian noise is:

( ) =

( . ) (g ⁄Hz) (3-11) where kb is Boltzmann’s constant (1.38×10^-23 J/K), T is temperature, b is damping factor and m is the weight in kg of proof mass. And the input-referred Brownian noise floor is:

( ) =

. (g √Hz⁄ ) (3-12) There are two sources of mechanical damping: the structural damping; and the viscous damping by gas flows. The CMOS MEMS structures are made of Aluminum and SiO₂, both are high-Q materials with very low structural damping. The damping in CMOS MEMS devices is mainly caused by the viscous flow of gas surrounding the micro structures. The dominant damping mechanism in lateral accelerometer is

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squeeze-film damping between lateral parallel-plate capacitor fingers. The squeeze- film damping can be modeled as:

= 7.2 (3-13) calculated by Eq. 3-12. Then the spring constant will also be specified by Eq. 3-3. The sensing capacitance C_s, spring constant k, and proof mass m can be used for design the accelerometer as the purpose of the accelerometer design flow.

3.2.2 Accelerometer Layout Design Flow

The accelerometer dimension parameter for core area is shown in Fig. 3.9. H is the total length of the spring turns, W is the half width of the proof mass, L is the half length of the proof mass, and F is the comb finger length plus the gap between finger and rigid frame. As described in section 3.1.2, the minimum width and minimum gap are both 4m according to the design rule. The sensing capacitance Cs, spring constant k, and proof mass m which are gotten in previous section can be used for the area design.

The single axial accelerometer layout design flow is shown in Fig. 3.10. Based on the parameter sensing capacitance C_s, spring constant k, and proof mass m, the dimension for minimum accelerometer can be specified. From Eq. 3-10, we need the

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comb finger length and number to fit the sensing capacitance value. The area of F×L would be minimized if the number of comb finger N is set to be 1, but the finger length/width ratio would be larger than 100. Due to the curvature issue [5], the length/width ratio of the comb finger should be less than the maximum value constrained by foundry rules. Without foundry data, we assume the ratio to be ρ for our tuning parameter. With width 4 m, the length of F would be calculated. The number of comb fingers would also be determined base on the capacitance data. Then the proof mass length 2L can be calculated from the comb finger number.

Figure 3.9: Single axial accelerometer dimension parameter for core area

From the value of the sensing capacitance and the length/width ratio of comb fingers, both F and L can be determined as shown in step two of the accelerometer layout design flow in Fig. 3.10. Then we choose the minimum turn of the spring to get the parameter H. In order to satisfy the minimum proof mass, the W can be increased.

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Then W is increased to fit the design setting of resonant frequency from Eq. 3-5. The core area will be gotten from the parameters F, H, L, and W. We keep increasing the spring turn number to run the loop until outputting the minimum area as shown in Fig.

3.10.

Figure 3.10: Single axial lateral accelerometer layout design flow.

The comb finger length/width ratio is set to be 78m/4m that is less than 20 for curvature consideration. After calculation of the layout design flow, the figure of the accelerometer area versus the spring number is shown in Fig. 3.11. We could find out

Figure 3.11: The accelerometer area versus the spring number.

3.00E-07

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that the minimum area comes out when the spring number is 4.

This method can also be used for dual axial lateral CMOS MEMS accelerometer design. It would be simpler than the design flow of single axial accelerometer.

Because the layout of the accelerometer is symmetry, the less parameter makes the design flow easier. The accelerometer dimension parameter for core area is shown in Fig. 3.12. There are three parameters for layout dimension design. In this thesis, dual axial accelerometer will be discussed further due to single axial accelerometer is what we design for the system.

Figure 3.12: Dual axial lateral accelerometer dimension parameter for core area.

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Chapter 4

Front-End Interfacing Circuit

4.1 Front-end Circuit Architecture

The analog front-end circuit is shown in Fig 4.1. The fully differential topology is employed to reject CMRR and PSRR. The input resistors Rb are replaced by diode-connected PMOS devices for providing DC bias at input nodes. There should be large impedance at input node, but using resistors would cost larger area. The diode-connected PMOS devices can also provide high impedance at input nodes and cost much smaller area than using resistors. But the tradeoff is that the diode-connected PMOS devices have capacitance and smaller bias current. Depending on 0.18μm CMOS technique, the capacitance of it is in the order of fF and the leakage current is about several nA. The value of capacitance and bias current could be tolerable to the circuit performance.

Figure 4.1: Front-end circuit architecture.

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The first stage amplifier A₁ design is to achieve reasonable gain boost, to optimize power-noise performance, and to limit the operation bandwidth. Then a CDS technique is used to subtract out the output error voltage of the first stage amplifier with two sequential samplings. The following second stage amplifier is a closed loop amplifier. The amplifier is designed for satisfying the gain of the system requirement and is working as a low pass filter. The modulation signals are generated the logic gates as shown in Fig. 4.2. The non-overlapping two phase clocking is designed to avoid the overlapping of the two phase clocking. The clock overlapping will cause the charging error.

Figure 4.2: Schematic of the non-overlapping two phase clock generator and its timing diagram.

4.2 First Stage Circuit Design

4.2.1 First Stage Amplifier

The two-stage topology is preferred to the single-stage topology for the following reasons. First, the power-noise optimization requires the input transistors to adjust width/length ratio, therefore, they do not have sufficiently large transconductance to

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drive the entire high-gain wide-band amplifier. Second, the two-stage topology makes it easy to implement offset compensation and minimizes the noise contributed by offset compensation circuits. Third, a low-gain input stage could achieve the following goals: minimizing main noise contributing devices; amplifying signal to attenuate noise from the following circuits; limiting gain to prevent large sensor position offset from saturating the circuit from the beginning; limiting gain to reduce Miller effect.

The schematic of the first stage amplifier is shown in Fig 4.3. The overall gain is 44dB. The CDS will double the output voltage so that its gain is 6dB. The first stage

Figure 4.3: The schematic of the first stage amplifier.

is an open-loop amplifier with a gain of about 16dB. The open-loop amplifier A₁ architecture is believed to have better noise performance because it suffers less from

is an open-loop amplifier with a gain of about 16dB. The open-loop amplifier A₁ architecture is believed to have better noise performance because it suffers less from

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