CHAPTER 3 CMOS MEMS ACCELEROMETERS
3.2 CMOS MEMS A CCELEROMETER D ESIGN
3.2.2 Accelerometer Layout Design Flow
The accelerometer dimension parameter for core area is shown in Fig. 3.9. H is the total length of the spring turns, W is the half width of the proof mass, L is the half length of the proof mass, and F is the comb finger length plus the gap between finger and rigid frame. As described in section 3.1.2, the minimum width and minimum gap are both 4m according to the design rule. The sensing capacitance Cs, spring constant k, and proof mass m which are gotten in previous section can be used for the area design.
The single axial accelerometer layout design flow is shown in Fig. 3.10. Based on the parameter sensing capacitance Cs, spring constant k, and proof mass m, the dimension for minimum accelerometer can be specified. From Eq. 3-10, we need the
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comb finger length and number to fit the sensing capacitance value. The area of F×L would be minimized if the number of comb finger N is set to be 1, but the finger length/width ratio would be larger than 100. Due to the curvature issue [5], the length/width ratio of the comb finger should be less than the maximum value constrained by foundry rules. Without foundry data, we assume the ratio to be ρ for our tuning parameter. With width 4 m, the length of F would be calculated. The number of comb fingers would also be determined base on the capacitance data. Then the proof mass length 2L can be calculated from the comb finger number.
Figure 3.9: Single axial accelerometer dimension parameter for core area
From the value of the sensing capacitance and the length/width ratio of comb fingers, both F and L can be determined as shown in step two of the accelerometer layout design flow in Fig. 3.10. Then we choose the minimum turn of the spring to get the parameter H. In order to satisfy the minimum proof mass, the W can be increased.
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Then W is increased to fit the design setting of resonant frequency from Eq. 3-5. The core area will be gotten from the parameters F, H, L, and W. We keep increasing the spring turn number to run the loop until outputting the minimum area as shown in Fig.
3.10.
Figure 3.10: Single axial lateral accelerometer layout design flow.
The comb finger length/width ratio is set to be 78m/4m that is less than 20 for curvature consideration. After calculation of the layout design flow, the figure of the accelerometer area versus the spring number is shown in Fig. 3.11. We could find out
Figure 3.11: The accelerometer area versus the spring number.
3.00E-07
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that the minimum area comes out when the spring number is 4.
This method can also be used for dual axial lateral CMOS MEMS accelerometer design. It would be simpler than the design flow of single axial accelerometer.
Because the layout of the accelerometer is symmetry, the less parameter makes the design flow easier. The accelerometer dimension parameter for core area is shown in Fig. 3.12. There are three parameters for layout dimension design. In this thesis, dual axial accelerometer will be discussed further due to single axial accelerometer is what we design for the system.
Figure 3.12: Dual axial lateral accelerometer dimension parameter for core area.
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Chapter 4
Front-End Interfacing Circuit
4.1 Front-end Circuit Architecture
The analog front-end circuit is shown in Fig 4.1. The fully differential topology is employed to reject CMRR and PSRR. The input resistors Rb are replaced by diode-connected PMOS devices for providing DC bias at input nodes. There should be large impedance at input node, but using resistors would cost larger area. The diode-connected PMOS devices can also provide high impedance at input nodes and cost much smaller area than using resistors. But the tradeoff is that the diode-connected PMOS devices have capacitance and smaller bias current. Depending on 0.18μm CMOS technique, the capacitance of it is in the order of fF and the leakage current is about several nA. The value of capacitance and bias current could be tolerable to the circuit performance.
Figure 4.1: Front-end circuit architecture.
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The first stage amplifier A1 design is to achieve reasonable gain boost, to optimize power-noise performance, and to limit the operation bandwidth. Then a CDS technique is used to subtract out the output error voltage of the first stage amplifier with two sequential samplings. The following second stage amplifier is a closed loop amplifier. The amplifier is designed for satisfying the gain of the system requirement and is working as a low pass filter. The modulation signals are generated the logic gates as shown in Fig. 4.2. The non-overlapping two phase clocking is designed to avoid the overlapping of the two phase clocking. The clock overlapping will cause the charging error.
Figure 4.2: Schematic of the non-overlapping two phase clock generator and its timing diagram.
4.2 First Stage Circuit Design
4.2.1 First Stage Amplifier
The two-stage topology is preferred to the single-stage topology for the following reasons. First, the power-noise optimization requires the input transistors to adjust width/length ratio, therefore, they do not have sufficiently large transconductance to
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drive the entire high-gain wide-band amplifier. Second, the two-stage topology makes it easy to implement offset compensation and minimizes the noise contributed by offset compensation circuits. Third, a low-gain input stage could achieve the following goals: minimizing main noise contributing devices; amplifying signal to attenuate noise from the following circuits; limiting gain to prevent large sensor position offset from saturating the circuit from the beginning; limiting gain to reduce Miller effect.
The schematic of the first stage amplifier is shown in Fig 4.3. The overall gain is 44dB. The CDS will double the output voltage so that its gain is 6dB. The first stage
Figure 4.3: The schematic of the first stage amplifier.
is an open-loop amplifier with a gain of about 16dB. The open-loop amplifier A1 architecture is believed to have better noise performance because it suffers less from noise folding compared with transimpedance amplifiers and capacitive feedback amplifiers [8]. Transistor m5 and m6 draw the DC current from the load branch to increase the impedance of the diode-connected load transistors to ensure proper gain.
The input transistors m1, m2 and load transistors m3, m4 are of the same type, so the
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temperature dependences of the input and load transistors will cancel each other out, making less sensitive to temperature variation.
4.2.2 Electronic Noise Analysis and Design Flow
Electronic noise comes from the following sources as shown in Fig. 4.4: the thermal noise of the input transistor, the flicker noise of the input transistor, the bias noise due to bias current of the diode in the biasing circuit, the noise from the modulation signal, and the noise from the following stages and the load of the circuit. The residue noises from the voltage references and the corresponding switches for generating the modulation signals may be injected into the sensing node, and the bias noise is negligible with small bias current. The noise contributions by the loads and the following stages can be neglected by dividing the first stage gain. The total noise will be dominated by the input transistors. Both thermal noise and flicker noise of the input noise are the critical issue for design consideration.
Figure 4.4: Circuit noise model of the capacitive-sensing frond-end.
A conventional CMOS amplifier has a typical input-referred noise spectrum, as shown in Fig. 4.5. For rather high frequencies, the noise can be considered as
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frequency independent or white. This is called the thermal noise floor. At low frequencies, the noise power increases almost linearly with decreasing frequency and is therefore commonly called flicker noise. The frequency at which the flicker \noise becomes dominant over the white noise is called the flicker noise corner frequency
f
knee.Figure 4.5: Noise power spectrum of standard CMOS amplifier.
The mean square equivalent input noise could be expressed as below:
= + ≅ 2 4 1 + ∆ + ( ) +( ) ∆ (4-1)
where kb is Boltzmann’s constant, T is absolute temperature, W is the MOSFET’s width, L is the MOSFET’s length, Cox is gate capacitance per area, f is frequency, and
K
fp is the PMOS flicker noise coefficient, and gm is transconductance.The PMOS transistors are used as the input pair due to their flicker coefficient is less than NMOS transistors. The design goal is to make the electronic noise to be less than 25% the total noise. Due to the larger gm1, the mean square equivalent input can be simplified as:
= + ≅ 2 4 ∆ +( ) ∙ ∆ (4-2)
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The electronic noise includes the single thermal noise of the input PMOS transistor and single flicker noise of the input PMOS transistor. The K, Kfp
, T, C
ox, and f
(chopper frequency) are constants. The thermal noise depends on the gm1 and flicker noise depends on width and length of input PMOS transistor. As the flow chart shown in Fig. 4.6, we can increase the bias current to make the thermal noise less than half electronic noise. The bias current could be gotten as:= ∙ (4-3)
The input MOS transistor width will be increased to MOS gate-source Cgs less than the parasitic capacitance constraint. The frequency would be increased until the flicker noise is less half of the electrical noise at the frequency, which is the chopper frequency. For this design, the chopper frequency is set to be 100 kHz. Through this design flow, we could get the optimized bias current and input MOS width for the specification design.
Figure 4.6: Electronic power-noise design flow.
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4.3 Chopper Stabilization
Chopper stabilization is a noise reduction technique that modulates the signal to higher frequency where there is no dc offset and less flicker noise, and then demodulates it back to the baseband after amplification. The principle of chopper stabilization is illustrated in Fig. 4.7. The approach applies modulation to transpose the signal to the chopper frequency, while the noise is unaffected. The input signal is modulated to a higher frequency by a square wave modulation carrier at the chopping frequency. Considering the Fourier series of a square wave, the input signal is converted to the odd harmonics frequencies of the modulation signal as shown in Fig.
4.7(b). After the second multiplier, the amplified signal is modulated using the same square wave used before. Therefore, the modulated input signal is demodulated back to base-band while the noise is modulated to the odd harmonics of the chopping frequency as shown in Fig. 4.7(c). The second stage amplifier working as a low-pass filter can be used to reduce the amplitude of the offset and noise. Therefore, if the chopper frequency is much higher than the signal bandwidth, the flicker noise will be greatly reduced with this technique.
In order to maintain a maximum DC gain, the phase shift between the input and the output modulators has to match precisely the phase shift introduced by the amplifier.
But the phase shift could be neglected due to the modulation frequency is order of hundred kHz. Since the noise and the offset are modulated only once, they are transposed to the odd harmonics of the output chopping square-wave, leaving the amplifier ideally without any offset and low-frequency noise. The chopper modulators are most often realized using MOS switches with non-idealities including clock
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feedback and charge injection. These non-ideal effects associated with the switches give rise to residual offset [16].
Figure 4.7: Chopper stabilization technology principle.
4.4 Correlated Double sampling
The correlated double sampling (CDS) technique is used to subtract out error voltage with two sequential samples. The CDS technique which has originally been introduced to reduce the noise produced in charged-coupled devices (CCD's) can be described as an auto-zeroing operation followed by a sample/hold [16]. It is widely used in sampled-data systems and particularly in SC circuits. The technique is illustrated in Fig. 4.8.
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Figure 4.8: Schematic of correlated double sampling.
During phase one, Ccds is charged to the output. During the complementary phase, the output drives the series of the pre-charged Ccds. Due to the input chopping, the output voltage Vo is as:
(1) = [− (1) + (1)] (4-4)
(2) = [+ (2) + (2)] (4-5)
where Verror is the offset and the flicker noise. By inspection of Fig. 4.8, during Φ1, we have
. (1) = − (1) (4-6)
Therefore, duringΦ2, the voltage across Ccds becomes
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. = [ ( ) ( )] ≅ 2 (4-7)
that is showing that the Verror is subtracted by CDS. The output of the first stage amplifier is differential. Therefore, the complete scheme of the method as shown in Fig. 4.8 can be realized that uses two CDS structures working on both outputs. The 2kT/C noise of the output sampling is negligible compared to the input divided byA12.
4.5 Second Stage Circuit Design
The second amplifier stage is a closed-loop capacitive-feedback amplifier based on an operational transconductance amplifier (OTA), whose schematic is plotted in Fig.
4.9. It is implemented with a fully differential folded-cascode architecture.
Figure 4.9: The schematic of the second stage amplifier.
The input differential pair uses long-channel large-width PMOS transistors to reduce the flicker noise. The open-loop gain is designed to be 80 dB with the
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unity-gain frequency at 100 kHz in order to filter the offset and noise. Compared with the open-loop amplifier A1, this closed-loop amplifier A2 can provide larger signal swing with good linearity and increase the dynamic range of the system. Since the operating frequency of the second stage amplifier is low, relatively high gain can be allowed in A2 without adding too much power consumption. The offset tuning signals Vos+ and Vos- are used to remove the offset due to the sensing capacitance mismatch.
The MOS width ratio of Vin
/V
os is set to 3:1 due to the output voltage range after CDS circuit is the order of ten mV. To reduce the MOS width of Vos could increase the tuning range.35
Chapter 5
Implementation
5.1 Simulation
5.1.1 CMOS MEMS Accelerometer Simulation
The software CoventorWare [17] are used for one axial accelerometer simulation.
The finite element model as shown in Fig.5.1 is to create the grid (mesh) for finit element analysis. The finite element method (FEM) often known as finite element analysis (FEA) is a numerical technique for finding approximate solutions of partial differential equations (PDE) as well as of integral equations. In a structural simulation, FEM helps tremendously in producing stiffness and strength visualizations and also in minimizing weight, materials, and costs. FEM allows detailed visualization of where structures bend or twist, and indicates the distribution of stresses and displacements.
Figure 5.1: Finite element model of the one axial accelerometer.
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Figure 5.2 shows the most important modes of the lowest resonant frequencies. This result is obtained from FEM simulations by CoventroWare. The mode in the sensing axis has the lowest resonant frequency, hence the highest sensitivity.
Figure 5.2: Resonant frequency model of the one axial accelerometer.
The calculation result versus simulation result is shown in table 5.1. The sensitivities of calculation and simulation are similar. The proof mass and spring constant of the simulation is smaller due to the mass parameter of the simulation is smaller.
Table 5.1: Calculation versus simulation data
Calculation Simulation
Proof mass (kg) 3.886E-09 3.393E-09
Spring Constant (N/s^2) 9.520E-01 7.557E-01 Resonant Frequency (Hz) 2.491E+03 2.436E-03 Modulate Voltage (V) 3.000E-01 3.000E+00 Sensitivity (fF/g) 1.000E-15 1.101E-15
Sensitivity (V/g) 1.000E-03 1.046E-03
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5.1.2 System Simulation
For system simulation, the following simplifications are made to obtain the lumped-parameter macro-model of the CMOS MEMS accelerometer through the differential equation of displacement and external acceleration of sensor. The lumped-parameter macro-model equation is as:
+ + = (5-1)
The RLC circuit could replace the Eq. 3-1 for system simulation. The equation could be transfer to the equivalent model circuit of the accelerometer as shown in Fig.
5.3. The sensing capacitance equations are as below:
= ⁄(1 − ∙ ) (5-2)
= ⁄(1 + ∙ ) (5-3)
Figure 5.3: Equivalent model circuit of the accelerometer.
where the mechanical parameter could be transfer to the electronic parameter as shown in table 5.2. The proof mass m is equal to L, the spring constant is equal to 1/C, and damping coefficient b is equal to R. The other parameters are used for sensing capacitance simulation. e electrostatic actuator; the electrostatic spring forces; the effect of parasitic capacitance; and the cross-axis sensitivity.
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Table 5.2: Mechanical parameter transfer to electronic parameter
Mechanical Electrical TSMC accelerometer is implemented by TSMC 1P6M 0.18um CMOS mix-signal technology.
The readout circuit operates with supply voltage 1.8V. The circuit is simulated in Cadence design environment using Spectre simulator. The chopper frequency is 100 kHz. The previous layout simulation (pre-simulation) of all corner status is shown in table 5.3. The post layout simulation (post-simulation) of all corner status is shown in table 5.4. The power between pre-simulation and post-simulation is similar, and costs between 29 mW and 54 mW. But there would be input offset voltage occurred on the post-simulation condition. Through Spurious-Free Dynamic Range (SFDR) results, the post-simulation shows the worse linearity. The gain between pre-simulation and pos-simulation are similar. The previous layout simulation (pre-simulation) under voltage variation is shown in table 5.5. The post layout simulation (post-simulation) under voltage variation is shown in table 5.6. The previous layout simulation (pre-simulation) under temperature variation is shown in table 5.7. The post layout simulation (post-simulation) under temperature variation is shown in table 5.8.
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Table 5.3: Pre-simulation of all corner status
TSMC Design TT SS FF FS SF
Vm(V) 0.3 0.3 0.3 0.3 0.3 0.3
Cp(F) 2.50E-13 2.44E-13 2.31E-13 2.46E-13 2.46E-13 2.36E-13
Cs(F) 2.50E-14 2.50E-14 2.50E-14 2.50E-14 2.50E-14 2.50E-14
Sensitivity(V/g) 1.000E-03 1.020E-03 1.068E-03 1.014E-03 1.014E-03 1.049E-03
DC gain 150 148.80 132.04 157.88 189.69 138.22
Output range ±600mV ±624mV ±565mV ±641mV ±769mV ±580mV
SFDR 66.985dB 66.401dB 67.968dB 61.742dB 68.075dB
PSRR+ 202.791dB 198.23dB 153.89dB 131.43dB 200.507dB
PSRR- 188.4dB 124.8dB 125.92dB 107.642dB 188.98dB
Input offset Voltage NA NA NA NA NA
Power (W) 41.617 27.165 59.049 31.660 53.750
Table 5.4: Post-simulation of all corner status
TSMC Design TT SS FF FS SF
Vm(V) 0.3 0.3 0.3 0.3 0.3 0.3
Cp(F) 2.50E-13 2.87E-13 2.58E-13 2.99E-13 2.89E-13 2.86E-13
Cs(F) 2.50E-14 2.50E-14 2.50E-14 2.50E-14 2.50E-14 2.50E-14
Sensitivity(V/g) 1.000E-03 8.902E-04 9.740E-04 8.596E-04 8.850E-04 8.929E-04
DC gain 150 145.34 125.83 154.59 183.57 134.98
Output range ±600mV +512.68mV
-522.17mV
SFDR 57.084dB 63.424dB 55.427dB 47.626dB 60.241dB
PSRR+ 65.822dB 67.90dB 68.68dB 48.97dB 67.68dB
PSRR- 58.39dB 59.62dB 62.46dB 44.75dB 61.06dB
Input offset Voltage 65.29uV 65.09uV 71.16uV 59.57uV 75.56uV
Power (W) 41.632 28.290 58.992 31.680 53.718
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Table 5.5: Pre-simulation under voltage variation
TSMC Design Pre (1.6V) Pre (1.8V) Pre (2V)
Vm(V) 0.3 0.3 0.3 0.3
Cp(F) 2.50E-13 2.07E-13 2.44E-13 2.74E-13
Cs(F) 2.50E-14 2.50E-14 2.50E-14 2.50E-14
Sensitivity(V/g) 1.000E-03 1.167E-03 1.020E-03 9.259E-04
DC gain 150 113.93 148.80 179.29
Output range ±600mV ±529.2mV ±624mV ±663.4mV
SFDR 50.386dB 66.985dB 52.983dB
PSRR+ 111.41dB 202.791dB 193.10dB
Sensitivity(V/g) 1.000E-03 1.053E-03 8.902E-04 8.333E-04
DC gain 150 105.62 145.34 170.06
Output range ±600mV +440.09mV -449.65mV
+512.68mV -522.17mV
+562.73mV -571.58mV
SFDR 63.616dB 57.084dB 57.342dB
PSRR+ 66.81dB 65.82dB 65.53dB
PSRR- 57.78dB 58.39dB 58.97dB
Input offset Voltage 90.51uV 65.29uV 52.04uV
Power (W) 19.733 41.632 74.210
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Sensitivity(V/g) 1.000E-03 1.027E-03 1.020E-03 9.983E-04
DC gain 150 147.60 148.80 158.88
Output range ±600mV ±607mV ±624mV ±626mV
SFDR 51.147dB 66.985dB 49.922dB
PSRR+ 190.22dB 202.791dB 116.73dB
Sensitivity(V/g) 1.000E-03 9.231E-04 8.902E-04 8.876E-04
DC gain 150 140.00 145.34 147.40
Output range ±600mV +510.62mV -519.79mV
+512.68mV -522.17mV
+518.2mV -528.16mV
SFDR 59.731dB 57.084dB 53.997dB
PSRR+ 64.46dB -65.82dB -66.53dB
PSRR- 56.23dB -58.39dB -59.84dB
Input offset Voltage 65.5uV 65.29uV 67.57uV
Power (W) 35.341 41.632 51.681
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These simulation results show the circuit architecture is a robust design. The system simulation results show that the functions are workable under the voltage variation, temperature variation, and all the corner status. But the simulation results of the gain of all status are with large range from 100 to 180. This range comes from the first stage open-loop amplifier design, and the parasitic capacitance variation of the input PMOS.
5.1.3 Input referred Noise Simulation
The noise simulation is achieved by periodic noise analysis with Spectre. The output square noise power after the CDS of the first stage amplifier is shown in Fig.
5.4. We can find that the chopper stabilization and correlated double sampling could almost remove the flicker noise. So that only the thermal noise dominates the electronic noise. Rooting the integration the square noise power from 1Hz to 100Hz being divided by the bandwidth, and then the 24dB gain of the first stage amplifier, the With CDS and CS, the input-referred noise is 9.82nV/√Hz for 100Hz bandwidth, but the noise is 3.23V/√Hz for 100Hz bandwidth without CDS and CS.
5.4. We can find that the chopper stabilization and correlated double sampling could almost remove the flicker noise. So that only the thermal noise dominates the electronic noise. Rooting the integration the square noise power from 1Hz to 100Hz being divided by the bandwidth, and then the 24dB gain of the first stage amplifier, the With CDS and CS, the input-referred noise is 9.82nV/√Hz for 100Hz bandwidth, but the noise is 3.23V/√Hz for 100Hz bandwidth without CDS and CS.