The Schematic of junction-based ΩG MOSFETs is shown in Fig. 1.2. The devices consist of four side gates on an insulating layer, but one of the sides has a gap. To avoid solving for 3-D Poisson equation that is too complicated to be derived, the 3-D JBΩG device can be replaced with two 2-D equivalent double-gate structures and a 2-D equivalent single-gate structure by ignoring the coupling effects for assuming that channel length/channel width and channel length/channel thickness is larger than 2 which fall within the restrictions required to obtain realistic and operational JBΩG devices [13], [19].
Fig. 1.2.1 Schematic of junction-based Omega-Gate MOSFETs: (a) a three-dimensional device structure, (b) with cut plane along y-direction (c) with cut plane along x-direction.
MOSFET and a 2-dimensional single-gate (SG) MOSFET as shown in (b) (c) respectively.
A transition from bulk to multiple-gate fully depleted silicon-on-insulator (SOI) MOSFETs offers higher current drive per unit silicon area and better short-channel immunity. The JBΩG device improves on the planar devices which reduce drain-source current leakage, and the control of the gates on the channel in a JBΩG MOSFET is stronger than that in a conventional MOSFET as the gate voltage is applied from several sides and not just from the top. In recent years, JBΩG MOSFETs have received more attention than the planar MOSFETs in the high speed or high frequency applications.
Comparing JBΩG device to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. JBΩG MOSFETs will be more promising for the future VLSI circuits. Therefore, exploitation and use of ΩG MOSFETs in memory circuits [13]
require the physics-based transistor model [14-17]. The findings of the model are much useful to investigate hot-carrier-induced threshold voltage and offer the basic guidance for the design of memory device.
Chapter 2
QUASI-TWO DIMENSIONAL
SUBTHRESHOLD BEHAVIOR MODEL FOR THE SOI OMEGA-GATE MOSFETs
WITH/WITHOUT LOCALIZED TRAPPED CHARGES
2.1 Quasi-Two Dimensional Subthreshold Behavior 2.1 1111Model for the SOI Omega-Gate MOSFETs
2.1.1 Model Derivation
Instead of solving for the complicated 3-D Poisson’s equation, we present a subthreshold model for junction-based Omega-gate MOSFETs based on the minimum central bottom potential derived from the scaling equation. The junction-based Omega-gate (JBΩG) device with the appropriate aspect ratio can be broken into two equivalent double-gate (DG) transistors and a single-gate (SG) transistor working in y-z and x-z planes, respectively.
W
Si
L
gSiO
2Source Drain
Gate
Gate
n
+p n
+X
Z
V
dsV
gsV
gsMetal
Fig. 2.1.1 Schematic of junction-based ΩG MOSFETs with cut plane along y-direction.
The n-channel junction-based Omega-Gate (JBΩG) cross-section along y-direction is shown in Fig. (2.1.1), the symbols and axes used for modeling are also indicated in this figure. We assume that the impurity density is uniform in the channel region. The channel potential distribution is expressed by( , )
x z
. According to the Poisson equation, the channel potential distribution can be written as eq. (2.1.1).2 2
where Na is the uniform doping concentration of the silicon film, W is the silicon film width (W= tsi), Lg is the device channel length, and the x-axis is perpendicular and the z-axis is parallel to the channel length, respectively.
By using the parabolic potential approach to solve the two-dimensional Poisson’s equation, the potential vertical to the channel direction can be assumed by
2
1 2 3
( , )x z C z( ) C z x( ) C z x( )
(2.1.2)
The boundary conditions of eq. (2.1.2) are as follow:
(1) The central potential Φc(z) is a function of z only.
( , )x z C z1( ) c( )z
(2.1.3)
(2) The electric field at x= -W/2 is determined by the gate and the oxide thickness
2
The surface potential Φs(x) in eq. (2.1.4) and eq. (2.1.5) is given by band voltage of gate bias given as the difference between gate material work function and silicon work function.
fb M si
V (2.1.7)
si is the silicon work function, which is given by
2
Substituting eq. (2.1.4) and eq. (2.1.5) into eq. (2.1.2), we get
2
We can find the channel potential as the combination of the surface and central potentials. It yields
The channel potential at x=0 can be expressed as
Fig. 2.1.2 Schematic of junction-based ΩG MOSFETs with cut plane along x-direction.
The n-channel junction-based Omega-Gate (JBΩG) cross-section along x-direction is shown in Fig. (2.1.2), the symbols and axes used for modeling are also indicated in this figure. It is assumed that the impurity density is uniform in the channel region. The channel potential distribution for single-gate (SG) is expressed by( , )
y z
. According to the Poisson equation, the channel potential distribution can be written as eq. (2.1.14).2 2
where Na is the uniform doping concentration of the silicon film, H is the silicon film width (H=tsi), Lg is the device channel length, and tbox is the buried oxide thickness and the y-axis and the z-axis is perpendicular/parallel to the channel length, respectively.
By using the parabolic potential approach to solve the two-dimensional Poisson’s equation, the potential vertical to the channel direction can be assumed by
2
1 2 3
( , )y z C z( ) C z y C z y( ) ( )
(2.1.15)
The boundary conditions of eq. (2.1.2) are as follow:
(1) The central potential Φc(z) is a function of z only.
( , )y z C z1( ) c( )z
(2.1.16)
(2) The electric field at y= -H/2 is determined by the gate and the oxide thickness
2
(3) The electric field at x= H/2 is zero, because the thickness of tbox is so large that we can ignore the effect of the electric field.
2 band voltage of gate bias given as the difference between gate material work function and silicon work function.
fb M si
V (2.1.20)
si is the silicon work function, which is given by
2
Substituting eq. (2.1.17) and eq. (2.1.18) into eq. (2.1.15), we can find the channel potential as the combination of the surface and central potentials.
The channel potential at y=0 can be expressed as
2
2.1.2 Boundary Conditions Value Problem
By solving the ordinary differential equation, the general solution of eqns. (2.1.11) and (2.1.22) can be expressed as
1 1
( ) z z
C z ae be c
(2.1.25)
The coefficients of a、b in eq. (2.1.25) can be determined by using the boundary conditions at the source/silicon junction and the drain/silicon junction. The potential at the source side is where Vbi=VTln(NaNd/ni2) is the built-in potential at the interface between source/drain and channel and Vds is the drain bias.
The potential at the drain side is
( , ) ( ) for x-z plane device
2.1.3 Scaling Length
Fig1.2 shows that junction-based Omega-Gate (JBΩG) device can be broken into two equivalent DG devices and a SG device working in parallel. According to the
where W and H are the channel width and channel height. The concept of ENG for the MOSFETs is first proposed to by [19] and gives a measure of gate control capability over the channel. The larger ENG provides the device with the better gate control over the channel in comparison to the smaller one. ENG for the Multi-Gate (MG) device can be defined as
λ
SGandλ
MG are the natural length for single-gate (SG) and Multi-Gate (MG). Because the ΩG device comprises one DG working in x-z plane and a fraction of DG、 SG devices working in y-z plane, respectively, the natural length can be determined by the following ENG equation:whereλ DG,1、λ DG,2 andλ SG,1 are the natural lengths for double-gate (DG,1 & DG,2) and single-gate (SG,1) devices working in x-z and y-z plane respectively, and η is the oxide-to-gate underlap coverage factor (OUCF) for the ΩG device.
Fig. 2.1.3 ENG, λ, Lminand ρ, for SG, DG, RG, CG, and SRG MOSFETs,
(Calculating parameters: H = W = 10 nm, tox = 1 nm, OUCF = 0.7 and minimum scaling factor = 3.16) [19]
2.1.4 Minimum Channel Potential
From(2.1.25) (2.1.26) (2.1.27)，the following equations are obtained :
1
We used the 3-D device simulator "DESSIS" [20] to validate the proposed model.
-0.2 -0.1 0 0.1 0.2
M in im u m P o te n ti a l ,
min( V )
Solid line : Model Symbol : DESSIS2.1.5 Threshold Voltage Model
The threshold voltage is defined as the gate voltage which causes the minimum central potential to become two times of bulk potential B that is the difference between the Fermi level and intrinsic level of silicon in the neutral region. Under this condition, the inversion carrier density at the silicon surface equals the density of the doping atoms in the silicon bulk Na. This definition has been physically reasonable and successful in identifying the turn-on condition for bulk devices, where Na -values are in the range of 11016cm-3.
The threshold voltage Vth can be obtained by solving for the gate voltage according
. min
It should be pointed out for the long-channel device, that the coefficients for
approach zeros and eq. (2.1.34) will be reduced to that is the threshold voltage for the long-channel JBΩG MOSFETs.20 40 60 80 100
Channel Length, L (nm)
-0.2 -0.1 0 0.1 0.2
V th ( v ) D IB L ( v )
Solid Line : Model Symbol : DESSIS
tsi= 20 nm Na= 11016cm-3 Nd= 11020cm-3 Vds= 0.1V , 1.0V OUCF= 0.5
tox= 1 nm
tox= 2 nm
tox= 3 nm
Fig. 2.1.5 The dependence of threshold voltage roll-off Vth and DIBL on channel length L for various thicknesses of gate oxide.
Fig. 2.1.5 shows the dependence of threshold voltage roll-off and DIBL versus the channel length for various gate oxide thickness and the data are compared with the 2D numerical simulation results. The threshold voltage roll-off (Vth) and DIBL predicted by the analytical solution is in good agreement with those from numerical simulation.
The plot indicates that the threshold voltage roll-off and DIBL increase rapidly when the channel length decreases, particularly when the gate oxide thickness is increase to 3 nm.
This implies that the gate gradually loses control of the channel as the gate oxide steadily increases its thickness, which prevents the vertical electric field from passing through the channel and brings about severe DIBL. Another efficient method to improve the degradation of the threshold voltage is to make the silicon film thickness thinner as shown in Fig. 2.1.6. The plot indicates that the threshold voltage roll-off increase rapidly when the channel length decreases, particularly when the silicon widths is increase to 20 nm. Fig. 2.1.7 shows the threshold voltage roll-off versus the channel length for different oxide-to-gate underlap coverage factor (OUCF). The small OUCF of 0.1 is preferred to improve the degradation of the threshold voltage. On the contrary, the large OUCF of 0.9 will enhance the threshold voltage roll-off (Vth) and DIBL.
20 40 60 80 100 length L for various silicon film widths.
20 40 60 80 100 length L for various oxide-to-gate underlap coverage factors (OUCF).
2.1.6 Subthreshold Current Model
Based on the parabolic potential approach, the channel potential ΦΩG (x, z) that comprises the surface potential Φs,ΩG and the central potentialΦc,ΩG ,can be written as
2 composed of the minimum central potential and minimum surface potential. This yield
, min min
By substituting x= tsi /2 into eq. (2.1.37) , one obtains the surface minimum potential as
, ,min , ,min ( ) 1 Since the current density for the ΩG device flows predominantly in the z direction (from source to drain), the electron quasi-Fermi potential is essentially constant in the y-direction and is only function of x. By using the drift-diffusion approach (DDA), the current density (both drift and diffusion) together with the electron carrier density at the virtual cathode point can be written as
doping density and Φn(z) is the electron quasi-Fermi potential. By integrating (2.2.39) in x and z directions, the subthreshold current for the ΩG device can be obtained as,min where W is the channel width and H is the channel height. Since the current is constant
along the channel z direction. By integrating eq. (2.1.41) along z direction, the subthreshold current can be obtained by
,min substituted into eq. (2.1.41) and eq. (2.1.42), the subthreshold current for ΩG MOSFET can be obtained.
Figs 2.1.8-2.1.10 shows the plots of subthreshold current model calculated from eq.
(2.1.42) which are compared with those simulated from DESSIS of ISE-TCAD simulator. It is obviously seen that the analytical data from our model be in good agreement with 3-D simulation for different oxide thickness. To investigate how the gate oxide thickness affects the subthreshold current, Fig. 2.1.8 shows the dependence of the subthreshold current on the gate bias with the gate oxide thickness as a parameter. The thinnest gate oxide of tox=1 nm will suffer the least SCEs and brings about the smallest subthreshold leakage current among the three gate oxide thicknesses of tox=1 nm, 3 nm, and 5 nm. Fig. 2.1.9 shows the variation of subthreshold current with the different gate bias voltage with the silicon thickness as a varied parameter. It is obviously seen that as the thickness is reduced, the subthreshold current will be decreased. Fig. 2.1.10 shows the subthreshold current versus the gate bias for the different workfunction. The smallest workfunction of 4.5eV will cause the largest subthreshold leakage current among the three workfunctions of 4.5eV, 4.8eV, and 5.1eV. Although a small workfunction of 4.5eV can result in large subthreshold current, it will induce a small flat-band voltage that is very useful for the low-power application circuits. The trade-off about how to take advantage of low-voltage operation without increasing the subthreshold leakage current must be taken into account as a small gate workfunction is applied for the device.
0.2 0.4 0.6 0.8 1 1.2
Fig. 2.1.9 The subthreshold current versus the gate bias for the different thicknesses of silicon body.
-0.4 0 0.4 0.8 1.2
Gate Bias , Vgs (V)
1x10-15 1x10-13 1x10-11 1x10-9 1x10-7 1x10-5
S u b th re sh o ld C u rr en t ,
I s ( A ) u b
Solid Line : Model Symbol : DESSIS tox= 3 nmW=10 nm H= 10 nm Lg= 40 nm Nd= 11020 cm-3 Na= 11016 cm-3 Vds= 0.05 V OUCF=0.5
: Workfunction= 4.5 eV
: Workfunction= 4.8 eV
: Workfunction= 5.1 eV
Fig. 2.1.10 The subthreshold current versus the gate bias for the different workfunction.
2.1.7 Subthreshold Slope Model
An important parameter characteristic of subthreshold region for junction-based omega-gate MOSFETs operation is subthreshold swing. The junction-based omega-gate MOSFETs operation in the subthreshold region is commonly characterized by the inverse subthreshold slope factor (or subthreshold swing) and defined as
( ) subthreshold slope (SS) is usually represented by the following classical expression.
, ,min , ,min
The central potential is larger than the surface potential for ΩG MOSFETs, which
results in
where
The first term (ln10VT) in the above equation states that the subthreshold slope is 60~70mV/decade for a long channel device. The later term is due to the short channel effects. Fig. 2.1.11 shows analytical solution of the subthreshold slope for omega-gate MOSFETs compared with 2D numerical simulation results with the silicon film thickness as a varied parameter, and good agreements are obtained. The plot indicates that the thinner silicon film for omega-gate MOSFETs has the smaller subthreshold slope than the thicker one does. It reveals that the degradation of subthreshold slope due to DIBL effect can be alleviated by the use of the thin silicon film. On the other hand, the subthreshold swing can also be substantially reduced by making use of the thinner gate insulator. Fig. 2.1.12 shows analytical solution of the subthreshold slope for omega-gate MOSFETs compared with 2D numerical simulation results with the gate insulator thickness as a varied parameter. The thinner insulator makes the gate capacitance smaller and implies lower subthreshold swing. It is found that omega-gate MOSFETs reduces DIBL effect and keeps swing of 60 decade/mV with long channel.
Fig. 2.1.13 shows analytical solution of the subthreshold slope for omega-gate MOSFETs compared with 2D numerical simulation results for different drain biases. It is observed as the drain voltage changed from 0.05V to 3V the subthreshold swing value will not shift very quickly until the channel length is scaled down to 40nm.
20 40 60 80 100
S u b th re sh o ld S lo p e, S (m v /d ec ) Solid Line : Model Symbol : DESSIS
S u b th re sh o ld S lo p e, S (m v /d ec ) Solid Line : Model
Symbol : DESSIS
20 40 60 80 100
Channel Length, L (nm)
60 70 80 90 100
S u b th re sh o ld S lo p e, S (m v /d ec ) Solid Line : Model Symbol : DESSIS
tox=3 nm tsi=10 nm Na=11017cm-3 Nd=11020cm-3 OUCF=0.5
Vds = 0.05 V
Vds = 2 V
Vds = 3 V
Fig. 2.1.13 Analytical solution of the subthreshold slope for ΩG MOSFETs compared with 2D numerical simulation results with the drain bias as a varied parameter.
2.1.8 Results and Discussion
Instead of solving for the complicated 3-D Poisson’s equation, we present a subthreshold model for junction-based omega-gate MOSFETs based on the minimum central potential derived from the scaling equation, where the junction-based Omega-Gate (JBΩG) device with the appropriate aspect ratio can be broken into two equivalent double-gate (DG) transistors and a single-gate (SG) transistor working in y-z and x-z planes, respectively.
Due to the increasing demand for high-performance and low-power-consumption ULSI technology, MOSFETs with sub-20-nm gate lengths are required [4]. As a result of reducing the device dimensions, new 3-D MOS structures with excellent tolerance to short-channel effects (SCEs) are needed. Omega-Gate (ΩG) structures offers higher drive current and better immunity for SCEs compared to DG MOSFETs [21]. The feasibility to fabricate n- and p-channel junction-based ΩG MOSFETs has been demonstrated in recent work.
The effects of different device parameters such as silicon film thickness, gate oxide thickness and drain bias on the model are thoroughly examined. To effectively suppress DIBL and SCEs, a thin oxide, a thin silicon film and a low drain bias can be applied to the device. It is shown that the proposed analytical model matches well with the numerical data over different device parameters.The accurate simulation results of the model make it useful for predicting the device subthreshold characteristics and offer guidance for the basic design of junction-based Omega-Gate (JBΩG) SOI MOSFETs.
Because the quantum-mechanical threshold-voltage variation needs to be taken into account when the silicon thickness drops below 8 nm [11], Quantum Mechanic effects (QMEs) are not considered here for these devices with silicon thickness larger than 10 nm. It should be pointed out that although the quantum mechanical effects (QMEs) for the device is not accounted for in the model, it has been derived in the previous literatures that QMEs will pull up the threshold voltage due to the fact that quantum mechanical channel potential barrier is larger than classical channel potential barrier, which hence increases the gate voltage for inducing the free carrier inversion.
2.2 Quasi-Two Dimensional Subthreshold Behavior 222 Model for the SOI Omega-Gate MOSFETs with 2222Localized Trapped Charges
2.2.1 Introduction
ITRS (International Technology of Roadmap for Semiconductor) [4] has reported that there is a requirement to implement advanced non-classical CMOS structures to overcome the difficult challenges when the semiconductor technology node is below 16nm. Multi-Gate (MG) MOSFETs such as omega-gate (ΩG) MOSFET and FinFET with the non-planar gate can be one of the key solutions to well control the short-channel effects (SCEs), such as the subthreshold voltage roll-off, the drain-induced barrier lowering (DIBL), and the subthreshold-slope degradation, compared with planar MOSFETs. ITRS also reported that the reliability for the novel devices must be characterized for their leading-logic application.As the dimensions of MOSFETs are scaled down to the nanoscale regime, the hot-carrier which effects (HCEs) on Multi-Gate MOSFETs is more obviously. Due to increasing the demand of high packing density of ULSI, the device dimension is needed to be further pushed into deep-submicrometer regime and the hot-carrier effects (HCEs) induced by the high electric field near the drain side will degrade the device/circuits performance [22][23].
HCEs will initiate the impact ionization, which will cause the unintentional gate and substrate leakage current when the accelerated carriers surmount the gate/buried oxide potential barrier and reach the gate and substrate terminals. Moreover, the hot-carrier-induced positive or negative charges can be trapped in the interface between the gate oxide and the silicon film, which can further cause the shift of the threshold voltage and deteriorate the electrical characteristic parameters of the device. Several studies have modeled the hot-carrier-induced threshold voltage of the planar and the double-gate MOSFETs in the past decade [24][25]. Recently, an analytical threshold voltage has been proposed for symmetrical nanoscale double-gate (DG) MOSFETs with an acceptor doping concentration Na=1016 cm-3, including only the effect of positive interface charges [26]. However, there is no thesis to investigate the threshold behavior model of the omega-gate MOSFETs with the localized interface trapped charges. The omega-gate MOSFETs that demonstrate the better short-channel controlling capability,
higher current drive, and shorter scaling length than both planar and double-gate MOSFETs that will be more promising for the future ULSI circuits [27]. Further exploitation and use of omega-gate MOSFETs in memory circuits may require the physics-based transistor model. In this work, by considering the effects of equivalent oxide charges on the flat-band voltage [28], we report a novel short-channel analytical threshold behavior model for the omega-gate MOSFETs with localized trapped charges based on the exact two-dimensional (2-D) solution of Poisson equation and perimeter-weighted-sum approach [29]. The proposed model is verified by the three-dimensional (3-D) numerical simulation DESSIS of ISE-TCAD and explicitly illustrates how the various localized trapped charge conditions and the device structure
higher current drive, and shorter scaling length than both planar and double-gate MOSFETs that will be more promising for the future ULSI circuits [27]. Further exploitation and use of omega-gate MOSFETs in memory circuits may require the physics-based transistor model. In this work, by considering the effects of equivalent oxide charges on the flat-band voltage [28], we report a novel short-channel analytical threshold behavior model for the omega-gate MOSFETs with localized trapped charges based on the exact two-dimensional (2-D) solution of Poisson equation and perimeter-weighted-sum approach [29]. The proposed model is verified by the three-dimensional (3-D) numerical simulation DESSIS of ISE-TCAD and explicitly illustrates how the various localized trapped charge conditions and the device structure