Chapter 2 Quasi-Two Dimensional Subthreshold Behaior Model for the SOI
2.2 Quasi-Two Dimensional Subthreshold Behavior Model for the SOI Omega-Gate
2.2.3 Quasi 2-D Generalized Potential Model
The coupling effects among two 2-D equivalently double-gate structures and a single-gate structure can be ignored by the fact that channel length (Lg)/channel width (W) and channel length (Lg)/channel thickness (H) are larger than 2, which fall within the restrictions required to obtain realistic and operational ΩG devices. Since the most leaky path is along the central of the channel for the 3-D ΩG device (i.e., at the position of (x=W/2, y=H/2, z), the 3-D potential of Φ(x=W/2, y=H/2, z) can be equivalently decomposed of 2-D central potential of Φ(x=W/2, z) for two double-gate (DG) MOSFETs and a single-gate.
Based on the exact two-dimensional (2-D) solution of Poisson equation, the central potential Φc,i(z) (i=1,2,3) for ΩG MOSFET can be expressed as
,1( ) 1 G 1 G ,1
2 (2 2)
From (2.1.10), we can obtain the surface potentials in regions of 1, 2 , and 3 as
,1 ,1
With the parabolic potential approach, the channel potential of ΩG i that comprises the surface potential s i, and the central potential c i, can be written as
2
, 2 , ,
( ) ox ( )
i c i gs fb i s i
si
x C V V x
C H (2.2.17) where Na is the uniform doping concentration of the silicon film, tox is the gate oxide thickness, tsi is the silicon film thickness, εsi is the dielectric constant of silicon (si=11.78.8510-14 ), ox is permittivity of oxide (ox=3.98.8510-14), Vgs is the gate bias, and Vfb1=Vfb3
is the flat-band voltage in the undamaged regions. In the damaged
region, due to the effect of equivalent oxide charges on the flat-band voltage, we obtain2 1 0 1
1 ( )
[ tox ] f
fb fb it fb
ox ox ox
x x qN
V V dx Q V
C t C
(2.2.18)where ρ(x) is localized oxide charge density assumed zero for simplicity, Cox
is the gate
oxide capacitance per unit area, and Qit= qNfis the uniform localized interface trapped
charge density.To verify the proposed model, the published 3-D device simulator, “DESSIS”, is performed to simulate the device. Fig. 2.2.2 shows the dependence of channel potential on the normalized channel position for the different ratios of damaged zone to undamaged zone. As the length of the damaged zone increases, the deformation of the potential barrier increases. In the case of the negative interface fixed charges, the minimum bottom potential appears in the damaged zone, whereas in the case of the positive interface fixed charges, it appears in the undamaged zone. This implies that a large Vth shift would be observed in the former case. It is shown that the damaged device with positive trapped charges will decrease the potential barrier between the source side and drain side in comparison to the fresh device. It will increase the threshold voltage degradation of the fresh device. On the other hand, the device with the negative trapped charges will increase the potential barrier between the source side and drain side (i.e., increasing DIBL). It will decrease the threshold voltage degradation of the fresh device (i.e., decreasing DIBL).
0 0.2 0.4 0.6 0.8 1 Normalized Channel Length, z/L
g-0.2 0 0.2 0.4 0.6 0.8 1 1.2
C h a n n el P o te n ti a l, x = W /2 ,y = H ,z V )
Line :Model Symbol :DESSIS Vds= 0.05 V Vgs= 0.2 V
tox= 3 nm H= 20 nm W= 20 nm Lg= 100 nm
a=1cm-3
d=1cm-3
f=1cm-2
Ld+Ls= 90 nm
Ld : Ls = 8 : 1
Ld : Ls = 4 : 5
Ld : Ls = 2 : 7
Ld +Ls = 0 nm Fresh Device
Damaged Device with +Nf Damaged Device with -Nf
Fig. 2.2.2 The dependence of channel potential on the normalized channel position for the different ratios of damaged zone to undamaged zone.
2.2.4 Threshold Voltage Model
The minimum central potential in eq. (2.2.1)-eq. (2.2.3) can be obtained as
,1,min 2 1 1 ,1
(2.2.14)-eq. (2.2.17), respectively. This yield
2
The coefficients in eq. (2.2.22)~ (2.2.24) are expressed as
i 1 4 i i
1 1 2 negative/positive trapped charges on the threshold voltage degradation. This interface
trapped charge induced threshold voltage degradation is called “ITTVD=
Vth,Damaged-Vth,Fresh (V)”. For the positive trapped charges, large thickness of H=40 nm will suffer more ITTVD than the small one of H=20 nm when Ld
is increased. However,
the large thickness of H=40 nm with negative trapped charges will suffer less ITTVD than the small thickness of H=40nm until the normalized damaged zone of Ld/Lgis
increasing beyond 0.5 (called critical ratio of damaged zone to the channel region denoted by CR≈0.5). In other words, to resist ITTVD caused by the negative trapped charges, the larger H is preferred only if CR<0.5. Fig. 2.2.4 shows the dependence of threshold voltage degradation on the normalized damaged zone for different gate oxide thicknesses. The localized trapped charges with large normalized damaged zone will cause great threshold voltage degradation, especially for the thick oxide thickness. To reduce ITTVD, not only the thin gate oxide should be accounted for, but also the small damaged zone must be desired for the device. Fig. 2.2.5 depicts the dependence of the threshold voltage roll-off on the gate length for both damaged and fresh devices. The ITTVD may be coupled with the DIBL. Since the ITTVD caused by the negative trapped charges (i.e., threshold voltage roll-up as shown in Figs. 2.2.3-2.2.4) has an opposed effect to DIBL, the threshold voltage roll-off for the negative trapped-charge device will be decreased and become less than that for the fresh device when the channel length is decreased. On the contrary, the ITTVD caused by the positive trapped charges (i.e., threshold voltage roll-off as shown in Figs. 2.2.3-2.2.4) takes the same effect as DIBL and the threshold voltage roll-off for the positive trapped-charge device will be enhanced and become more than that of the fresh device. Although the negative trapped charge can alleviate DIBL, it will bring about the large threshold voltage. This could be an obstacle for the low-voltage circuit application. It should be pointed out that if both Lg/H <2 and Lg/W<2, the coupling effects among two double-gate and a single-gate MOSFETs cannot be negligible [14] and it can cause the large discrepancy between the model and numerical simulator. This clearly explain why when channel length is further reduced toward into 40 nm in Fig. 2.2.5, both Lg/H <2 and Lg/W<2 will yield the large deviation between results of the analytical model and those of 3-D numerical simulation. 2-D model can accurately predict the threshold voltage of ΩG transistor as long as Lg/H >2 and Lg/W>2. Otherwise, 3-D model is required to simulate the ΩG device accurately. With the better control of SCEs than the planar MOSFETs, the advanced non-planar multi-gate (MG) MOSFETs such as the double-gate (DG), omega-gate (ΩG), and quadruple-gate (QG) MOSFETs are the more attractive devicesfor the nanometer MOSFET application. Fig. 2.2.6 shows how the oxide-to-gate under coverage factor (OUCF) affects the ITTVD when the normalized damaged zone Ld/Lg is increased from 0 to 1.0. For the positive trapped charges, the large OUCF of 0.9 is desirable to resist the ITTVD. On the contrary, the small OUCF of 0.1 is preferred to alleviate the ITTVD caused by the negative trapped charges.
It should be pointed out that although the quantum mechanical effects (QM) is not accounted for in the work, it has been derived in the previous literatures [30] that QM will pull up the threshold voltage since the quantum mechanical channel potential barrier is larger than classical channel potential barrier, which will increase the gate voltage for inverting the channel. It can be concluded that the threshold voltage in Fig.2.2.5 will shift upward in parallel by considering QM. The corner inversion effects [31] that induce independent channels with different threshold voltages in the ΩG MOSFETs can be negligible in the model due to Lg/H >2 and Lg/W>2 that will cause almost the same potential between the surface and the corner for the device [32].
0 0.2 0.4 0.6 0.8 1 Normalized Damaged Zone, LdLg
-0.3
Solid Line : Damaged device with Nf
Dash Line : Damaged device with Nf Line : Model Symbol : DESSIS
Fig. 2.2.3 The threshold voltage degradation versus normalized damaged zone for different thicknesses of silicon body.
0 0.2 0.4 0.6 0.8 1
Normalized Damaged Zone, Ld
/
Lg-0.5
Dash Line : Damaged device with - Nf Solid Line : Damaged device with +Nf
Fig. 2.2.4 The threshold voltage degradation versus normalized damaged zone for different thickness of gate oxide.
20 40 60 80 100
Fig. 2.2.5 The threshold voltage roll-off versus gate length for both fresh and damaged devices.
0 0.2 0.4 0.6 0.8 1
Normalized Damaged Zone, Ld
/
Lg-0.15
Dash Line : Damaged device with Nf Solid Line : Damaged device with Nf Line : Model
Fig. 2.2.6 The threshold voltage degradation versus normalized damaged zone for different oxide-to-gate underlap coverage factors (OUCF).
2.2.5 Subthreshold Current Model
By accounting for the effects of equivalent oxide charges on the flat-band voltage, a novel interface-trapped-charge-induced subthreshold current model is presented for the junction-based Omega-Gate (JBΩG) MOSFETs based on the quasi-3D scaling equation and Pao-Sah’s integral. It indicates that a thin gate oxide can effectively reduce the subthreshold current degradation caused by the trapped charges. In contrast to the thin gate oxide, a thick silicon film is required to alleviate the subthreshold current degradation caused by the negative trapped charges.
From eq. (2.2.17), the minimum channel potential can be composed of the minimum central potential and minimum surface potential. This yield
, min min
By substituting x= tsi /2 into eq. (2.2.37) one obtains the surface minimum potential as
, ,min , ,min ( ) 1 direction (from source to drain), the electron quasi-Fermi potential is essentially constant in the y-direction and is only function of x. By using the drift-diffusion approach (DDA), the current density (both drift and diffusion) together with the electron carrier density at the virtual cathode point can be written as
doping density and Φn(z) is the electron quasi-Fermi potential. By integrating (2.2.39) in x and z directions, the subthreshold current for the ΩG device can be obtained as,min Where W is the channel width and H is the channel height. Since the current is constant along the channel z direction. By integrating eq. (2.1.41) along z direction, the subthreshold current can be obtained by
,min
(2.2.14)-eq. (2.2.16) are substituted into eq. (2.2.41) and eq. (2.2.42), the subthreshold current for ΩG MOSFET with the interface trapped charges can be obtained.
Interface-Trapped-Charges-Induced Subthreshold Current Degradation
(ITSUBD=log [Ids,damaged]-log[Ids,fresh) is defined by the difference between the fresh and damaged devices for their subthreshold currents in logarithm scales. With the fixed positive/negative trapped charges, Fig. 2.2.7 plots ITSUBD versus normalized damaged zone Ld/Lg for different silicon film thicknesses. Increased the Ld/Lg can further enhance ITSUND for both positive and negative trapped charges. A thick silicon film of H=40 nm is desirable for reducing the ITSUBD caused by the negative trapped charges. On the contrary, a thin silicon film, such as H=20 nm is required to suppress ITSUBD caused by the positive trapped charges. Fig. 2.2.8 shows ITSUBD with Ld/Lg for different gate oxide thicknesses. Irrespective of the polarities for the trapped charges, tox=3 nm induces a smaller ITSUBD than tox=4 nm and tox=5 nm. Although a thin gate oxide is needed to make the device suffer less ITSUBD, it may initiate the oxide leakage current due to the tunneling effects, which will cause the static power consumption. The trade-off regarding how to reduce ITSUBD without inducing the gate leakage current caused by the tunneling effects should be taken into account as the thin gate device is applied for memory circuits. Fig.2.2.9 plots subthreshold current roll-up versus the gate length for damaged and fresh devices. The subthreshold current roll-up (SUBRUP) is defined by the difference between the long-channel and short-channel
devices for their subthreshold currents in logarithm scales. (i.e., SUBRUP =log [Ids,short]-log[Ids,long]). As the gate length is reduced, the damaged device with
negative trapped charges suffers less short-channel effects (SCEs) and has a smaller
SUBRUP than the fresh device. In contrast to the negative trapped charges, the positive trapped charges can enhance SCEs and cause the damaged device more SUBRUP than the fresh device when the gate length is further decreased.0 0.2 0.4 0.6 0.8 1
Normalized Damaged Zone, L
dL
g-6 -4 -2 0 2 4 6
IT S U B D ( A )
Solid Line : Damaged device with Nf Dash Line : Damaged device with Nf
: W=H=20nm
: W=H=30nm
: W=H=40nm
Vds=0.05 V Vgs=0.5 V tox=3 nm Lg=100 nm Ls=0 nm
Na=11016cm-3 Nd=11020cm-3 Nf=11012cm-2 OUCF=0.5
Line : Model Symbol : DESSIS
Fig. 2.2.7 ITSUBD versus normalized damaged zone for different silicon body thicknesses.
0 0.2 0.4 0.6 0.8 1
Normalized Damaged Zone, L
dL
g-6
Solid Line : Damaged device with Nf Dash Line : Damaged device with Nf
Vds=0.05 V
2.2.6 Results and Discussion
The hot-carrier effects (HCEs) that bring about the accumulated interface trapped charges will degrade the device/circuits performance. The generic mechanism of the hot-carrier-induced trapped charges was revealed in the previous literatures. It indicates that the device/circuits degradation with the trapped charges is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In other words, the damaged zone and the interface positive/negative trapped charges can be attributed to DAHC. A numerous of literatures have modeled the hot-carrier-induced threshold voltage of planar and double-gate MOSFETs in the past decade. Until now, there is no thesis to investigate the subthreshold behavior model of the JBΩG MOSFETs including the localized interface trapped charges. In this work, by considering effects of equivalent oxide charges on the flat-band voltage, effective conducting path, and Poisson equation, a novel analytical subthreshold behavior model for JBΩG MOSFETs with the interface trapped charges including threshold voltage is developed. The model thoroughly investigates the effect of localized trapped charges with the different polarities, damaged zones, oxide thicknesses, and channel widths/thicknesses on the threshold voltage degradation. When ITTVD and ITSUBD are prominent and coupled with short short-channel effects, the positive/negative interface trapped charges can increase/decrease threshold voltage degradation caused by DIBL. Besides, the thin oxide will improve the threshold voltage behavior when the interface charges are presented and the damaged zone is increased. Instead of small thickness of silicon film, a large thickness of silicon body is required to resist the ITTVD and ITSUBD when the negative interface trapped charges are presented. The proposed model is verified by the three-dimensional numerical simulation and explicitly illustrates how the trapped charge density with different polarities, damaged zone, oxide thickness, and silicon thickness affect the threshold voltage characteristics.
Chapter 3
TWO DIMENSIONAL SUBTHRESHOLD BEHAVIOR MODEL FOR THE SOI
OMEGA-GATE MOSFETs WITH/WITHOUT LOCALIZED TRAPPED CHARGES
3.1 Two Dimensional Subthreshold Behavior Model 1111for the Single-Gate MOSFETs
3.1.1 Model Derivation
The n-channel junction-based Omega-Gate (JBΩG) cross-section along x-direction is shown in Fig. (3.1.1), the symbols and axes used for modeling are also indicated in this figure. We assume that the impurity density is uniform in the channel region. The channel potential distribution is expressed by( , )
y z
. According to the Poisson equation, the channel potential distribution can be written as eq. (3.1.1) [19].2 2
2 2
( , ) ( , )
0 , 0
a
si g
si
y z y z qN
y t z L
y z
(3.1.1)
Si
HLg
SiO2
Drain Gate
Source
Box
n+ Y p n+
Z
Vds Vgs
Metal
Fig. 3.1.1 Schematic of junction-based Omega-Gate (ΩG) MOSFETs with cut plane along x-direction.
where Na is the uniform doping concentration of the silicon film, tox is the gate oxide thickness, tbox is the buried oxide thickness, tsi is the silicon film thickness, Lg is the device channel length, and the y-axis is perpendicular and the z-axis is parallel to the channel length, respectively. By using the superposition method, the resultant solution
( , )
y z
can be composed with one-dimensional (1-D) potential solution V(y) and 2-D potential solution U(y,z) which satisfy the following 2-D Laplace equation and 1-D Poisson equation, respectively [20].
( , )
y z V y
( )U y z
( , ) (3.1.2)
Substituting eq.(3.1.2) into eq.(3.1.1), we obtain
2 2 2
2 2 2
( , ) ( ) ( , ) a
si
U y z V y U y z qN
z y y
(3.1.3)
1-D Poisson equation
2 2
( ) a
si
V y qN
y
(3.1.4)
2-D Laplace equation
2 2
2 2
( , ) ( , )
U y z U y z 0
y z
(3.1.5)
3.1.2 2-D Boundary Conditions Value Problem
The Poisson equation is solved by using the following boundary conditions:
(A) At the top side, electric flux at the interface of silicon/gate oxide is continuous:
0
where Vgs is the top gate bias, tox is the gate oxide thickness, si is permittivity of silicon (si =11.78.8510-14), ox is permittivity of oxide (ox =3.98.8510-14), and Vfb is the
si
is the silicon work function, which is given by
2
(B) At the bottom side, electric flux at the interface of silicon/buried oxide is continuous ( , ) (C) The potential at the source end is
( ,y z 0) Vbi (0 y tsi)
(3.1.10) Where Vbi=VTln(NaNd/ni2) is the built-in potential at the interface between source/drain and channel and Vds is the drain bias [33].
(D) The potential at the drain end is
( ,y z Lg) Vbi Vds (0 y tsi)
(3.1.11)
3.1.3 1-D Solution
From boundary condition (A) and (B), we get
0
( ) ox gs fb ( )
si ox
y
V V V y
V y
y t
(3.1.14)
( ) 0
y tsi
V y y
(3.1.15)
Using eq.(3.1.14) and eq.(3.1.15), 1-D solution can be obtained as
( ) 2
2
a si
V y qN y ay b
(3.1.16) where
a si si
a qN t
(3.1.17)
a si ox
gs fb
ox
qN t t b V V
(3.1.18)
3.1.4 Scaling Length
By using separation method together with boundary condition, one obtains the following resultant solution of the two-dimensional Laplace equation. From eq. (3.1.5) and by letting
( , ) ( ) ( )
U y z
Y y Z z
(3.1.19) By substituting eq.(3.1.19) into eq.(3.1.5), we obtain'' ''
From boundary condition (A) and (B), one obtain From eq.(3.1.28) and (3.1.29), we obtain
s thickness and silicon thickness. It is obviously seen that both thin insulator and silicon film will be required for the small scaling length which decreases the 2D effects causing DIBL and threshold voltage degradation.
Fig. 3.1.2 The contour plot of the electrostatic scaling length versus insulator thickness and silicon thickness.
3.1.5 Coefficients Solution
The Fourier series coefficients of Pn, Qn, Cn and Dn in the resultant solution of the two-dimensional Laplace equation can are expressed as
2sinh( )
Where γ, η and ρ in above equations are defined as
Fig. 3.1.3 shows the decay of Fourier series Pn, Qn and Dn coefficients versus the term number. Since the Fourier series coefficients decay rapidly, the first term of Pn, Qn, and
D
n will dominate the whole series and be used to derive the threshold voltage according to the minimum surface potential [38].0 4 8 12 16
Term Number , n -0.2
0 0.2 0.4 0.6 0.8
C o ef fi ci en t( P
n,Q
n,D
n)
tox = 3 nm tsi = 10 nm tbox = 100 nm Lg= 40 nm Vgs= 0 V Vds= 0.05 V
a=1cm-2
d=1cm-2
: Dn
: Qn
: Pn
Fig. 3.1.3 The decay of Fourier series Dn, Pn, and Qn coefficients versus the term number.
3.1.6 2-D Generalized Potential Model
The full expression for the potential in silicon channel region is
2
1
2 sin
n n
k z k z
a
n n n n
si n
qN y ay b P e Q e k y
(3.1.39)To verify the analytical body potential model, Fig. 3.1.4 shows the 3-D potential distribution from the device simulator of DESSIS [20]. Fig. 3.1.5 shows the 3-D potential distribution from the model results. It is obviously seen that a close agreement for the 3-D potential distribution between the device simulator and analytical model are obtained. Fig. 2.1.6 shows the variation of the potential Ф(y=0,z) and Ф(y=tsi,z) with the normalized channel length position z/Lg for the different gate biases of Vgs=0V and Vgs=0.2V. A good agreement between the results calculated from our model with those simulated using the device simulator is obtained. It is observed that when the gate bias Vgs is increased from 0V to 0.2V, the minimum potential for both surface at y=0 and y=tsi are increased.
Fig. 3.1.4 The 3-D potential distribution from the device simulator of DESSIS for
Fig. 3.1.5 The 3-D potential distribution from the model results for single-gate device of Vgs=0V.
0 0.2 0.4 0.6 0.8 1
Normalized Channel Length Position , (z/L
g)
0.4 0.6 0.8 1 1.2
P o te n ti a l, y ,z V
: Bottom potential
: Surface potential tox=3 nm
tsi=10 nm Vds=0.05 V Na=11017 cm-2 Nd=11020cm-2
Solid Line : Model Symbol : DESSIS
Vgs=0.2 V
Vgs=0.0 V
Fig. 3.1.6 The variation of the surface potential of Ф(y=0,z) and Ф(y=tsi,z) with the normalized channel length position of z/Lg for the different gate biases of Vgs=0V and Vgs=0.2V.
3.1.7 Minimum Channel Potential
In the single-gate MOSFETs, the subthreshold leakage current mainly occurs at the positions of the minimum potential along the channel. Therefore, the subthreshold behavior can be monitored by the minimum channel potential. From eq. (3.1.39), the minimum potential can be derived by setting ( , )
y z
0z
. Accordingly, the position zmin of the minimum channel potential can be found by
1 1 min
1
ln 2
P z Q
k
(3.1.40) As zmin is solved, the minimum channel potential Фmin for the single-gate MOSFETs can be obtained as
2
min 2 1 1 sin 1 1
2
a si
qN y ay b PQ k y
(3.1.41)
In Fig. 3.1.7, the minimum channel potential is increased as the channel length decreased. The subthreshold leakage current is stronger for short channel length (Lg30 nm), and it leads to threshold voltage roll-off. Besides, the drain-induced barrier lowering effect (DIBL) increases for the shorter channel length. As the potential barrier is reduced by the short channel length, the channel is easily to conduct as the thermal voltage mounts above the barrier height.
-0.2 -0.1 0 0.1 0.2 Gate Voltage , V
gs(V)
0.3 0.4 0.5 0.6 0.7 0.8 0.9
M in im u m P o te n ti a l ,
min( V )
tox = 3 nm tsi = 10 nm tbox = 100 nm Vds = 0.05 V
d = cm-3
a = cm-3 Solid Line : Model
Symbol : DESSIS
Lg = 30 nm
Lg = 40 nm
Lg = 50 nm
Fig. 3.1.7 The variation of minimum surface potential minwith gate bias Vgs for different channel lengths.
3.1.8 Threshold Voltage Roll-off Model
Historically, the most popular Vth definition used in compact modeling is the gate voltage B at which the band bending reaches at the silicon surface [40], where B is the difference between the Fermi level and intrinsic level of silicon in the neutral region.
Under this condition, the inversion carrier density at the silicon surface equals the density of the doping atoms in the silicon bulk Na. This definition has been physically reasonable and successful in identifying the turn-on condition for bulk devices, where Na -values are in the range of 11017cm-3.
In order to solve analytical threshold voltage, we need to rewrite coefficients as a linear equation related to Vgs. From eq. (3.1.17), eq. (3.1.18) and eq. (3.1.32-3.1.35), we get
1 gs 2
1 1 equation related to gate bias Vgs.