Chapter 4 Two Dimensional Subthreshold Behavior Model for the SOI Junctionless
4.2 Quasi-Two Dimensional Subthreshold Behavior Model for the SOI Junctionless
2222MOSFETs with Localized Trapped Charges
4.2.1 Introduction
The ITRS (International Technology of Roadmap for Semiconductor) [4] has reported that nonplanar MOSFETs of double-gate, tri-gate, surrounding-gate, and omega-gate MOSFETs are attractive devices for nanometer scaling. All of these devices show a steep subthreshold slope and low leakage current with a very short channel length. In spite of that, the formation of ultra-sharp and super shallow source/drain junction to suppress SCEs still imposes a constraint about the doping techniques and thermal budget. To avoid these problems, the junctionless (JL) MOSFETs have been proposed [7], [8]. Due to the further exploitation and use of the JLΩG in circuit, it is mandatory to develop the physics-based and feasible device model. Although several previously published literatures have reported the long-channel analytical model for JL double-gate [78], [79], no short-channel threshold voltage models regarding the JLΩG device are proposed by now. In this brief, based on the quasi-2-D scaling equation, an analytical short-channel threshold voltage model for the JLΩG MOSFET is developed.
The model clearly predicts the threshold voltage degradation caused by SCEs such as drain-induced barrier lowering (DIBL).The model not only provides the basic designing guidance for JLΩG devices but also can be easily used to analyze the threshold voltage behavior of the JLΩG MOSFETs for its simple formula and computational efficiency.
ITRS also reported that the reliability for the novel devices must be characterized for their leading-logic application.As the dimensions of MOSFETs are scaled down to the nanoscale regime, the hot-carrier which effects (HCEs) on Multi-Gate MOSFETs is more obviously. Due to increasing the demand of high packing density of ULSI, the device dimension is needed to be further pushed into deep-submicrometer regime and the hot-carrier effects (HCEs) induced by the high electric field near the drain side will degrade the device/circuits performance [63][64]. HCEs will initiate the impact ionization, which will cause the unintentional gate and substrate leakage current when the accelerated carriers surmount the gate/buried oxide potential barrier and reach the gate and substrate terminals. Moreover, the hot-carrier-induced positive or negative
charges can be trapped in the interface between the gate oxide and the silicon film, which can further cause the shift of the threshold voltage and deteriorate the electrical characteristic parameters of the device. However, there is no thesis to investigate the threshold behavior model of the JLΩG MOSFETs with the localized interface trapped charges. The JLΩG MOSFETs that demonstrate the better short-channel controlling capability, higher current drive, and shorter scaling length than both planar and double-gate MOSFETs that will be more promising for the future ULSI circuits. Further exploitation and use of JLΩG MOSFETs in memory circuits may require the physics-based transistor model. In this work, by considering the effects of equivalent oxide charges on the flat-band voltage, we report a novel short-channel analytical threshold behavior model for the JLΩG MOSFETs with localized trapped charges based on the exact two-dimensional (2-D) solution of Poisson equation and perimeter-weighted-sum approach. The proposed model is verified by the three-dimensional (3-D) numerical simulation DESSIS of ISE-TCAD and explicitly illustrates how the various localized trapped charge conditions and the device structure parameters affect the potential distribution, and threshold voltage behavior. The findings of the model are much useful to investigate hot-carrier-induced threshold voltage and offer the basic guidance for the design of the JL omega-gate charge-trapped memory device.
With the effects of interface trapped charges on the flat-band voltage, we report a novel quasi-3D interface-trapped-charge-induced threshold voltage model for JL Omega-Gate (JLΩG) MOSFETs based on the scaling equation including equivalent number of gates (ENG). Quantum effects are not considered here since the quantum-mechanical threshold-voltage variation needs to be taken into account when the silicon thickness drops below 8 nm [17]. It should be pointed out that although the quantum mechanical effects (QME) for the device is not accounted for in the model, it has been derived in the previous literatures that QME will pull up the threshold voltage due to the fact that quantum mechanical channel potential barrier is larger than classical channel potential barrier, which hence increase the gate voltage for inducing the free carrier inversion.
4.2.2 Model Description
The schematic of the 3-D JLΩG MOSFETs is shown in Fig. 4.2.1(a). Figs. 4.2.1(b) and 4.2.1(c) are the two-dimensional (2-D) device structures to derive the model. With various trapped charge distributions, the channel can be divided into three regions.
Region 1 (Lg-Ld-Ls) and region 3 (Ls) denote undamaged zone. Region 2 (Ld) is damaged zone. To avoid solving for 3-D Poisson equation, the 3-D JLΩG device can be genuinely replaced with the two 2-D equivalently JLDG and a JLSG structures working in the x-z plane and y-z plane, respectively.
H two-dimensional JLDG and JLSG MOSFETs as shown in (c), where regions 1, 3, and 2
4.2.3 Quasi 2-D Generalized Potential Model
The coupling effects among two 2-D equivalently JLDG structures and a JLSG structure can be ignored by the fact that channel length (Lg)/channel width (W) and channel length (Lg)/channel thickness (H) are larger than 2, which fall within the restrictions required to obtain realistic and operational ΩG devices. Since the most leaky path is along the central of the channel for the 3-D JLΩG device (i.e., at the position of (x=W/2, y=H/2, z), the 3-D potential of Φ(x=W/2, y=H/2, z) can be equivalently decomposed of 2-D central potential of Φ(x=W/2, z) for two JLDG MOSFETs and a JLSG MOSFET.
Based on the exact two-dimensional (2-D) solution of Poisson equation, the central potential Φc,i(z) (i=1,2,3) for JLΩG MOSFET can be expressed as
,1( ) 1 G 1 G ,1
1 1 2 1 1
2
, 2 , ,
( ) ox ( )
i c i gs fb i s i
si
x C V V x
C H (4.2.17) where Nd is the uniform doping concentration of the silicon film, tox is the gate oxide thickness, tsi is the silicon film thickness, εsi is the dielectric constant of silicon (si=11.78.8510-14 ), ox is permittivity of oxide (ox=3.98.8510-14), Vgs is the gate bias, and Vfb1=Vfb3
is the flat-band voltage in the undamaged regions. In the damaged
region, due to the effect of equivalent oxide charges on the flat-band voltage, we obtain2 1 0 1
1 ( )
[ tox ] f
fb fb it fb
ox ox ox
x x qN
V V dx Q V
C t C
(4.2.18)where ρ(x) is localized oxide charge density assumed zero for simplicity, Cox
is the gate
oxide capacitance per unit area, and Qit= qNfis the uniform localized interface trapped
charge density.4.2.4 Threshold Voltage Model
The minimum central potential in eq. (4.2.1)-eq. (4.2.3) can be obtained as
,1,min 2 1 1 ,1 eq.(4.2.14)-eq.(4.2.17), respectively. This yield
2
The coefficients in eqns. (4.2.22) ~ (4.2.24) are expressed as
i 1 4 i i
1 1 2 negative/positive trapped charges on the threshold voltage degradation. This interface
trapped charge induced threshold voltage degradation is called “ITTVD=
Vth,Damaged-Vth,Fresh (V)”. For the positive trapped charges, large thickness of H=30 nm will suffer more ITTVD than the small one of H=10 nm when Ld
is increased. However,
the large thickness of H=30 nm with negative trapped charges will suffer less ITTVD than the small thickness of H=40nm until the normalized damaged zone of Ld/Lgis
increasing beyond 0.5 (called critical ratio of damaged zone to the channel region denoted by CR≈0.5). In other words, to resist ITTVD caused by the negative trapped charges, the larger H is preferred only if CR<0.5. Fig. 4.2.3 shows the dependence of threshold voltage degradation on the normalized damaged zone for different gate oxide thicknesses. The localized trapped charges with large normalized damaged zone will cause great threshold voltage degradation, especially for the thick oxide thickness. To reduce ITTVD, not only the thin gate oxide should be accounted for, but also the small damaged zone must be desired for the device. Fig. 4.2.4 depicts the dependence of the threshold voltage roll-off on the gate length for both damaged and fresh devices. The ITTVD may be coupled with the DIBL. Since the ITTVD caused by the negative trapped charges (i.e., threshold voltage roll-up as shown in Figs. 4.2.2-4.2.3) has an opposed effect to DIBL, the threshold voltage roll-off for the negative trapped-charge device will be decreased and become less than that for the fresh device when the channel length is decreased. On the contrary, the ITTVD caused by the positive trapped charges (i.e., threshold voltage roll-off as shown in Figs. 4.2.2-4.2.3) takes the same effect as DIBL and the threshold voltage roll-off for the positive trapped-charge device will be enhanced and become more than that of the fresh device. Although the negative trapped charge can alleviate DIBL, it will bring about the large threshold voltage. This could be an obstacle for the low-voltage circuit application. It should be pointed out that if both Lg/H <2 and Lg/W<2, the coupling effects among two double-gate and a single-gate MOSFETs cannot be negligible [14] and it can cause the large discrepancy between the model and numerical simulator. This clearly explain why when channel length is further reduced toward into 40 nm in Fig. 4.2.4, both Lg/H <2 and Lg/W<2 will yield the large deviation between results of the analytical model and those of 3-D numerical simulation. 2-D model can accurately predict the threshold voltage of JLΩG transistor as long as Lg/H >2 and Lg/W>2. Otherwise, 3-D model is required to simulate the JLΩG device accurately. With the better control of SCEs than the planar MOSFETs, the advanced JL non-planar multi-gate (JLMG) MOSFETs such as the JLDG, JLΩG, and JLQG MOSFETs are the more attractive devices for the nanometer MOSFET application. It should be pointed out that although the quantum mechanical effects (QM) is not accounted for in the work, it has been derived in the previous literatures [71] that QM will pull up the threshold voltage since the quantum mechanical channel potential barrier is larger than classical channel potential barrier, which will increase the gate
voltage for inverting the channel. It can be concluded that the threshold voltage in Fig.4.2.7 will shift upward in parallel by considering QM. The corner inversion effects [72] that induce independent channels with different threshold voltages in the JLΩG MOSFETs can be negligible in the model due to Lg/H >2 and Lg/W>2 that will cause almost the same potential between the surface and the corner for the device [73].
0 0.2 0.4 0.6 0.8 1
Normalized Damaged Zone, L
dL
g-0.2 -0.1 0 0.1 0.2
IT T V D ( V )
Solid Line : Damaged device with Nf Dash Line : Damaged device with Nf
Line : Model Symbol : DESSIS
: W=H=10nm
: W=H=20nm
: W=H=30nm
Vds=0.05V tox=3nm Lg=60nm Ls=0nm Nd=11018 cm-3 Nf=11012 cm-2 OUCF=0.5
Fig. 4.2.2 The threshold voltage degradation versus normalized damaged zone for different thicknesses of silicon body.
0 0.2 0.4 0.6 0.8 1 Normalized Damaged Zone, LdLg
-0.2
Dash Line : Damaged device with - Nf Solid Line : Damaged device with +Nf
Line : Model
Fig. 4.2.3 The threshold voltage degradation versus normalized damaged zone for different thicknesses of gate oxide.
Fig. 4.2.4 The threshold voltage roll-off versus gate length for both fresh and damaged devices.
4.2.5 Subthreshold Current Model
By accounting for the effects of equivalent oxide charges on the flat-band voltage, a novel interface-trapped-charge-induced subthreshold current model is presented for the JLΩG MOSFETs based on the quasi-3D scaling equation and Pao-Sah’s integral. It indicates that a thin gate oxide can effectively reduce the subthreshold current degradation caused by the trapped charges. In contrast to the thin gate oxide, a thick silicon film is required to alleviate the subthreshold current degradation caused by the negative trapped charges.
From eq. (4.2.17), the minimum channel potential can be composed of the minimum central potential and minimum surface potential. This yield
2
By substituting x= tsi /2 into eq. (4.2.37) one obtains the surface minimum potential as
, ,min , ,min ( ) 1 direction (from source to drain), the electron quasi-Fermi potential is essentially constant in the y-direction and is only function of x. By using the drift-diffusion approach (DDA), the current density (both drift and diffusion) together with the electron carrier density at the virtual cathode point can be written as
doping density and Φn(z) is the electron quasi-Fermi potential. By integrating (4.2.39) in x and z directions, the subthreshold current for the JLΩG device can be obtained as,min where W is the channel width and H is the channel height. Since the current is constant along the channel z direction. By integrating eq. (4.2.41) along z direction, the subthreshold current can be obtained as
,min substituted into eq. (4.2.42) and the subthreshold current for JLΩG MOSFET with the interface trapped charges can be obtained.
Interface-Trapped-Charges-Induced Subthreshold Current Degradation
(ITSUBD=log [Ids,damaged]-log[Ids,fresh) is defined by the difference between the fresh and damaged devices for their subthreshold currents in logarithm scales. With the fixed positive/negative trapped charges, Fig. 4.2.5 plots ITSUBD versus normalized damaged zone Ld/Lg for different silicon film thicknesses. Increased the Ld/Lg can further enhance ITSUND for both positive and negative trapped charges. A thick silicon film of H=40 nm is desirable for reducing the ITSUBD caused by the negative and
positive trapped charges. Fig. 4.2.6 shows ITSUBD with Ld/Lg for different gate oxide
thicknesses. Irrespective of the polarities for the trapped charges, tox=1 nm induces a smaller ITSUBD than tox=2 nm and tox=3 nm. Although a thin gate oxide is needed to make the device suffer less ITSUBD, it may initiate the oxide leakage current due to the tunneling effects, which will cause the static power consumption. The trade-off regarding how to reduce ITSUBD without inducing the gate leakage current caused by the tunneling effects should be taken into account as the thin gate device is applied for memory circuits. Fig.4.2.7 plots subthreshold current roll-up versus the gate length for damaged and fresh devices. The subthreshold current roll-up (SUBRUP) is defined by the difference between the long-channel and short-channel devices for theirsubthreshold currents in logarithm scales. (i.e., SUBRUP =log[Ids,short]-log[Ids,long]).
As the gate length is reduced, the damaged device with negative trapped charges suffers less short-channel effects (SCEs) and has a smaller SUBRUP than the fresh device. In contrast to the negative trapped charges, the positive trapped charges can enhance SCEs and cause the damaged device more SUBRUP than the fresh device when the gate length is further decreased.
0 0.2 0.4 0.6 0.8 1
Normalized Damaged Zone, L
dL
g-3 -2 -1 0 1 2 3
IT S U B D ( A )
Solid Line : Damaged device with Nf Dash Line : Damaged device with Nf
Line : Model Symbol : DESSIS
: W=H=20nm
: W=H=30nm
: W=H=40nm
Vds=0.05 V Vgs=0.2 V tox=3 nm Lg=60 nm Ls=0 nm
Nd=11018cm-3 Nf=11012cm-2 OUCF=0.5
Fig. 4.2.5 ITSUBD versus normalized damaged zone for different thicknesses of silicon body.
0 0.2 0.4 0.6 0.8 1 Normalized Damaged Zone, LdLg
-3
Solid Line : Damaged device with Nf
Dash Line : Damaged device with Nf Line : Model Symbol : DESSIS
4.2.6 Results and Discussion
The hot-carrier effects (HCEs) that bring about the accumulated interface trapped charges will degrade the device/circuits performance. The generic mechanism of the hot-carrier-induced trapped charges was revealed in the previous literatures. It indicates that the device/circuits degradation with the trapped charges is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In other words, the damaged zone and the interface positive/negative trapped charges can be attributed to DAHC. A numerous of literatures have modeled the hot-carrier-induced threshold voltage of planar and double-gate MOSFETs in the past decade. Until now, there is no thesis to investigate the subthreshold behavior model of the JLΩG MOSFETs including the localized interface trapped charges. In this work, by considering effects of equivalent oxide charges on the flat-band voltage, effective conducting path, and Poisson equation, a novel analytical subthreshold behavior model for JLΩG MOSFETs with the interface trapped charges including threshold voltage is developed. The model thoroughly investigates the effect of localized trapped charges with the different polarities, damaged zones, oxide thicknesses, and channel widths/thicknesses on the threshold voltage degradation. When ITTVD and ITSUBD are prominent and coupled with short short-channel effects, the positive/negative interface trapped charges can increase/decrease threshold voltage degradation caused by DIBL. Besides, the thin oxide will improve the threshold voltage behavior when the interface charges are presented and the damaged zone is increased. Instead of small thickness of silicon film, a large thickness of silicon body is required to resist the ITTVD and ITSUBD when the negative interface trapped charges are presented. The proposed model is verified by the three-dimensional numerical simulation and explicitly illustrates how the trapped charge density with different polarities, damaged zone, oxide thickness, and silicon thickness affect the threshold voltage characteristics.