Large amount of process induced traps exist in high-k dielectric bulk material as mentioned in many papers. We organize IG RTN method and utilize it to detect existing traps in high-k MOSFETs in detail in Chapter 1. Proposed in Chapter 3 is method to profile stress induced traps behavior. For stress induced drain current positive bias temperature instability (PBTI) in high-k nMOSFETs, we apply Fowler-Nordhiem stress at constant voltage without elevating temperature and produce traps which cause apparent 2-levels of gate current noise. Chapter 4 discusses the characteristic and gate current fluctuation after soft breakdown. Finally in Chapter 5, the results of this thesis and suggestions for future works are summarized.
Chapter 2 Random Telegraph Signal of Gate Current for Process
Induced Traps in High-k MOSFETs
2.1 Experimental
2.1.1 Preface
Conventionally, BTI characterization is carried out by periodically interrupting stress to measure electrical parameters, introducing a switching delay between stress and measurement which may give rise to an imprecise or even incorrect result. Recently, a two frequency charge pumping measurement has been utilized to characterize high-k trap properties [2.1][2.2]. First, the charge-pumping current may be too small to be reliably measured in small-size devices at a lower frequency required to probe into the high-k layer. Second, due to the mixture of interface and high-k bulk traps, the two-frequency Charge-pumping method may not be viable when the high-k trap density is comparable to or even less than the interface trap density. Third, charge-pumping current may contain gate leakage as devices are stressed or heavily destroyed even wear out or soft breakdown happen.
In this chapter, a newly developed characterization technique named “Gate Current Random Telegraph Noise” for exploration of high-k and interfacial layer trap properties by measuring the gate current in small-area devices is presented. Single electron capture and emission could be observed. The physic of gate current instability is interpreted in Section 3.2. Based on the temperature and voltage dependence of single charge effect, an analytical model for tunneling mechanism is developed and traps parameters are extracted.
2.1.2 Device Preparation and Previous Work
The devices used in this work are nMOSFETs with a poly-silicon electrode, and a bi-layered gate dielectric stack consisting of HfSiO and an interfacial SiOxNy layer. EOT of stacked dielectrics is 12A.
The gate width is 0.12µm~10µm, and the gate length range from 0.09µm~1µm. The complete procedure is shown in Fig. 2.1. The devices are first subjected to ID-VG and IG-VG measurement, and then “detrap” at low negative gate voltage (VG= -1V, 10s). ID-VG is used to check out normal I-V characteristic of devices and then we chose similar gate dielectric properties to compare that have most the same IG-VG. To avoid pre-existing electrons trapped in the dielectric affect gate current instability, a
“detrap” step is utilized before IG RTN.
2.1.3 IG RTN measurement system
The measurement setup of IG RTN is shown in Fig. 2.2, Fig. 2.3. Gate current is about 10pA ~1nA, three orders of magnitude or more smaller than drain current and hence probe station leakage path is more needed to be calibrated well. It is suggested to have parameter analyzer connecting to probe station directly without passing through switch equipment. On the other hand, large fluctuation may happen as probe needles don’t contact with the pad of wafer well, especially for body contact. The sampling rate is maximum 103 readings per second, that it means there is minimum 1ms of resolution.
RTN phenomenon may be not observed as interval time set too larger due to capture or emission time less than the interval time. RTN happens only during local gate voltage so it’s better to detect varying tight gate voltage step as sampling. Otherwise, area of devices also affects IG RTN articulation;
generally it could be seen more clearly as area of devices going down but magnitude of gate current decreases relatively. So it is a trade-off to gain evidence of IG RTN.
2.1.4 Statistics
The target of RTN measurement is to extract mean capture and emission time and then further profiles traps properties. Therefore, the switch of trap captures and emits electrons must be distinguished. We can determine using naked eye and it is also the most precise method to obtain mean capture and emission time. Nevertheless, it wastes time and not efficient for large amount of data. In our work, we write a program and used a current level that lies in the middle of the high and low current state to differentiate trap holding or releasing an electron automatically. Sequentially, every period of time was added and divided by numbers of events. Consequently, we extracted mean capture and emission time more accurately and can handle much larger amount of data also.
2.2 Cause of 2-Levels Gate Current Fluctuation
2.2.1 Factor of Fluctuation
It is obvious that gate current is more responsible to electrons capture and emission in a trap site than drain/source current in Fig. 2.4. The amplitude, capture and emission time are the critical parameters of random telegraph noise phenomenon and they depend on the trap properties, such as trap depth into dielectrics, trap energy apart from conduction band (valance band if holes are captured and emitted) and magnitude of gate leakage current. Besides, retention of traps holding an electron and how much time an empty trap can capture an electron are also influenced by the electric field distributed among dielectrics and temperature that would involve in the probability of electrons hopping over activation energy mentioned in Chapter 2.
2.2.2 Direct Tunneling Model
Although high-k dielectrics have smaller effective oxide thickness than conventional insulator, SiO2, their physical thickness is still large over 50A. Therefore, the gate leakage current is considered as
direct tunneling current from the substrate to the gate through a trapezoid energy barrier as gate bias is around VG=1.2V. Fowler-Nordhiem tunneling current exists as gate bias larger than 1.8V. In our RTN measurement, all used gate voltages for sampling are below 1.5V and large amount of gate current are direct tunneling current.
Gate current becomes smaller as an electron captured in the trap site in Fig. 2.5. The cause is electron trapped will screen the proximity of the trap and hence suppress the local direct tunneling current. It seems like a big stone laying in the flow of river so the flow rate is apparently rolling off. It is believed that the screen area is small compared with gate area and we know that trap induced direct tunneling current varied locally but not globally.
2.3 Process Induced Traps
2.3.1 Gate Current Waveform
In the following, we start to apply this method to analyze process induced traps behavior. It could not be seen absolutely in every device, and sometimes it is available to observe IG RTN phenomenon;
nevertheless analysis afterward is hard to process for some reasons, such as undistinguishable amplitude, multi-levels gate current states. Here below we show two valuable IG RTN measurement results for process induced traps here and discuss the traps properties in later sections.
First one (PIT1) is measured at T=25℃ shown in Fig. 2.6. Traps start to capture electron as gate bias over 0.9V and then emission. As gate voltage increases, capture events happen more frequently.
The events happen twice during 10 seconds at VG= 0.9V and over 40 times at VG= 1.1V. The other one (PIT2) is shown in Fig. 2.7. Same trend happens with PIT1 as gate voltage varied but on different gate voltage, VG= 0.9V ~1.2V.
2.3.2 Capture and Emission Time
Fig. 2.8 shows the mean capture and emission time gathered statistics from Fig. 2.6 and Fig. 2.7.
Capture time is affected by gate voltage and emission time keeps constant, i.e., the capture time relates to the electric field on dielectrics and electrons stride over barrier to trap sites by tunneling. On the other hand, emission time has no response to electric field and electrons escape does not go through tunneling possibly. Further study will be shown in Section 3.4. Electron occupation factor, ft defined below is shown in Fig. 2.8 [2.3]. RTN is undetectable since the trap is always empty in weak inversion regime (i.e., VG< 0.9V). ft increases linearly in strong inversion regime since 40% at VG= 1V to 80% at VG= 1.15V for PIT1, and saturates as gate voltage going up abidingly. ft of PIT2 also increases linearly since 10% at VG=0.95V to 75% at VG=1.1V but not saturates yet. Electron occupation factor is
e Which is dominated by emission time that is too larger than capture time as we know from Eq. (2.1).
Hence, the saturation happens when electron occupation factor is near the maximum “1”. This result is in accordance with the equilibrium case that ft (=1/(1+exp(ET-EF)/kT) increases as the trap energy becomes more negative with respect to the Fermi level.
2.4 Result and Discussion
Based on the Shockley–Read–Hall statistics [2.4], the carrier capture rate 1/τc can be written in terms of the carrier density (per unit volume) n in the channel, the average velocity of the carriers v, and the average capture cross-section σ as Eq. (2.2), where
τ σ
c nv
= 1 (2.2)
⎟⎠ activation energy for capture. T and v are usually taken to be the equilibrium lattice temperature and average thermal velocity vth. This approximation is invalid at large lateral electric field, and electron heating occurs and affects the electron capture time. Emission time is given as Eq. (2.4) [2.5], g is the
( )
degeneracy factor. The term (EF-ET) represents the trap energy with respect to the Fermi energy. kB are the Boltzmann’s constant.
2.4.1 Trap Energy
From the principle of detailed balance, one can write the ratio of the mean emission time τe to mean capture time τc as below. In nMOSFETs, as the gate bias is increased, the trap occupancy should increase,
and, τc/τe consequently show a decrease. The change in the mark-space ratio of the switching signal with respect to gate voltage indicates which transition corresponds to capture and which transition corresponds to emission of an electron. ET0 is reference trap energy at specific gate bias VG0, such as VG0= 1.025V for PIT1, and ETn is trap energy at relative gate bias VGn as represented in Eq. (2.6). From plot of ETn-ET0 versus VG, relationship of trap energy variation to electric field is understood in Fig.
2.10. The variation is more obvious in PIT2 than in PIT2, and ∆ET/∆VG is about 20meV/0.1V for PIT1 and 50meV/0.1V for PIT2. It seems that these two traps distribute in different position of dielectrics and hence gate voltage produces distinct field change. Basically, trap sitting near poly-gate has larger variation as field changed in the same dielectric. From the measurement result, we may conclude that PIT1 is near the substrate and PIT2 is close to poly-gate but it s not the truth proven in the next section.
The emission time constant is shown below [2.6], where NC is the effective conduction band densities of state. ECd-ET is trap energy difference apart from conduction band of dielectric. The emission time constants τe depends on the energy ET and the capture cross-section σ. The electron thermal velocity and effective density of states in the conduction band are shown in Eq. (2.8), Eq.(2.9), allowing the emission time constant to be written as Eq. (2.10), where γ is a coefficient. A plot of ln(τe T2) versus In our experiment shown in Fig. 2.10-2.11, ECd-ET is about 1.02eV and 1.06eV for PIT1 and PIT2 respectively. It can be seen that there is only a slight variation in ECd-ET as the gate voltage is increasing. These values set the trap around the conduction band edge when compared to ϕ0 =3.1eV [2.7] [2.8], the difference between the electron affinities of Si and IL, consistent with an acceptor trap acting as a repulsive center for electrons in the channel.
2.4.2 Trap Depth
By the principle of detailed balance, a relationship between the mean capture and emission times and trap parameters is found as Eq. 2.11 [2.9], where ECd, EC, EF, ϕ0 and ψs are defined in Fig. 2.13(a).
EOT is the effective oxide thickness and VFB is the flat-band voltage. We can estimate ZT, effective depth from the substrate, from measurements of τc/τe by varying VG. ZT is 5.7A for PIT1and 3.8A for PIT2 shown in Fig. 2.14. It means PIT1 sites into the gate dielectrics is deeper than PIT2 that is obviously contradictory to the assumption in Section 3.4.1. Hence, we could predict PIT1 and PIT2 lying in different type of dielectrics, that PIT1 is in high-k bulk layer and PIT2 is in the interfacial or transition layer. From the prediction, the measurement in Fig. 2.10 is reasonable because electric field variation in high-k bulk layer is small due to large permittivity. To extract reliable effective trap depth, the measurement is repeated in different temperature and result is shown in Fig. 2.15. They result in the same slope and ZT is extracted to same values as varying temperature.
2.4.3 Activation Energy
The capture and emission of an electron in the conduction band by a defect at the Si–IL interface can be explained utilizing a nonradiative multiphonon emission process. It is believed that the nonradiative multiphonon emission occurs due to the crossing of free electronic states with bound electronic states when sufficiently large lattice displacements exist. Before capturing an electron, the defect center will experience thermal vibrations around an equilibrium position close to the upper level
of the energy gap. After this capture, the defect would relocate at a new equilibrium position in the energy gap with shifted coordinates, creating violent lattice vibration at the defect. This instability subsides by damping down the vibration to the thermal vibration amplitude and emitting phonons. At lower temperatures, this relaxation takes longer time, effectively slowing down the switching events.
This thermally activated behavior can be understood in terms of a configuration coordinate diagram of the trap (see Fig. 2.13(b)). An empty trap can be thermally excited to the crossover point B, where it can capture and electron from the silicon conduction band. The occupied trap then relaxes to its lowest stable level and dissipates the excess energy by multiphonon emission. The energy needed for emitting an electron is usually higher than that needed for capturing one [2.10]. The activation energies depend on the trap energy level relative to the silicon conduction band, and therefore, on band bending.
Varying the gate voltage will affect the activation energies. This effect is larger in deep traps (larger ZT).
The plot of characteristic time to 1/kT is shown in Fig. 2.16-2.17. Firstly we see τc and τe increasing intensely as temperature going down. For the capture time, electron thermal energy increases in the channel. Larger temperature enhances electrons hopping over activation energy barrier of capture Ea,capture , same as emission, electrons held in trap have larger possibility to escape over activation energy barrier of emission Ea,emission. Secondly both Ea,emission and Ea,emission are lower with gate bias.
Ea,capture is proven lower than Ea,emission here and decreases intensely as gate bias raising slightly, Ea,capture
varies around 0.38eV~0.61eV, as a result that gate bias would influence activation energy to capture of channel carriers. As illustrated in Fig. 2.18, time constant to tunnel from traps to poly-gate or back to substrate is much longer the time to Frankle-Poole emission.
Procedure
Detraping
VG=-1V, 10s
I G RTN I D -V G
VG=-1V to 2V, Step=0.1, VD=0.05V
I G -V G
VG=0V to 2V, Step=0.1V, VD=0V
Fig. 2.1 The operating procedure of following measurement applied to DUT.
Parameter Analyzer HP 4156C
PC
Probe Station
Fig. 2.2 The measurement setup using Analyzer HP 4156C to sampling as RTN processing. Notably there is no switch equipment HP 5250 here.
HfSiO SiO
xN
ySource Drain
Substrate
+V G
Fig. 2.3 The terminals setup using Analyzer HP 4156C to sampling.
50.5 51.0 51.5 52.0
I
G( x10p A)
(a)
-1.8 -1.6 -1.4 -1.2
I
S(uA)
(b)
2 3 4 5 6 7 8 9 10
1.2 1.4 1.6 1.8
I
D(uA)
Time (s) (c)
Fig. 2.4 Evolution of current for single electron capture and emission. (a) IG, (b) IS, (c) ID.
High-k IL substrate
Empty Direct
Tunneling
(a)
High-k IL substrate
Electron
captured Direct Tunneling
(b)
Fig. 2.5 Schematic plot of gate current instability due to electrons trapped. (a) Trap empty state, (b) Trap filled state.
2 4 6 8 10
Fig. 2.6 Gate current waveform of high-k nMOSFET with process induced trap (PIT1), T=25℃
2 4 6 8 10
Fig. 2.7 Gate current waveform of high-k nMOSFET with process induced trap (PIT2), T=25℃
1.00 1.05 1.10 1.15 1.20 1.25 10-1
100
Gate Voltage, V
G(V)
Capture or Emission Time (sec)
(a)
0.95 1.00 1.05 1.10
10-1 100
Capture or Emission Time (sec)
Gate Voltage, V
G(V)
(b)
Fig. 2.8 Variation of capture time τc (filled symbol) and emission τe (open symbol) as gate voltage increasing (a) PIT1 (b) PIT2.
1.00 1.05 1.10 1.15 1.20 1.25 0.4
0.5 0.6 0.7 0.8 0.9
Gate Voltage, V
G(V)
PIT1
Electron Occupation Factor, ft
(a)
0.90 0.95 1.00 1.05 1.10 1.15
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Gate Voltage, V
G(V)
Electron Occupation factor, ft
PIT2
(b)
Fig. 2.9 Plot of electron occupation factor ft versus gate voltage (a) PIT1, (b) PIT2.
1.03 1.08 1.13 1.18
35 36 37 38 39 40 41 e
-1e
0e
1e
2e
3e
4e
5V
G
=0.95V V
G=1V V
G=1.05V
1/kT ( eV -1 )
τ e T 2 ( K 2 -s )
E Cd -E
T =1.06eV
Fig. 2.11 τeT2 versus 1/kT plots for PIT1. Energy difference between conduction band of dielectric and trap ECd-ET is around 1.06eV.
35 36 37 38 39 40 41 e
-4e
-3e
-2e
-1E Cd -E
T =1.02eV
V
G=1V
V
G=1.025V V
G=1.05V
1/kT ( eV -1 )
τ e T 2 ( K 2 -s )
Fig. 2.12 τeT2 versus 1/kT plots for PIT2. Energy difference between conduction band of dielectric and trap ECd-ET is around 1.02eV.
Ec
Ev E
FE
Cd-E
TZ
Tϕ
0E
FgE
CgTrap
qψ
SChannel High-k IL
poly
(a)
E
a,captureE
a,emissionB
A
C
Normal Coordinate
(b)
Fig. 2.13 (a) Energy band diagram at the trap position in the channel.
(b) Configuration-coordinate diagram for an acceptor trap. Open circle represents an empty trap and solid one is for a filled trap.
1.00 1.05 1.10 1.15 1
2
Z
T=3.8A
PIT2 PIT1
τ c / τ e
Gate Voltage, V
G(V)
Z
T=5.7A
Fig. 2.14 Relationship of τc/τe to gate voltage. The extracted ZT from the slope is 5.7A and 3.8A for PIT1 and PIT2 respectively.
0.90 0.95 1.00 1.05 1.10 1
10 T=12.5
oC
T=25
oC T=37.5
oC T=50
oC
τ c / τ e
Gate Voltage, V
G
(V)
Fig. 2.15 Plot of τc/τe versus gate voltage at different temperature. The slope of plot at different temperature is identical. (i.e., ZT is reliable in our extraction.)
36 38 40
Fig. 2.16 Dependence of characteristic time to 1/kT on distinct gate voltages for PIT1 (a) capture time, (b) emission time. Activation energy Ea is also expressed in the plot.
36 38 40 42
Fig. 2.17 Dependence of characteristic time to 1/kT on distinct gate voltages for PIT2 (a) capture time, (b) emission time. The trend of Activation energy Ea is identical with PIT1.
High-k IL Substrate
PIT1 PIT2
E
Cd-T1E
Cd-T2Direct Tunneling Frankle-Poole
Emission
E
CdFig. 2.18 Schematic plot of capture and emission mechanism. This is proven that electrons could be captured by tunneling from substrate and emitted by Frankle-Poole emission.
Chapter 3 Random Telegraph Signal of Gate Current for Stressed Devices
in High-k nMOSFETs
3.1 PBTI in NMOSFETs with High-k Dielectrics
Bias Temperature Instability is a degradation phenomenon in MOSFETs. Even though the root causes of the degradation are not yet well understood, it is now commonly admitted that under a constant gate voltage and an elevated temperature, a build up of charges occurs either at the interface Si/SiO2 or in the oxide layer leading to the reduction of MOSFETs performances. Unlike SiO2, the high-K dielectrics such as Hf-based dielectrics present serious instabilities for negative and positive bias (NBT), after NBT and PBT (Positive Bias Temperature) stresses. The trapped charges are sufficiently high to represent one of the high-k integration most critical show stopper that causes Vt
instabilities and drive current degradation. The instability is worrying, especially in the case of NMOS PBTI. It has been reported that the HfO2 MOSFETs is limited by nMOSFETs PBTI rather than pMOSFETs PBTI [3.1]. In this section, we focus the discussion on NMOS only.
3.1.1 Threshold Voltage Instability
The NMOS PBTI reported in [3.2] shows an electron trapping (∆Vt >0). The main difference with PMOS NBTI is that the whole Vt shift is recovered. That means that no interface traps are generated at this gate bias stress. As for the NBTI, the PBTI characteristics display a logarithmic law and it can be well explained by the direct tunneling electron trapping. The trapping dynamic can be well explained by the model proposed by [3.3]. As explained below, the Vt shift during the stress can be well
explained by an electron tunneling from channel interface to the acceptor traps in the interfacial or high-k bulk layer, i.e.,
0 The Vt could be characterized by pulsed Id-Vg method only and it is unreliable in D-C measurement system due to transient carriers trapped happening in conventional Id-Vg and C-V methods. The interfacial oxide thickness effect and the interface treatments on the Vt instability have also been reported [3.4][3.5]. Like ∆Vt, saturation drain current Id.sat is heavily degraded owing to amounts of trap generation near the channel. Unlike ∆Vt and Id.sat, sub-threshold swing and maximum transconductance Gm,max do not change with stressing thereby indicating that interfacial trap generation is negligible [3.6].
3.1.2 Trap Generation
Compared with SiO2, high-k based material dielectrics have severe reliability issue post stress operation and affect regular I-V characteristics. In [3.7], the degradation is investigated to exhibits two stages, different degradation rate and stress temperature dependence. The drain current degradation in the first stage is attributed to the charging of pre-existing high-k dielectric traps while the degradation in the second stage is mainly due to additional high-k trap creation by transient measurement system.
Compared with SiO2, high-k based material dielectrics have severe reliability issue post stress operation and affect regular I-V characteristics. In [3.7], the degradation is investigated to exhibits two stages, different degradation rate and stress temperature dependence. The drain current degradation in the first stage is attributed to the charging of pre-existing high-k dielectric traps while the degradation in the second stage is mainly due to additional high-k trap creation by transient measurement system.