Noise Amplitude

Gate current and step amplitude of gate current is plotted in Fig. 3.17. Gate current of SIT1 is lower due to lower direct tunneling at VG= 0.8V~1V and step amplitude is also smaller. Gate current is large about 1~2nA and step amplitude is about 100pA. Step amplitude increases with gate current and

∆IG/IG,high is fixed about 10%.

3 4 5 6 7 10

²⁰

10

²¹

High-k layer

fresh

PBTI @ Vg=1.8V, 25

⁰

C, 500sec PBTI @ Vg=1.8V, 85

⁰

C, 500sec

Traps Density, N

T

( cm

-3

)

Effective Depth, Z

_Eff

(A)

NMOS W/L=10/1um

IL

Fig. 3.1 Plot of trap density versus effective depth Zeff. This profile plot is derived by Charge Pumping method.

Procedure

Stress

Detraping

I

_G

RTN I

_D

-V

_G

I

_G

RTN

I

_G

RTN

Cycling

Fig. 3.2 Typical procedure of following analysis in stressed devices. 3^rd step

“Stress“ would continue if 4^th step “IG RTN” has no observation of 2 levels of gate current noise.

2 4 6 8 10 12

Fig. 3.3 Evolution of gate current during stress. (a) High-field stress, VG=2.5V, (b) Low-field stress, VG=2.1V. Other terminals are grounded.

0.0 0.7 1.4 2.1 tunneling current at low VG and F-N tunneling current appears at high VG. VD=0.05V, VS=VB=0V

Degradation

Poly

IL High-k

- - - -

--

--

-(a)

- - - -

--

--

-Poly

IL High-k

(b)

Fig. 3.6 Schematic plot of F-N stress. (a) Low VG (b) High VG

700

Fig. 3.7 Gate current waveform of high-k nMOSFET with high-field stress induced trap (SIT1), T=25℃

2 4 6 8 10 12 14 16 18 20

Fig. 3.8 Gate current waveform of high-k nMOSFET with low-field stress induced trap (SIT2), T=25℃

0.80 0.85 0.90 0.95 1.00 10^-1

10⁰ 10¹

V

G

(V)

Time ( sec)

(a)

1.25 1.30 1.35

10^-1 10⁰ 10¹

Time (sec)

V

G

(V)

(b)

Fig. 3.9 Variation of capture time τc (open symbol) and emission τe (filled symbol) as gate voltage increasing (a) SIT1 (b) SIT2.

0.80 0.85 0.90 0.95 1.00 0.1

0.2 0.3 0.4 0.5 0.6 0.7

V

G

(V)

E lectron Occupation Factor, f

t

(a)

1.20 1.25 1.30 1.35 1.40

0.1 0.2 0.3 0.4 0.5 0.6 0.7

V

G

(V)

El ect ron Occupat ion F act or, f

t

(b)

Fig. 3.10 Electron occupation factor versus gate voltage plots, (a) high field stress induced trap (SIT1), (b) low field stress induced trap (SIT2).

Ec

Fig. 3.11 Schematic plots of band diagram in high-k dielectrics MOSFETs. (a) Electrons tunneling from gate model and specific defined parameters, (b) relative trap energy position at low VG, (c) relative trap energy position at high VG.

0.8 0.9 1.0

10

⁰

10

¹

Gate Voltage, V

_G

(V)

Z

_t

=3.2A (from gate) τ

c

/ τ

e

(a)

1.26 1.29 1.32 1.35

10⁰ 10¹

Gate Voltage, V

_G

(V) τ

c

/ τ

e

Z

t

=3.7A

(from substrate)

(b)

Fig. 3.12 Capture time to emission time ratio versus gate voltage plots. (a) high field stress induced trap (SIT1), (b) low field stress induced trap (SIT2).

0.800 0.85 0.90 0.95 1.00 20

40 60 80

V

_G

(V) Trap Energy Variation,

∆

E

T

(meV)

(a)

1.275 1.300 1.325 1.350 1.375

-120 -100 -80 -60 -40

Trap Energy Variation,

∆

ET (meV)

V

G

(V)

(b)

Fig. 3.13 Trap energy variation respect to gate voltage plots (a) positive movement in high field stress induced trap (SIT1) (b) negative movement in low field stress induced trap (SIT2).

36 37 38 39 40 41 e

²

e

³

e

⁴

e

⁵

e

⁶

e

⁷

E Cd -E

T =1.2eV

τ e T 2 ( K 2 -s )

V

G

=0.85V V

G

=0.875V V

G

=0.9V

1/kT ( eV ^-1 )

Fig. 3.14 τeT² versus 1/T plots for SIT1. Energy difference between conduction band of dielectric and trap Ecd-ET is around 1.2eV.

36 38 40 42

Fig. 3.15 Dependence of characteristic time to 1/kT on distinct gate voltages for SIT1 (a) capture time, (b) emission time. Activation energy Ea is also expressed in the plot.

High-k IL

F-P emission

Gate Channel

Fig. 3.16 Diagram of electrons captured/emitted mechanism from channel or poly-gate.

0.80 0.85 0.90 0.95 1.00

Gate Current, I

G

(x100pA)

Gate Voltage, V

Gate Current, I

G

(x100pA )

Gate Voltage, V

G

(V)

∆ I

_G

I

_G,low

(b)

Fig. 3.17 Magnitude of gate current plot, (a) SIT1 (b) SIT2.

Chapter 4 Random Telegraph Signal of Gate Current for Post Soft

Breakdown Devices in High-k nMOSFETs

4.1 Time Dependence Dielectric Breakdown

It has been observed that SiO2 has strong thickness dependence in terms of intrinsic Weibull distribution [4.1] and the dependence can be explained by percolation model [4.2]. The breakdown failure mechanism in high-k gate dielectrics under constant voltage stress in inversion and accumulation mode is physically analyzed with the aid of high resolution transmission electron microscopy. The results show that the breakdown phenomenon in high-k gate dielectrics is different from that of ultrathin SiOxNy and Si3N4 gate dielectrics. Dielectric breakdown-induced epitaxy, which is the failure defect responsible for breakdown in SiOxNy and Si3N4, has also been observed in HfO2

but in a slightly different morphology. The microstructural damages observed in the breakdown of HfO2 gate dielectrics are probably related to HfSix, and HfSiOx, formation during BD event [4.3].

4.1.1 Soft and Hard Breakdown

Hard breakdown of gate dielectrics can be detected by large changes in the voltage or current during stress, while soft breakdown is characterized by smaller offsets in the DC characteristics and an abrupt increase in electrical noise. After constant-current stress, low values of post-breakdown voltage indicate a more abrupt, hard breakdown, while higher values, close to the stress voltage, indicate soft breakdown. An increase is observed in the incidence of soft breakdown as to, decreases, such that hard breakdown is rarely observed for thin gate dielectrics, but dominates the behavior of thicker dielectrics.

Additionally, soft breakdown is observed more often when oxides are stressed using lower and more

realistic voltages or current densities. Soft breakdown becomes "softer" and even less abrupt as the thickness or stress is decreased. The characteristic differences between hard and soft breakdown are evident from post-stress I-V curves, with hard breakdown resulting in resistive I-V behavior, while gate current still has an exponential dependence on V, following soft breakdown. For a given thickness, constant voltage testing yields a harder breakdown than constant current stress [4.4]. The post soft breakdown conductance was explained by a multiple trap assisted electron tunneling mechanism in a localized small area of the capacitor. In this model the creation of electron traps in the ultra-thin gate oxide is the most important precursor effect for dielectric breakdown. It was also demonstrated that the ultra-thin gate oxide reliability can be easily overestimated when a constant current stressing is used if the soft breakdown is not taken into account [4.5].

4.1.2 Impact of Soft Breakdown on Device and Circuit Performance

Fluctuations in the gate current directly cause noise at the gate electrode. A series noise-voltage source is required to model the gate noise when the driving impedance is small relative to the gate impedance. The resultant noise across the gate will cause drain-current fluctuations proportional to the gain of the device and the gate current noise can couple directly into the channel. Additionally, the drain-current noise can be modified by correlations between fluctuations in the gate and drain currents.

For thicker oxides, the l/f drain-current noise is related to the trapping and detrapping of electrons in the channel. However, in thinner oxides there can be an additional process whereby electrons are captured from the substrate and escape through the gate. This carrier-hopping process causes the gate-current fluctuations and leads to drain-current fluctuations, by modulating the channel potential.

Overall, soft breakdown can degrade total device noise in a number of ways, although the precise impact of increased gate noise will depend on the circuit configuration, noise margins, and the device noise prior to soft breakdown. To properly account for these effects, it is essential that gate noise and gate conduction be included in models of devices with ultrathin gate dielectrics [4.4]. Soft breakdown

can produce a strong decrease of the drain current and transconductance in MOSFETs with small width.

This effect is due to the formation of a localized oxide damaged region likely trapping negative charge over a large portion of the channel width, around the SB conductive path. The SB impact on the transistor drain current increases as the stress proceeds and the SB current increases, as the damaged region becomes wider due to thermal dissipation and defect generation. The dielectric defects producing the drain current collapse are distributed over a relatively large area, much wider than the area of the SB conductive path evaluated from the QPC model. This effect is evident in devices with small width and fades as width increases. In large width devices, this effect becomes less important as width becomes larger than the damaged region, as in case of electrically stressed components. From the viewpoint of reliability: extrapolations, while evaluating the device lifetime from stresses on MOS capacitors is widely accepted and well justified in case of oxide lifetime evaluation and large width transistors, it may be questionable in MOSFETs with small width.

4.2 I

_G

RTN in Post Soft-Breakdown Devices

4.2.1 Stress Adjustment

Soft breakdown doesn’t happen certainly as stressing continues. It depends on the dielectric thickness, gate area and stress voltage. Hard breakdown rarely appears as gate dielectric scaling down but it still dominates the breakdown mechanism in high-k dielectric MOSFETs due to larger physical thickness of high-k dielectric layer. Compared with high-k layer, the interfacial layer is hard to get hard breakdown and soft breakdown happens normally during stressing for EOT about only 3~4A. EOT of total dielectrics in our devices is only 12A and it’s easier to observe soft breakdown appearance, nevertheless it still depends on stress voltage. As experience in our measure, smaller gate area is necessary to gain soft breakdown appearance. Too larger gate area would cause the road of soft

breakdown to hard breakdown shorter and it’s difficult to recognize. Breakdown spot happening in large gate area will accumulate the injected carriers and induce more and more breakdown path. It could be avoid in small gate area. Finally, stress voltage is the most critical parameter for soft breakdown observation. Large stress voltage will make dielectrics breakdown faster but it almost hard breakdowns immediately. Adequate small stress voltage is essential but it will need more time to stress aiming at soft breakdown happening. Too small stress voltage would like normal stress and it’s not sure to get breakdown appearance. Summarized, it need more tests on different gate area devices and stress voltage and hence some devices will be failure in need.

4.2.2 I-V Characteristics

As aforementioned, constant current stress (CCS) is likely to obtain soft breakdown than constant voltage stress (CVS). We firstly measure IG-VG at VD=VS=VB= 0V and choose the magnitude of gate current at VG= 2.5V as stress condition of CCS. Fig 4.1 shown the evolution of “gate voltage” at IG= 1.5µA. Measured gate voltage doesn’t change at initial stress and soft breakdown happens about T=2300s. After soft breakdown, the digital SBD could be recognized during wear-out. Drain current degrades initially and has no more degradation after stressing time beyond 500s shown in Fig 4.2(a).

Beside, gate current lasts increasing during stress. In the beginning, gate current is direct tunneling current, stress induced leakage current (SILC) appears after stress, and gate current has apparent jump from SILC to soft breakdown appearance.

4.3 Result and Discussion

4.3.1 Gate Current Waveform

The magnitude of gate current near operating voltage (VG= 1.2V) is less than 1nA in former measurement. It increases to several hundreds of nA when devices suffer soft breakdown as shown in Fig. 4.3. Step amplitude is also much larger about 100nA. In the figure, we not only see one large amplitude but also a small noise existing abstrusely whose amplitude is about 25nA. Hence, two SBD paths exist informational by IG RTN plots. The “on” and “off” of SBD paths involved in gate current plot is shown in Fig. 4.4(a). Four levels of gate current appear and its effect on gate current is very intense that would influence the circuit operation heavily.

The effective area of the conductive region is now given in Fig. 4.4(b) by Eq. 4.1 [4.6], where EOT is the effective oxide thickness. For EOT= 1.2nm and ∆V= 0.16V, the effective area of slow SBD-path is 163nm² which is of the same order of magnitude as in other publication [4.6]

q qEOT

A⁼ε∆E ⁼ ε∆V (4.1)

4.3.2 Capture and Emission Time

Capture time and emission time after soft breakdown paths existing are shown in Fig. 4.5. Capture time has the same trend that we discussed before as schemed of electrons tunneling from channel. It shows logarithmic decrease with gate voltage stepping up and saturates at about 3 seconds at high gate voltage in T= 20℃. Capture time is lower about one order of magnitude as temperature becoming 40℃

and saturates at 0.8 seconds approximately. On the other hand, emission time is so different with those that we measure in prior sections. It is lower and has same variation with capture time here. Emission time does not only depend on temperature but also gate voltage. The clearer dependence is shown in Fig. 4.6. The activation energy of capture time decreases intensely with gate voltage (Ea,capture= 0.62eV, VG= 1.4V; Ea,capture= 0.22eV, VG= 1.55V). Compared with capture time, the activation energy of emission time varies slightly and fits with process and stress induced traps as results that activation

energy of emission is lower at high gate bias.

4.3.3 Model

As shown in Fig. 2.16, 2.17, 3.15(b) and 4.6, emission time prior to soft breakdown is independent of gate voltage and hence it is irrelevant to electric field over dielectrics and channel carriers density.

After soft breakdown, gate dielectrics suffer heavy destroyed and large amount of traps generate. The spot is a capacitor prior breakdown paths appearing and a short circuit after breakdown. There are a conductive path existing and make current flow through without a barrier. Fig 4.7 presents the trap is distributing in 0.93eV below the conduction band of dielectrics and it’s roughly identical with process and stress induced traps. Nevertheless the fit lines in τeT² versus 1/kT plots gradually move upward after soft breakdown. Emission time is dependent with parameters as shown in Eq. 4.2. The Capture cross section σ is assumed as a constant at small gate bias variation prior to SBD but it’s not true after SBD. In section 2, Eq. 2.10 also can be represented as below. The intersection with Y-axis in τeT²-1/kT plots means electron capture cross section σ multiplying with pre-factor γ (−σγ). Prior to SBD, the lines in τeT²-1/kT plots have same slopes and intersection with Y-axis, that it means ECd-ET is fixed and capture cross section is independent of gate bias and temperature. After SBD paths existing, ECd-ET is roughly identical at distinct gate bias. Nevertheless capture cross section varies with gate bias. It shows capture cross section is smaller at high gate bias. The cause comes from large traps generation after SBD and it would change the area and probability of electron capture. Capture cross section increases at large gate bias and it enhances SBD paths area active for capture electrons.

( )

Frankle-Poole emission is a factor besides the gate voltage that affects the conduction band bending and only dependent of the trap energy distribution. In conclusion, the traps distributing near soft breakdown paths will capture and emit electrons as soft breakdown appearance in devices and it will aplenty induce the current through conductive paths.

0 1000 2000 3000

1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6

Gate V o ltage ,V G (V)

Time (sec)

Soft breakdown

Wear-out

Fig. 4.1 Evolution of gate voltage as the device suffered stress. Soft breakdown occurrence and wear-out are represented in the plot.

-0.50 0.0 0.5 1.0 1.5 2.0

Fig. 4.2 Gate and drain current versus gate voltage plots. Open square is the fresh one and an inverted triangle is post soft breakdown one.

20 40 60 80 100

Fig. 4.3 Gate current waveform at different gate voltage during VG=1.4V to 1.475V.

Four levels of gate current are obviously shown and two SBD paths exist.

1.0 1.1 1.2 1.3 1.4 1.5 1.6 Gate Current, I

G

(x100nA)

path 1 , path 2

Fig. 4.4 (a) Relation of SBD paths switch to gate current.

(b) Low and high conductive state involved with gate current versus gate voltage plot. ∆V between IG,low and IG,high is 0.16V.

1.40 1.45 1.50 1.55 10

^-1

10

⁰

10

¹

10

²

Ca pture o r Emissio n Time (sec )

Gate Voltage, V

G

(V) T=20°C

T=40°C

Fig. 4.5 Dependence of capture time (filled symbol) and emission time (open symbol) versus gate voltage plot.

36 38 40

Fig. 4.6 Temperature and gate voltage dependence of (a) capture time and (b) emission time. The activation energy is extracted from the slope of log(Time) to 1/kT plot.

36 37 38 39 e

³

e

⁴

e

⁵

e

⁶

e

⁷

e

⁸

e

⁹

e

¹⁰

e

¹¹

E Cd -E

T =0.93eV

τ e T 2 ( K 2 -s )

V

_G

=1.55V V

_G

=1.5V V

_G

=1.45V V

_G

=1.4V

1/kT ( eV ^-1 )

Fig. 4.7 τeT² verus 1/kT plots at different gate voltage during VG=1.45V to 1.55V. All the plots have the same scale and ECd-ET from the slopes is 0.93eV approximately.

IL High-k

Breakdown path

Gate Channel

F-P emission

IL High-k

Breakdown path

Gate Channel

F-P emission

Fig. 4.8 Schematic plot of band diagram post SBD. Breakdown path occurs and near SBD path trap will capture/emit electrons. Emission is through Frankle-Poole emission.

Chapter 5 Summary and Conclusion

The gate current instability is further studied in this thesis and the behaviors of electrons trap/trapping are analyzed. The method “Gate current random telegraph noise” is arranged coherently for our experiments. Through electric field and temperature dependence, we could understand the physics behind the RTN phenomenon in distinct extent destruction.

Firstly, a new IG RTN method has been successfully implemented to identify the location of traps generated in high-k and interfacial layer. Traps site in high bulk layer that results trap energy level variation less that in interfacial layer. Then, different electrons tunneling mechanism (from the substrate or gate) can be observed for devices under high-field or low-field Fowler-Nordhiem stress.

The depth extraction has also been finished by varied equation. Both PIT and SIT site in about 1eV below the conduction band of dielectric. The temperature dependence of capture and emission time indicate activation energy of capture time will decrease with gate bias as electrons are sourced from channel and increase as electrons from poly gate. Emission is independent with electron source and also decreases with gate bias.

Furthermore, application of the method to SBD reveals that capture and emission time are so different from PIT and SIT. The SBD provides larger electron capture cross section with gate bias that would both influence capture and emission time. An extra leakage path in high-k as a result of breakdown can be well estimated in terms of the size of breakdown path.

In conclusion, this IG RTN method is an effective and direct tool for the diagnosis of generated traps in CMOS with high-k dielectrics and we more understand the physics and the behaviors in high-k dielectrics for distinct extent destruction.

References

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在文檔中 探討高閘極介電層N通道金氧半電晶體的新穎閘極電流隨機電報量測法 (頁 50-0)