Organization

The rest of this thesis is organized as follows. A preview of 3D integration technology is introduced in Chapter 2. Section 2.1 will present the advantage and evaluation of 3D integration. Different kinds of fabrication of 3D integration will be introduced in section 2.2. Especially, the key technology of TSV 3D integration will also be discussed detailed in section 2.3. Although 3D ICs offer many advantages over 2D ICs, many challenges should be overcome before volume production of TSV 3D ICs, and these challenges will be presented in the final of this chapter.

The power TSV placement and optimization in TSV 3D integration is proposed in Chapter 3. The essential power grid analysis of 2D system has been invested at first.

And the TSV electrical characteristic and TSV modeling will be introduced to consider the power supply noise behavior in section 3.2 and 3.3. Increasing the TSV cross section area will reduce the impedance of the PDN structures and as a result mitigate the power noise. However, increase in the dimension and density will reduce the routable area of the stacked dies. Therefore, a design method of power TSV in TSV 3D integration is proposed to derive the adequate TSV parameter in order to satisfy the efficiency condition between power noise reduction and area overhead.

Analysis supply noise regulation in TSV 3D integration is realized in Chapter 4.The optimization of passive decoupling capacitor for reducing power supply noise in 2D system will be discussed in the section 4.1. Section 4.2 describes another scheme for reducing power supply noise, which is using active circuits. In section 4.3,

a noise suppression technique using low power active decoupling capacitors (DECAPs) is proposed for TSV 3D integration. Through the latch-based noise detection circuitry, the power supply noise can be detected and regulated via active DECAPs.

Design methodology of power delivery system in TSV 3D integration is implemented in Chapter 5. Substrate noise canceller and proposed voltage regulator will be introduced in section 5.1 and 5.2. The power delivery system in TSV 3D integration is implemented UMC 65nm technology and TSV model, its simulation result and discussion is realized in section 5.3. Finally, the overall investigation results and conclusions will be discussed in Chapter 6.

Chapter 2

Preview of 3D Integration Technology

In this chapter, it introduces the preview of 3D integration technology. The motivation of IC design from 2D to 3D would be described in Section 2.1. Section 2.2 shows the general categories of 3D integration technology. In addition, the key fabrication technology of TSV 3D integration would be detailed in Section 2.3.

Finally, Section 2.4 would give an introduction for the challenge of TSV 3D integration.

2.1 Why 3D?

As the semiconductor roadmap strides on, packaging and interconnection technologies are required to follow. In order to stay in pace with system demands on scaling, performance and functionality 3D integration is gaining a lot of interest as a solution to this demand [2.1]. The reasons and requirements for 3D integration are however very diverse and often application specific.

A basic reason for 3D-integration is system-size reduction. Traditional assembly technologies are based on 2D planar architectures. Die are individually packaged and interconnected on a planar interconnect substrate, mainly printed circuit boards. The area-packaging efficiency (ratio of die to package area) of individually packaged die is generally rather low (e.g. 5x5mm die in 7x7mm package: 50% area efficiency) and an additional spacing between components on the board is typically required, further

reducing the area efficiency (for example above e.g. 1mm clearance: 30% area efficiency). If we consider the volumetric packaging density, the packaging efficiency drops to very low levels. If in the previous example, we consider the active area of a die to be about 10 μm, and the combined package and board thickness to be 2 mm, the volumetric packaging density is only 0.15%. There is clearly room for improvement of the packaging density.

A different reason for looking at 3D integration is performance driven.

Interconnects in a 3D assembly are potentially much shorter than in a 2D configuration, allowing for a higher operating speed and smaller power consumption.

This is of particular interest for advanced computing applications. Due to the rising on-chip clock speeds, only a limited distance may be traveled by a signal in a synchronous operating mode. Using 3D-IC stacking techniques, more circuits may be packed in a single synchronous region. This requires a technology with 3D interconnects with low parasitics; in particular low capacitance and inductance are needed to avoid additional signal delay. The interconnection of circuit elements can be performed at several levels of the on-chip hierarchy. Of particular interest is the 3D stacking at the so-called “tile-level”. As shown in Fig. 2.1, typical system-on-chip, SOC, devices are constructed of a number of functional blocks. The longest on-chip lines are those that are used to interconnect these tiles. Functional ‘tiles’ on the die are rearranged in multiple die that are vertically interconnected, resulting in much shorter global interconnect These lines are typically in the top-on-chip interconnect layers and are referred to as “global” interconnects in the on-chip wiring hierarchy. Within the tiles, “local“ and “intermediate“ wiring hierarchy levels are mainly used. In a 3D approach, the large die is split in a number of smaller die, using the 3D interconnects as “global” interconnects between the tiles on both die. As this interconnect goes one

or more levels down the traditional IC-pad level, a very high 3D interconnect density is required for such an application.

Fig. 2.1 Conceptual view a 3D stacked SOC.

A third, and maybe most important, reason to consider 3D integration is so-called hetero-integration. As silicon semiconductor technologies continue to scale (vertical scaling), the realization of true SOC devices with a large variety of functional blocks becomes very difficult to achieve. Technologies need specific optimization for logic, analog, memory etc. to reach the desired performance levels and circuit density.

Furthermore, the substrates used to build active devices may vary significantly between technologies, including non-silicon substrates, e.g. compound semiconductors. Also systems may contain other planar components, such as MEMS and integrated passive devices. Besides the ‘vertical’ scaling we are also experiencing a ‘horizontal’ scaling. Realizing the full system on a single SOC die is becoming increasingly difficult and often not economically justified. If however a high-density 3D technology is available, a “3D-SOC” device could be manufactured, consisting of a stack of heterogeneous devices. This device would be smaller, lower power and higher performance than a monolithical SOC approach. Such an approach is the obvious choice for many sensor-array applications. Many sensor applications use particular substrate materials, such as IR and X-ray sensing, that are incompatible

with Si-CMOS processing. These applications require however high-density circuits to read-out the signals from individual sensor pixels, a requirement best met with advanced CMOS technologies. The solution therefore consists in flip-chip (3D) mounting the sensor-array on a read-out electronics chip. Another possible application for this approach is the combination of logic and memory, which is shown as Fig. 2.2.

The left one is 2D interconnect between logic and memory die, and the center is present (2D-SOC) combined logic and memory device, and the Right one is shown

“heterogeneous 3D-SOC” stacking of a memory and logic device with 3D interconnects between individual logic tiles and memory banks.

Fig. 2.2 Different approaches for combining logic and memory

Most applications require a combination of logic and memory. When large amounts of memory are needed, the memory is realized as a separate die, using a high density, optimized memory technology. Due to the use of large busses on the logic and memory die and the use of off-chip interconnects, only a relatively slow and power-hungry interconnect between memory and logic is possible. To overcome these limitations, e.g. for real-time data processing applications, a SOC approach is typically used. Although not optimal for the integration of high-density memory, the IC logic technology is used for integrating large amounts of memory. This allows for allocating smaller pieces of memory (memory-banks) to specific logic blocks.

Distance between logic and memory is short, resulting in the required performance.

The integrated memory is however of the same performance as dedicated

memory technologies would offer. In particular, a much larger die area is consumed by the memory cells, resulting in a die are that is significantly larger than the case with 2 die solutions. 3D interconnect technology may solve this problem, by allowing for logic ‘tiles’ on a first die to directly access memory banks on a memory chip. In this case the number of 3D connections required from the memory die to the logic die will increase by an order of magnitude compared to the I/O count of standard memory devices. Similarly as for the example shown in figure 1, this approach uses 3D interconnects as “global-on chip” interconnect layers to realize a “heterogeneous 3D-SOC” structure.

A new electronics era has begun to emerge, the focus of which is on 3D ICs instead of monolithic integration of heterogeneous functions. While the impact of this approach is profound, it addresses a small part of the system. Therefore, another paradigm shift is illustrated in Fig. 2.3. 3D Systems are leading to unparalleled miniaturization, functionality and cost at system level.

Fig. 2.3 3D Systems from ICs and 3D ICs.

To conclude, there are different motivations for the development of 3D IC solutions:

z Form factor: It can increase density, achieve the highest capacity and volume ratio.

z Increased electrical performances: Which includes shorter interconnects length and improves device speed, and it achieves better electrical insulation (to reduce electrical parasitances in RF applications).

z Heterogeneous integration: Integration of different functions in a 3D IC is available. (RF + memory + logic + sensor + imagers + different substrate materials + …)

z Cost : Cost of 3D integration may be cheaper than to keep shrinking 2D design rules following the ITRS / Moore law

2.2 Categories of 3D integration technology

3D integration is generally defined as fabrication of stacked and vertically interconnected device layers. The large spectrum of 3D integration technologies can be reasonably classified mainly in three categories [2.3][2.4][2.6][2.7][2.8][2.9]:

1. Stacking of packages and Die stacking (without TSVs) 2. TSV technology

3. Monolithic 3D

Fig. 2.4 is a representative schematic illustration of the 3D integration technologies that have been proposed to date and consists of three categories. The first category consists of 3D stacking technologies that do not utilize TSVs and are shown

in Fig. 2.4 (a)-(c). The second category consist of 3D integration technologies that require TSVs (Figure 2 (d)-(e)), and the third category consists of monolithic 3D systems that make use of semiconductor recrystallization to form active levels that are vertically stacked (with on-chip interconnects possibly between). Of course, a combination of all these technologies is possible.

Fig. 2.4 Schematic illustration of various 3D integration technologies

A. Stacking of packages and Die stacking (without TSVs)

The non-TSV 3D systems span a wide range of different integration methodologies [2.4] and [2.5]. Fig. 2.4 (a) illustrates stacking of fully packaged dice.

Although this may offer the advantages of being low cost, simplest to adopt, fastest to market, and modest form-factor reduction, the overhead in interconnect length and low-density interconnects between the two die do not enable one to fully exploit the advantages of 3D integration. Fig. 2.4 (b) illustrates the most common method to stacking memory die, which is based on the use of wire bonds. Naturally, this 3D technology is suitable for low-power and low-frequency chips due to the adverse effect of wire bond length, low density, and peripheral limited pad location for

signaling and power delivery. Fig. 2.4 (c) illustrates the use of wireless signal interconnection between different levels using inductive coupling (capacitive coupling is also possible, but more limiting). This approach is quite elegant for low-power chips that require high-data rate signaling (without the need for TSVs). Power delivery, however, requires use of wire bonds for top dice in the stack, which are not applicable for high-performance/power chips. There are several derivatives to the topologies described above, such as the die embedded in polymer approach. This approach, although different from others discussed, makes use of a redistribution layer and vias through the polymer film, and thus is a hybrid die/package level solution. It is important to note that all non-TSV approaches rely on stacking at the die/package level (die-on-wafer possible for inductive coupling and wire bond) and thus do not utilize wafer-scale bonding. This may serve to impose limits on economic gains from 3D integration due to cost of the serial assembly process.

B. TSV technology

Fig. 2.4 (d) and (e) illustrate 3D integration based on TSVs. The former figure illustrates bonding of dice with C4 bumps and TSVs. The short interconnect lengths and high density of interconnects that this approach offers are important several orders of magnitude larger number of interconnects. Although it is possible to bond at the wafer level, this approach is most suitable for die-level bonding (using a flip-chip bonder) and thus faces some of the same economic issues described above. Fig. 2.4 (e) illustrates 3D stacking based on thin-film bonding (metal-metal or dielectric-dielectric). Not only are solder bumps eliminated in this approach, but also increased interconnect density and tighter alignment accuracy can be achieved when compared to the previous approach due to the fact that these approaches are based on wafer-scale bonding. Thus, they utilize semiconductor based alignment and

manufacturing techniques.

C. Monolithic 3D

Finally, Fig. 2.4 (f) illustrates a purely semiconductor manufacturing (non-packaging) approach to 3D integration. The main enabler to this approach is the ability to deposit an amorphous semiconductor film (Si or Ge) on a wafer during the IC manufacturing process and re-crystallize to form a single-crystal film using a number of techniques.

Ultimately, this approach may offer the most integrated system with least interconnects possible but may not provide chip-size areas for device fabrication in the stack.

Besides, Fig. 2.5 shows the functionality and density of those advanced packaging technology that we have mention above. We can see the TSVs can deliver the highest performance and functionality and be cost effective.

Fig. 2.5 Advanced packaging trends

It is important to note that none of the above described 3D integration

technologies address the need for cooling in a 3D stack of high performance chips.

This is a significant omission and imposes a constraint on the ability to fully utilize the benefits of 3D technology. As such, new 3D integration technologies are needed for such applications.

2.3 Key Technologies and Design Choice of TSV 3D Integration

A number of 3D integration schemes or architectures are available to the system designer. The various 3D architectures for TSV 3D integration are based on the key process technologies of the following as shown as Fig. 2.6 [2.3][2.6][2.7][2.8][2.9]:

1. Stacking approach 2. Wafer (Substrate) selection 3. Bonding method

4. Direction of stacking

5. Fabrication of Thru-Si-Via (TSV)

Fig. 2.6 Enable technology of TSV 3D integration

A. Stacking approach

There are three kinds of stacking approach in TSV 3D integration (see Fig. 2.7):

1. Die to Die or Chip to Chip (D2D) 2. Die to Wafer (D2W)

3. Wafer to Wafer (W2W)

If we using D2D or D2W technology, will the yields be higher than W2W.

Because we can test the chip and find know good die (KGD) before bonding.

Moreover, W2W technology is only suitable for common size. Although D2D or D2W is suitable for both common and dissimilar size, and it has high yields, it has two main shortcomings: handling problem and low throughput.

Fig. 2.7 Stacking approach

B. Wafer (Substrate) selection

There are two kinds of wafer selection has been used today. One is Bulk Si, which includes Si, Ge, or GaAs, and anther is SOI wafer which is shown in Fig. 2.8. High aspect ratio TSV are required in Buck Si wafer, the target length of TSV is equal to 50μm. And it’s the most developed approach today. On the other hand, SOI simplify TSVs formation, avoid the need of a temporary carrier, and allow to stack extremely

thin layers. The BOX layer can be used as stopping layer, so the thickness of 2^nd layer will be more uniform. However, it’s very expensive. It seems that this approach is not cost-effective.

Fig. 2.8 Wafer selection

C. Bonding method

A major 3D bonding architectural choice is between dielectric bonding (Oxide-to-Oxide or Polymer-to-Polymer) and metallic bonding (Metal-to-Metal), which illustrate in Fig. 2.9. In addition to the differences in bonding materials, this choice also has a substantial impact on the details of the interstratum connections. In dielectric bonding, the interstratum connections are completed after bonding by using TSVs to pass through the top die and to connect to the conventional interconnect in the adjacent strata. In metallic bonding, the interstratum connections are completed by bonding pre-existing microconnects, and the interstratum connection may include TSVs. Another major option in the bonding of strata is the choice of wafer-to-wafer, die-to-wafer, and die-to-die bonding. Dielectric bonding typically uses wafer-to-wafer bonding, while metallic bonding is commonly associated with any of the three. Other detail characteristic is shown in Table 2.1.

Fig. 2.9 Bonding Method Table 2.1 Comparison of boding method

Pro. Con.

Metal-to-Metal

1.Metal bonding can be used as extra metal layer

Polymer- 1.Possible tight pitch 1.Good cleanness requirement to- 2.Everywhere is polymer-boned 2.Heat dissipation

Polymer 3.Stronger bond strength than oxide 3.Possible polymer contamination issue

D. Direction of stacking

Further 3D bonding architectural choices relate to the relative orientation of the dice in a 3D stack. The bonding scheme can be face-to-back, or face-to-face, where face refers to the surface on which transistors and the primary interconnect layers are formed and back refers to the Si substrate side of a die. Fig. 2.10 is a schematic illustration of a 3D chip stacking where the left one are bonded face-to- back and the right one is bonded face-to- face.

Fig. 2.10 Direction of stacking

E. Fabrication of Thru-Si-Via (TSV)

According to Fig. 2.11, Fabrication of TSV can be separate into via first and via last.

It depends on the via fabrication step before or after the BEOL process. Via-first approach is challenging by CMOS process. There will be issues with the subsequent CMOS steps at different temperature ranges, so the materials must be CMOS compatible. But it has no yield issue, only good wafers are used. And it has lower cost than via-last. Via-last will not being thermal stress issues, but where the vias etching must be carefully done. However, the yield of the TSV process affects the full process, and it will lower the total yield.

Fig. 2.11 Fabrication of Thru-Si-Via (TSV)

2.4 Challenge of TSV 3D integration

Although 3D ICs offer many advantages over 2D ICs, many challenges should be overcome before volume production of TSV-based 3D ICs becomes possible. These challenges include technological challenges, yield and test challenges, thermal challenges, infrastructure challenges [2.12], etc.

1. Thermal issue—Although the power consumption of a die within a 3D IC is expected to decrease due to the shorter interconnects, the heat removing of a 3D IC is much more difficult than that of a 2D IC. The cause is that the ambient environment of the die of a 2D IC is the cooling material, but the ambient environment of a die within a 3D IC may be another die which also generates heat.

Therefore, the thermal issue of a 3D IC is much severer than that of a 2D IC.

2. Yield issue—3D integration technology may benefit the yield of 3D ICs but may deteriorate the yield of 3D ICs on the other hand. For W2W bonding technology, the yield of a 3D IC is the product of the yields of multiple die and the yield of stacking process. When combining n untested die from wafers with a die yield Yi, then the compound yield of the 3D structure Y can be expressed as Y

2. Yield issue—3D integration technology may benefit the yield of 3D ICs but may deteriorate the yield of 3D ICs on the other hand. For W2W bonding technology, the yield of a 3D IC is the product of the yields of multiple die and the yield of stacking process. When combining n untested die from wafers with a die yield Yi, then the compound yield of the 3D structure Y can be expressed as Y