Design Method for Choosing Height and Number of TSV Bundle

Fig. 3.15 The parameter of the TSV bundle

The parameter of the TSV bundle is shown as Fig. 3.15. The I is the current of each TSV in a TSV bundle, the total current of the TSV bundle can be presented as I . The parameter ‘N’ is the number of TSV bundle which will impact the I on each single TSV. Such that,

I ^I _N (3.35)

V mV 2 ^I _N ^Dµ

D_µ

Dµ

(3.36)

3.4.5 Design Method for Choosing Height and Number of TSV Bundle

According to equation (3.36), the noise of power supply is the function of D (Diameter of TSV) and N (number of TSV in a bundle). As the simulation result, we found that the V decrease when increasing the Diameter of TSV, but the V will be saturation when D is higher than a threshold value (D ). Therefore, we find out the D by solving the following equation

1 (3.37)

V V

D_µ

The result is shown as the Table 5. We find that the threshold value (D ) is more related to the filling material instead the Height of TSV.

Table 3.6 Power TSV design method

Filling by Copp re Filling by Tungsten

D 5.5 I 10.3 D 8 I 17.9

H=60μm

D 6.3 I 10.5 D 9.2 I 17.9

H=80μm

D 7.1 I 10.7 D 10.3 I 18.1

H=100μm

Fig. 3.16 Design Flow to select the Number (N) and Diameter (D)

Hence, we can follow the flowchart, as shown in Fig. 3.16, to choose the suitable Height of one TSV and Number of the TSV bundle. First, setting a TSV bundle with N=2 to estimate I of a TSV. According to different filling material to select different minimum Diameter to calculate the V . If Vnoise is less Vtolerant, you can increase D or increase N to lower the Vnoise. Both in each case, you always need to check that is the D large than D or not, in order to insure that is efficiency when you are increasing the diameter of the TSV.

Finally, the example of power TSV design method is shown in Fig. 3.17. This example shows the following environment: the supply current is 1 A, and the tolerant noise supply voltage is 50mV, and the TSV is filled by copper and its height is 100μm. Fig. 3.17 shows procedures of choosing the power TSV parameter step by step.

Fig. 3.17 Example of the power TSV design method

Chapter 4

Analysis Supply Noise Regulation in TSV 3D Integration

In chapter 3, we already have discussed the power grids system in 2D system, and the characteristic of a TSV. We also estimate the noise of the power grids on a TSV, and then we propose a method to choose the parameters of a TSV bundle. Next, we will discuss the technical of supply noise regulation for providing a robust supply voltage. Robust power delivery is also considered as one of the grand challenges. As predicted in the roadmap for integrated circuit (IC) development from the ITRS-2004 update [4.1], the chip working frequency and supply voltage will continue to scale aggressively, both of which will lead to significant Ldi/dt noises and IR drops on power/ground (P/G) networks, which will further affect the performances and reliabilities of VLSI chips.

Decoupling capacitors are widely used to manage power supply noise.

Decoupling capacitors are an effective way to reduce the impedance of power delivery systems operating at high frequencies. A decoupling capacitor acts as a local reservoir of charge, which is released when the power supply voltage at a particular current load drops below some tolerable level. Since the inductance scales slowly, the location of the decoupling capacitors significantly affects the design of the power/ground (P/G) networks in high performance integrated circuits (ICs) such as

microprocessors. At higher frequencies, a distributed system of decoupling capacitors is placed on-chip to effectively manage the power supply noise.

However, two major constraints limit the usage of passive DECAPs in scaled technologies. First, adding on-chip DECAPs consumes a large amount of die area.

Usually, a total on-chip DECAP of ~100 s of nFs or more have to be deployed on a microprocessor die to keep the supply noise within the target range [4.2]. As a result, in some high-end microprocessor chips more than 20% of the total area has been occupied by DECAPs leading to a significant waste of active die area. Second, adding on-chip DECAPs introduce large amount of gate tunneling leakage that eats into the power budget.

Analysis supply noise regulation in TSV 3D integration is realized in this Chapter. The optimization of passive decoupling capacitor for reducing power supply noise in 2D system will be discussed in the section 3.1. Section 3.2 describes another kind of reducing power supply noise, which all are using active circuits. In section 3.3, a noise suppression technique using low power active decoupling capacitors is proposed for TSV 3D integration. Through the latch-based noise detection circuitry, the power supply noise can be detected and regulated via active DECAPs.

4.1 Optimizations for Passive Decoupling Capacitor

As technology advances the operating voltage levels are reduced aggravating these problems as noise does not scale with technology. The most commonly used solution is to incorporate on-chip decoupling capacitors to the power delivery network to keep the noise within a tolerance margin ensuring circuits functionality. First, we will discuss how to place DECAPs to get a better performance. And then we will introduce the method for MOS decoupling capacitor optimization.

4.1.1 Placing the Passive Decoupling Capacitor

A methodology for efficiently placing distributed on-chip decoupling capacitors to replace one large capacitor has been proposed in [4.3]. A distributed on-chip decoupling capacitor network is an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints in nanoscale ICs. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power delivery system. Hierarchically allocating the on-chip decoupling capacitors greatly relaxes the technology constraints for physically distant capacitors as the Fig. 4.1. The magnitude of the decoupling capacitors is based on the impedance of the interconnect segment connecting a specific capacitor to a current load, and this scheme makes the distant on-chip decoupling capacitors more effective [4.4].

Fig. 4.1 A network of distributed on-chip decoupling capacitors.

In [4.5], the paper show that inserted DECAPs can be detrimental if its distance to the power supply pins is not considered properly for both single line and mesh type circuits. The author propose two metrics: “distance DECAP-switching source” and

“distance DECAP-supply pin”, in Fig. 4.2, to determine the correct insertion position for a DECAP to be effective in reducing power supply noise. Fig. 4.2(a) shows DECAP inserted closer to switching circuit but farther away from supply (configuration A), and Fig. 4.2(b) shows DECAP inserted near supply and switching

circuit (configuration B).

Fig. 4.2 Different location of DECAP

The author calculates the effective distance coefficients: coefficient a is the distance between Vdd pin and DECAP, coefficient a is the distance between switching source and DECAP. The author also observes that the distance DECAP-switching source (coefficient b) increases with the increase in the DECAP size and the distance DECAP-Vdd pin (coefficient a) decreases with an increase in DECAP size. These observations are intuitive: for coefficient a, a greater DECAP will have a greater effective distance from the source; for coefficient b, a greater DECAP has to be closer to the power supply pin in order to be recharged.

4.1.2 MOS Decoupling Capacitor Optimization

With technology scaling down to 90 nm and below, gate leakage current of DECAPs becomes so significant that we have to explicitly consider DECAPs leakage currents for robust P/G grid design. This is especially the case tox when shrinks below 2nm.

In [4.6], the author take a first look at the impacts of gate leakage of practical MOS-based DECAPs on P/G grid designs. To clearly show the influence of gate leakage currents of DECAPs on the P/G grids, the author propose a leakage current model for practical DECAPs. Then, analyzing the effect of leakage currents and show that practical (leaky) DECAPs may increase power consumption significantly and thus demand more routing resource or die area for achieving robust power delivery.

The author proposes a more effective two-stage optimization approach to efficiently optimize P/G grids in the presence of DECAP leakage currents.

Based on minimizing the cost function of implementing DECAPs, a novel optimization technique for determining the optimum channel length of the MOS DECAPs was presented in [4.7]. This approach was applied to the 45nm and 32nm technologies, and the results showed that, on contrary to the conventional belief of setting the DECAP channel length to about 10 times the minimum channel length, the optimum channel length is different from this value and should be calculated individually for each technology node and operating frequency. Next, two optimum DECAP configurations were discussed. One only used NMOS transistors and was suitable for the applications where the area was the main concern. The other was built only by PMOS transistors and was a good candidate for low leakage applications. The comparison table is shown as Table 4.1.

Table 4.1 Specifications of DECAP configurations

4.1.3 Decoupling Capacitor Allocation in 3D IC

Conventional technologies for implementing DECAPs are based on SiO2-based structures that are widely used in robust power delivery network design.

Three-dimensional power grid optimization has been studied in [4.8]. Unlike the 2D case, new considerations come into play while optimizing a 3D power grid using CMOS DECAPs:

Since CMOS DECAPs are usually fabricated using white space on the device layer, they must compete for area with TSVs, or with the landing pads of 3D vias, for the limited white space. This leads to a new resource contention problem. One way to resolve this contention problem is to increase the chip size in order to make room for CMOS DECAPs. However, one of the advantages of 3D circuits over 2D implementations is that they result in a reduced chip footprint: increasing the chip size may counteract this benefit.

Leakage power is an important issue in 3D circuit design. The CMOS DECAPs added to the 3D circuit will consume extra leakage power and make things worse.

While new high-k dielectrics have been proposed, they are not in widespread use yet and even when they are deployed, they will provide temporary relief to the gate leakage problem.

The approach in [4.9] presents an approach for decap allocation in 3D power grids, using both conventional CMOS DECAPs and metal–insulator–metal (MIM) DECAPs. Unlike CMOS capacitors that are built in the device layer, MIM capacitors are fabricated between metal layers. These structures have high capacitance density and low leakage current density. Fig. 4.3 shows the positions of CMOS and MIM DECAPs in a 3D circuit. MIM DECAPs are usually fabricated between the top two

metal layers in each 2D tier. A significant advantage of MIM DECAPs lies in their extremely low leakage: in [4.9], the leakage current for the 250 nF MIM DECAPs is reported to be about 1.0 × 10−8 A (with leakage density of 3.2 × 10−8 A/cm2), while the leakage current for a 25 nF CMOS decap in parallel with MIM is approximately 3.2 × 10−6 A (with leakage density of 1.45 × 10−4 A/cm2).

However, MIM DECAPs cannot be used unconditionally to replace CMOS DECAPs, since their use incurs a cost: they present routing blockages to nets that attempt to cross them. In [4.9], the decap budgeting problem, using both CMOS and MIM DECAPs, is formulated as a linear programming (LP) problem, and an efficient congestion-aware algorithm is proposed to optimize the power supply noise while trying to find a balance between the routing congestion deterioration and leakage power increase.

Fig. 4.3 MIM and CMOS DECAPs in one 2D tier with three metal layers.

An iterative flow is used to solve the decap allocation problem. In each iteration a relatively small amount of decap is allocated to the current circuit for two reasons.

First, the decap allocation problem is highly nonlinear, and this iterative approach permits the optimization process to be controlled by solving a sequence of linear

programs, one in each iteration. In order to enable the formulation of these linear programs, it is necessary to model the noise violation and the congestion using models that are linear in the decap value. The second reason is related to this approximation:

it avoids the excessive allocation of DECAPs that could invalidate the approximate linear model of congestion and noise violation used in the algorithm; these models are predicated on the assumption of small perturbations.

Experimental results demonstrate that the use of CMOS DECAPs alone is insufficient to overcome the violations; the use of MIM DECAPs results in high levels of congestion; and the optimal mix of the two meets both congestion and noise constraints with low leakage.

4.2 On-Die Noise Suppression with Active Circuits

The traditional solution for reducing power supply noise is to use on-chip decoupling capacitors, along with on-package and on-board capacitors to supply instantaneous current demand. However, the large consumption of die area and gate leakage has limited the total amount of DECAPs that can be deployed on a chip for noise reduction. In this section, we will introduce the noise suppression mechanical with active circuits which is more efficiency to reduce to noise on power delivery network.

4.2.1 On-Die Noise Suppression by Improving Impedance of Power Grid

The lower the resistance, the lower the overshoots; however that comes with an increased power consumption trade-off. Adding a conventional resistor in parallel to the power grid network would increase the power consumption significantly. In reality, damping is only required in the frequency domain around the resonance frequency,

rather than at all frequencies as provided by a conventional resistor. An active resistor in parallel with the on-chip decoupling capacitors [4.10] for damping has been presented. And achieving 40% peak noise reduction for overshoots and 15% reduction for undershoot. However, the increased IR droop limits the usefulness of this technique.

Active DECAPs were previously used for the suppression of substrate crosstalk in mixed-signal ICs [4.11]. Fig. 4.3 shows the principle of our proposed active DECAP circuit that is targeted towards the suppression of supply noise due to finite on-chip and off-chip parasitic impedances in digital ICs. The proposed circuit consists of an operational amplifier (Opamp) and a passive load capacitor Cload. The feedback loop detects changes in the voltage VDD-Gnd and drives the load capacitance, effectively amplifying the capacitance seen at the VDD input to (1+A(ω))·Cload via the Miller effect, where A(ω) represents the gain of the opamp. In [4.12] and [4.13], the same idea but the new active DECAP circuit is proposed. The proposed circuit is designed suitable for digital implementation by using self-biasing schemes and has maximized its output swing to obtain sufficient noise regulation range. Simulations are performed to exam the DECAP boosting performance under various capacitive load conditions. Results show that the proposed circuit not only can boost the DECAP value by more than 10 but also exhibits significant advantage of suppressing the dominant resonant noise in an IC chip.

Fig. 4.4 Principle of proposed active DECAP circuit for supply noise suppression.

4.2.2 On-Die Noise Suppression by Providing Additional Current

Unlike the section 4.2.2, we introduce the supply noise suppression technology by proving additional current. In [4.14] and [4.15], an active circuit to detect and suppress excessive supply-voltage undershoots and overshoots caused by large current transients or by excitation of supply resonance. A nominal-voltage active supply, VDDA, is used to inject extra charge into the power grid during excessive undershoots. The use of a nominal-voltage VDDA eliminates the need for any high-voltage supplies and enables use of DECAPs and transistors with nominal oxide thickness, which is shown as Fig. 4.5. A similar circuit is proposed in [4.16], Fig. 4.6 shows the schematic of the noise suppression. When the logic circuit wakes up, the switch between VDDH and VDD is turned on by the level-shifter and the current from VDDH substitutes the current flowing through the bonding wire and the onboard supply lines of VDD. But this technical has a disadvantage that is trigger by the switching circuit rather than detecting the power supply noise.

Fig. 4.5 Power delivery model with active noise suppression.

Fig. 4.6 (a) Configuration of the noise suppression

Both the technical we mention above need an additional power supply, Jianping presents an on-die resonance suppression circuit technique that uses band-limited active damping to reduce resonance-induced voltage fluctuations [4.17]

and [4.18]. Fig. 4.7 shows an on-die resonance-suppression circuit (RSC) technique that uses band-limited active damping to reduce resonance-induced voltage fluctuations. The RSC consists of a supply noise amplifier with an integrated band-pass filter that lowers RSC sensitivity to out-of-band supply noise. The amplified supply noise in the pass band feeds a comparator that drives a current generator, which produces the damping current. When the load current has a large component at the resonant frequency, the supply voltage variation is 180°

phase-shifted compared to the load current as a rising load current induces a falling

supply voltage. The RSC monitors the supply voltage and generates an AC current in phase with the voltage fluctuations, or 180° out of phase with the in-band load current, effectively clamping the voltage overshoots.

Fig. 4.7 block diagram of RSC

4.2.3 On-Die Noise Suppression by switching DECAP

We mention the noise suppression technical by proving additional current in section 4.2.2. However, it is not a good idea to provide addition current to reduce the power supply noise in power efficiency view.

Fig. 4.8 Principle of resonant noise suppression using switched DECAPs The Fig. 4.8 shows the principle of using switched DECAPs to boost the amount of charge that is delivered by the conventional DECAPs. Two passive DECAPs are connected in parallel during normal condition and serve as conventional DECAPs.

When supply noises undershoot reaches a switching trigger threshold VSW, the

DECAPs are switched into a series connection where charge is dumped into the supply network. In the supply overshoot cycle, the capacitors are switched back into parallel and charge is restored to the capacitors from the supply network.

Fig. 4.9 illustrates the complete active DECAP design containing four blocks: a reference voltage generator, a pair of high-pass filters, two comparators, and the switched DECAPs in [4.19] and [4.20]. The user logic circuit block shown in the figure is considered to be the main cause of power supply noise violation. This active DECAP using latch-based comparators in 90 nm CMOS is able to switch in 0.5 ns and consumes a relatively low power of 2.8mW, which is about 5X lower than a previous design running at approximately the same speed. Even more, the author investigate these higher stack height configurations to assess the degree of improvement in supply noise reduction [4.21]. Extensive simulation results correlated with a test chip indicate that an active DECAP with a stack height of three provides the best noise reduction if the supply noise level is between 7%-14%, but a stack height of two is best if the noise level is between 14%-16%.

Fig. 4.9 Active DECAP architecture

On the contrary, Fig. 4.10 shows the schematic of the switched DECAP regulator with a digital resonant detection scheme which is proposed in [4.22]. The noise

detection is realized by comparing the delay of a constant delay line (CDL) and a variable delay line (VDL). The CDL forms a ring oscillator with a frequency of 2 GHz to continuously trigger the comparison. The supply of the CDL (Vdd’) is low-pass filtered so that the delay is insensitive to supply noise above 10 MHz which is the low cut-off frequency of our resonant regulation. The supply of VDL is directly connected to the noisy Vdd so its delay varies with supply fluctuations. Measurements

detection is realized by comparing the delay of a constant delay line (CDL) and a variable delay line (VDL). The CDL forms a ring oscillator with a frequency of 2 GHz to continuously trigger the comparison. The supply of the CDL (Vdd’) is low-pass filtered so that the delay is insensitive to supply noise above 10 MHz which is the low cut-off frequency of our resonant regulation. The supply of VDL is directly connected to the noisy Vdd so its delay varies with supply fluctuations. Measurements