TSV’s parameter and optimization

According to [3.7], increase the density of the TSV placement in the stacked ICs such that the power noise is reduced below an acceptable voltage drop tolerance.

Increasing the density of TSV reduces the voltage drop caused by the TSV failure. Fig.

3.6, demonstrates iterations among the dimensions of the TSV and the changes of the aspect ratio (height to cross section) of the TSV. Increasing the TSV cross section area will reduce the impedance of the PDN structures and as a result mitigate the power noise. However, increase in the dimension and density will reduce the routable area of the stacked dies. According to the Design Rule Check, there is a keep out area surrounding the TSV in the contact of the TSV and tier power grids where no signal or power could be routed and no hard macro could be placed.

Fig. 3.6 TSV design with TSV pitch and width scaling.

Selvanayagam et al. [3.8] performed comprehensive study on thermo-mechanical reliability of the TSV for different TSV dimensions. Their study shows the relation between the thermal strain and diameter of the TSV is derived. The increase in the TSV diameter will increase the thermo-mechanical strains and as a result the reliability is reduced. The thermal resistance of the stacked 3D PDN reduces with the increase in the TSV densities.

Fig. 3.7 Normalized TSV reliability factor.

The relative normalized TSV reliability factor for fixed number of operation cycles is derived in Fig. 3.7. Fig. 3.7 shows that as the TSV diameter increases, the relative reliability factor is reduced. The 3D PDN reliability is also increased with the increase in the density of the TSV in the stacking. In addition, from Fig. 3.6 it is

observed that we have the minimum power noise for the largest TSV diameters and highest density.

These conclude all observation in Fig. 3.8(a) which represents the cost function:

Failure rate × max voltage drop. There is a tradeoff between the reliability and the power noise reduction as the TSV diameters increases. Increases in the diameter will reduce the voltage noise but decrease the reliability factor which is demonstrated in Fig. 3.8 (a). Besides, Fig. 3.8 (b) concludes the TSV analysis framework. To obtain the minimum cost function (Failure rate × max voltage drop) with the minimum feasible TSV block out area, the author minimize the failure rate × maximum voltage drop × block out area . The minimum, in Fig. 3.8 (b), is the configuration where the 3D PDN has the least cost function (failure × noise) under local TSV failures and the block out region is minimized.

Fig. 3.8 (a)Maximum ΔV × Failure rate vs. TSV pitch and size (b) Max ΔV × Failure rate × Block out area.

However, various techniques can impact the quality of power delivery in 3D ICs.

These include through-silicon via (TSV) size and spacing, controlled collapse chip connection (C4) spacing, and a combination of dedicated and shared power delivery.

In [3.9], their evaluation system is composed of quad-core chip multiprocessor,

memory, and accelerator engine. Each of these modules is running representative SPEC benchmark traces. And they present a set of guidelines for designing and optimizing power delivery networks in future 3D designs:

z Locality in the vertical dimension impacts both IR drop and Ldi/dt voltage droop trends in a 3D PDN. A voltage droop at a node in 3D can get current from decoupling caps in the vertical neighbors as well as from the ones in the same plane. The resulting behavior is dependent on the locality of the droop as well as the state of the neighboring nodes. Therefore, a detail 3D PDN analysis with architecture or module level placement using representative workloads is necessary during 3D chip design.

z A critical observation in [3.9] is the saturation trend of IR drop in 3D PDNs with increased TSV size. This suggests the need for first finding the optimal TSV size given the on-chip grids in 3D stacked layers such that the least amount of silicon area penalty is incurred.

z While it is generally expected that the power delivery would be affected most in the die stacked furthest away from the C4 connections, the author report that percentage degradation in power delivery is in fact worse in lower level dies closer to C4s. This is particularly true when a highly active module, such as PROC, is placed next to heat sink for thermal concerns and furthest away from C4 connections. Therefore, 3D PDN analysis needs to carefully consider the impact in all the dies while optimizing the grid.

z Increasing the TSV granularity or equivalently decreasing the TSV spacing in 3D PDN improves the standard deviation in IR drop and Ldi/dt voltage droop most, with marginal improvements in maximum and average values. Therefore,

physical design for 3D PDN must consider this impact and choose TSV granularity accordingly.

z Despite selecting the optimal TSV size and TSV spacing, 3D PDN performs worse in both IR drop and Ldi/dt voltage droop compared to 2D PDN if the package connection, such as C4, pitch or granularity is maintained the same as in the 2D case. This study shows that improving off-chip component of the 3D PDN, for example through reducing C4 pitch for a higher number of C4s, has the highest relative impact on power grid metrics that enables 2D like or even better quality 3D PDN.

z A combination of shared and dedicated TSV power delivery can be used, as illustrated in 3D TAP configuration in Fig. 3.9 , to achieve improvements in both IR drop and Ldi/dt voltage droop.

Fig. 3.9 Tapered Stacked (TAP) 3D Configuration

3.4 Proposed Methodology of Power TSV Placement and