This thesis describes the design of CMOS frequency synthesizer for ultra wideband wireless PAN applications. Chapter 1 introduces the motivation and the specifications of frequency synthesizer for the UWB WPAN applications. Chapter 2 discusses the state of the art and the frequency planning in this work. Chapter 3 presents the spurious suppressing techniques in the proposed UWB frequency synthesizer. Chapter 4 presents the linear model of the phase-locked loop in order to decide the loop bandwidth, the phase margin, the phase noise, and the settling time in short time. The design and implementations of the frequency synthesizer are described in Chapter 5, including the
voltage-controlled oscillator, the frequency dividers, the phase frequency detector, the charge pump, the loop filter, and the single-sideband mixer. The layout, the testing setup, and measurement results of the voltage-controlled oscillator are also presented. The phase frequency detectors are also presented and the phase frequency detector with charge pumps in the package version. Chapter 6 gives the conclusions and the future works.
Chapter 2 Frequency Planning
There are many kinds of methods to synthesize frequencies. Such as direct synthesizers, indirect synthesizers (phase-locked loop frequency synthesizers), and direct digital frequency synthesizers. Because the phase-locked loop frequency synthesizer is easy to synthesize high frequencies and consumes low power, it is the most popular method used in high frequency synthesizers. In order to easily integrate in low-cost CMOS process and operate at high frequencies, we choose phase-locked loop synthesizer. There are many kinds of PLL frequency synthesizers changing division to synthesize various frequencies, such as integer-N, and fractional-N frequency synthesizers. However the time to switch between different band frequencies within a band group should be less than 9.47ns. The fast switching time precludes the use of a standard phase-locked loop (PLL)-based frequency synthesizer. Some possible ways of the performing the frequency generation in a UWB device are discussed in this section.
2.1 Architecture of UWB Frequency Synthesizer
In the UWB system, the frequency range is from 3.1-GHz to 10.6-GHz, and the carrier switching time must below 9.47ns. The specifications of the switching time and the spurs are difficult to meet. The frequency hopping time can not be satisfied with conventional PLL-based frequency synthesizers because the locking time of the phase-locked loop is several hundreds ns or severalμs. In order to fast switch between bands, one approach incorporates some phase-locked loops and some single sideband mixers to synthesize different frequencies that present all time. The other approach incorporates multiple PLLs to generate different frequencies presented all times. The frequency range of the UWB system is very large, and the range covers the wireless LAN standard such as 802.11a. The reciprocal mixing effect can occur easily and degrade the wanted signal. In order to coexistent with other bands in 3-GHz~8-GHz, the suppression of the spurious must be concentrated. There are several kinds of UWB frequency synthesizer architectures and will be introduced in the following section.
2.1.1 State of the art 1 [3]
In [3], the UWB synthesizer shown in Figure 2.1 is designed to operate in “mode 1” bands. The frequency bands of mode 1 are 3432 MHz, 3960 MHz, and 4488 MHz.
The three frequencies are produced by three fixed-modulus phase-locked loops,
therefore avoiding SSB mixers. The SSB mixer must have a low harmonic distortion, and the phase and gain mismatch can introduce spurious at the output of the SSB mixer.
The output is changed between three voltage-controlled oscillators by the selector;
therefore it may be sensitive to inductor coupling and carrier leakage. The architecture needs a good layout to provide good isolation. When the numbers of bands increases, the architecture will require more phase-locked loops, and it will increase the production cost and consume more power.
PLL1
PLL2
PLL3
Selector
3432MHz/3960MHz/4488MHz
3432MHz
3960MHz
4488MHz
Figure 2.1 One band with one PLL frequency synthesizer
2.1.2 State of the art 2 [2]
In [2], there are two phase-locked loops in the architecture as shown in Figure 2.3.
In the UWB center frequencies, some high band frequencies are twice as larger as the low band frequencies. The 6864-MHz, 7392-MHz, and 7920-MHz frequencies are generated by a VCO in the PLL, and the 3432-MHz, 3960-MHz, and 4488-MHz
frequencies can be generated by divde-by-2 circuits. Therefore they can share the same phase-locked loop. For example, In Figure 2.2, when the frequency synthesizer is turned on, PLL1 provides the frequency to the present band (3960-MHz), and PLL2 is switched to the next band (3432-MHz). They operate by turns. Because the symbol period is 312.5ns, the settling time of the PLL standby must be less than 312.5ns. This means the architecture needs a wide loop bandwidth to achieve fast settling time, and the reference spurious problem will be critical. The charge pump circuit must be designed carefully because it is critical to minimize the reference spurious.
PLL1
PLL2
PLL1
PLL2 4488
3960
3432 Frequency
(MHz)
312.5ns
9.5ns
Time PLL2
Stand by
PLL1 Stand by
PLL2 Stand by
PLL1 Stand by
Figure 2.2 Frequency switching for each symbol of a MB-OFDM UWB burst
Figure 2.3 Two phase-locked loops frequency synthesizer
2.1.3 State of the art 3 [4]
An approach to synthesize all bands needed by single-sideband mixers and phase-locked loops is introduced in the following sections.
In [4], the architecture in Figure 2.4 uses two phase-locked loops to generate 3960-MHz and 528-MHz frequencies, then the single-sideband mixer spans the frequencies in band group one. Because the SSB mixer needs quadrature inputs, the quadrature signals are provided by the frequency divider circuit in the PLL. For example, in PLL1, it needs to provide quadrature signals at 3960MHz. Therefore the voltage-controlled oscillator needs to oscillate at 7920MHz, and the following divide-by-2 circuit (current mode logic architecture) can provide quadrature outputs at 3960MHz easily. The disadvantage is the spurs problem at the SSB mixer output.
SSB Mixer
3432MHz/
3960MHz/
4488MHz
Selector
I Q
I Q 3960MHz
+528MHz/
-528MHz/
0 528MHz
Figure 2.4 Two phase-locked loops and one SSB mixer frequency synthesizer
2.1.4 State of the art 4 [5]
In [5], two PLLs are used again, but in a different way to generate seven bands from 3-GHz to 8-GHz. In Figure 2.5, one phase-locked loop provides two frequencies for input signals of the output SSB mixer. And the programmable tri-mode divider placed in front of the SSB mixer has a DC, and quadrature signalswith opposite I/Q sequences, therefore can provide more input signals for the SSB mixer. The SSB mixer has more selections of the input path. Therefore the frequences which the SSB mixer can synthesize will be more than the architecture in Figure 2.5. In order to suppress the spurious, the SSB mixer incorporates LC loads. The LC load acts as a band pass filter, and band switching is accomplished by using capacitor arrays to change the resonance frequency of the LC tank.
Figure 2.5 New two phase-locked loops and one SSB mixer frequency synthesizer
2.1.5 State of the art 5 [6]
In this year, a frequency synthesizer that generates twelve bands form 3.1-GHz to 9.5-GHz was presented. The frequency synthesizer consist SSB mixers and only one PLL. All the LO frequencies required for 3.1-GHz to 9.5-GHz operation are generated from the 8.448-GHz QVCO which consumes low power. A harmonic suppressing filter is inserted at the SSB1 mixer output terminal. The cut-off frequency of the filter is programmed according to the changing bands.
There are many kinds of architectures to implement the UWB frequency synthesizer. If the synthesizer architecture does not employ mixers, it required multiple PLLs, and therefore area and power consumption will be increased. The spurious problem is not serious because there is no mixer in the architecture. When the architecture applied to more bands, the carrier leakage problem will be more serious. If the synthesizer architecture consists of mixers, it required less PLLs, the area and power consumption are saved but more spurious will be introduced. The trade off must be made carefully to achieve fast switching time while not to increase area or power and to keep spurious minimized. In Table 2.1, the architecture consisting of mixers can synthesize more band frequencies and consume less power, but the spurious is higher than architecture without using mixers.
2005
2.2 Frequency Planning
In order to synthesize all band group of the UWB system, there are more intermediate frequency components generated, and more SSB mixers are required.
Therefore, the unwanted sidebands are accumulated through multi-stage mixing. The output signal will be degraded because of the multi-stage mixing. So the synthesizer must have approaches to suppress spurious signal. For example, the SSB mixer incorporates band-pass loads to suppress sidebands and spurious sinals.
Because the switching time is 9.47ns, and in order to design a UWB frequency synthesizer which can synthesize all band group frequencies, SSB mixers should be used or it will be difficult to synthesize all band group frequencies with less PLLs.
Using multiple PLLs will consume much power and die area. And the LO leakage problem will be worse. So the architecture consisting of SSB mixers is used. In order to reduce the number of phase-locked loops and have a lot of auxiliary frequencies provided for SSB mixers, the frequency of the voltage-controlled oscillator must be chosen carefully. Some possible approaches of the frequency generation in a UWB are discussed in [7]. To generate all band groups, there will be a lot of intermediate frequencies provided for SSB mixers. The intermediate frequencies can be provided by the dividers in the phase-locked loop or the mixers. Using the divider is better because quadrature outputs are easily obtained and no need for power and area wasting mixer
components. In order to have maximum possible intermediate frequencies from a fixed VCO frequency, the division ratio should be with small size such as 2 and 3.
528-MHz is the baseband clock signal in MB-OFDM UWB system. In Figure 2.7, the frequency tree shows the different possible VCO frequencies that can generate a 528-MHz tone by successive division by 2, 3, or both. The SSB mixer requires quadrature signal inputs, and the quadrature signals can be generated by the passive RC polyphase filters or current mode logics. It is not practical by using polyphase filters, because multiple ployphase filters are required to cover all band groups and cost a lot of area. Aside from the problem, at high frequencies, the parasitic capacitances of the resistor are likely to make unacceptable errors in quadrature. In order to generate quadrature frequencies, the reliable way is by restricting all frequency division in the frequency synthesizer to current mode logic which can produce balanced quadrature outputs.
To sum up, in order to have more balanced quadrature intermediate frequencies by the phase-locked loop, choosing the VCO frequency as 8448-MHz and following the path enclosed by the dotted line (in Figure 2.7) is used in the proposed synthesizer design.
Figure 2.7 A frequency tree
The integer-N architecture is chosen in our phase-locked loop. Since the output signals of the frequency dividers are provided for SSB mixers, so they must be a fixed frequency values. The PLL can generate 8448-MHz and 4224-MHz frequencies. From
[1], 8448-MHz and 4224-MHz are upper frequencies of the 3960-MHz and 8184-MHz
channels. Now regard these two as the major frequencies and separate the UWB center frequencies into two parts as shown in Figure.2.8. One part is close to 4224-MHz and the other is close to 8448-MHz. In order to synthesize all band group frequencies, the offset frequencies such as 264, 792, 1320, and 1848-MHz are required.
8448MHz 4224MHz
3432MHz
3960MHz
4488MHz
5016MHz
5544MHz
6072MHz
7128MHz
7656MHz
8184MHz
8712MHz
9240MHz
9768MHz 6600MHz
10296MHz 264MHz
792MHz 1320MHz 1848MHz Offset frequency
Major frequency Major frequency
Figure 2.8 Two parts of the UWB frequency bands
Instead of direct mixing these frequencies, a divide-by-two circuit is inserted after the mixer because the division helps to suppress spurious signals [9]. In order to insert a divide-by-two circuit after the mixer, the offset frequencies must be doubled. Therefore 528, 1584, 2640, and 3696 MHz at the mixer output are required and 528 MHz is already generated in the PLL. Now the intermediate frequencies in the PLL are used to generate the doubled offset frequencies. The mixer output frequency 1584 MHz is generated by down-converting 2112 MHz with 528 MHz. (Note: both 2112 MHz and 528 MHz are generated in the PLL). In the similar way, 2640 and 3696 MHz can be acquired by up-converting 2112 MHz with 528 MHz and by down-converting 4224
MHz with 528 MHz respectively. In Fig. 3, the PLL can generate frequencies of 8448, 4224, 2112, 528, and 264 MHz. The SSB1 mixer output frequency is 1584, 2640, or 3696 MHz, and the offset frequencies can be acquired after the divider following the SSB1 mixer. Hence, the SSB2 mixer and the SSB3 mixer can generate all band group frequencies for UWB systems by the major frequencies (8448 and 4224 MHz) and the offset frequencies (264, 792, 1320, and 1848 MHz).
Figure 2.9 Architecture of this work
Chapter 3 Spurious Suppressing Techniques
Frequency spurious of the LO signal can down-convert in-band signals to the same frequency as the wanted band. To meet the specification on low LO spurs is much more difficult than the specification on low phase noise in the UWB system. Therefore to decrease the spurious in the UWB system is very important. This chapter will introduce some spurious suppressing techniques in this work.
3.1 Using Divide-By-2 Circuit After the Mixer
Literature
[9], presented that the spurs after division-by-2 is lower than spurs
before division-by-2. In Figure 3.1, consider two tones at ω1 and ω2 applied to the divide-by-2 circuit. ω1 is the wanted signal and ω2 is the unwanted spurious whose amplitude is A. The spurious tone ω2= ω1+Δω can be decomposed into equal amplitude modulation (AM) and phase modulated (PM) sidebands by linearsuperposition. Each of them is the same amplitude A/2, and they locate symmetrically Δω away from ω1.
The flip-flop (the divide-by-2 circuit) is sensitive only to the threshold crossing of the input signals. (Note: Assume the differential threshold is zero) Therefore, the flip
flop only reacts to the input PM signals.
In Figure 3.2, the input PM signal is applied to the flip-flop. Whenever the differential clock input across zero, the flip-flop output toggles. The appearance is clear in the time-domain input and output waveforms. The output waveform tracks the input waveform whenever the input signal is at positive-slop trigger. The deviation is also tracked by the flip flop. However, the output frequency is half of the input frequency;
the deviation in phase at output is half corresponding to the input signal. Therefore, the PM sidebands at output are half of the input PM sidebands at input. So the amplitude of the output PM sidebands are 0.25A. However, the rate or relative frequency of PM is still the same as before. Therefore, the sidebands are located at
ω ± Δ ω
2
1 .
To sum up, when large interesting input tones and small unwanted input spurs are applied to the to the divede-by-2 circuit, the large interesting input tones are divided by two, and each of the small unwanted input spurs is surrounded by two output spurs that are symmetrically disposed around the large tone at the same frequency offset as the single input spur but at 1/4 (-12 dB) the input spur’s relation amplitude. (In Figure 3.3) More frequency division-by-2 conserves the spur separation but lowers the relative levels by 6 dB.
In an SSB mixer followed by frequency division, gain mismatch and phase errors in the I and Q mixers will generate a small unwanted spurs. This is the input of the
divider From above discussing, the divide-by-two circuit can help to suppress spurious.
+Δω
ω
1ω
1ω
21
A
Δ
ω
ω
1ω
2 0.5A 2ω1-ω2-Δω
0.5A 0.5A
ω
1-Δω
+Δω
0.5A
0.5A 1
Δ
ω
0.5A Δ
ω
A
linear superposition
Figure 3.1 Decomposing a spur into equivalent AM and PM sidebands
Figure 3.2 Output waveforms of a divide-by-2 circuit when PM signal is input
Figure 3.3 Output spectrum of divide-by-2 circuit
Figure 3.4, 3.5, and 3.6 respectively show the output spectrums of the 792-MHz, 1320-MHz, and 1848-MHz generated with and without the divide-by-two circuit. The dot line presents the output without divide-by-two circuit, and the solid line is for that with dive-by-two circuit.
Since the input frequencies of the mixer with and without divide-by-2 are different, the spurs at output are not at the same offset frequency away from carrier frequencies.
But the spurious near the synthesized frequency with divide-by-two circuit is lower than that without divide-by-two circuit.
Figure 3.4 Frequency spectrums of 794-MHz
Figure 3.5 Frequency spectrums of 1320-MHz
Figure 3.6 Frequency spectrums of 1848-MHz
3.2 Single-Sideband Mixer
Single-sideband mixers are employed in the proposed synthesizer. As shown in Figure 3.7, the relation between the output and the input of the mixer is in the following equation.
t t
t t
t
Out = cos( ω
1) cos( ω
2) ± sin( ω
1) sin( ω
2) = cos( ω
1m ω
2)
(3.1) Therefore, the architecture can make the unwanted sideband lower. But SSB mixers require quadrature inputs and arise two issues which are the mismatches between the quadrature inputs and the nonlinearities. A general way to quantifying the I/Q mismatch in a SSB mixer is to concern two signals V0sinω
1t and V
0cosω
1t to the I
and Q inputs and check the spectrum produced by the adder. In the ideal case, the SSB mixer output is shown as equation 3.2. In equation 3.3, ε is a gain mismatch, and θ isphase imbalance.
t V
t t
V t t
V
Out
= 0cos(ω
1 )cos(ω
2 )+ 0sin(ω
1 )sin(ω
2 )= 0cos(ω
2 −ω
1) (3.2))
In practice, the cross-talk between the two data streams becomes negligible if the above test yields an unwanted sideband about 30dB below the wanted signal.
The mixers are usually designed such that the switching port experiences rapid switching. The switching port is so nonlinear that the RF signal is multiplied by a
rectangular waveform. Therefore, in Figure 3.7, harmonics of ω
1
and ω2
are generated in each port of the mixers, leading to various cross-products after multiplication. The problem will be mitigated by using LC tank. We will introduce in the next section.Figure 3.7 Ideal SSB mixing
3.3 LC Tank with Switching Inductor
The SSB mixer in Figure3.8 incorporates band pass loads to suppress spurious [5].
The SSB mixer with inductor loads are used to achieve broadband operation. Band selection is accomplished by adding capacitor arrays to adjust the resonances frequency of the tanks. The wide range operation (3-8GHz) of [5] uses multiple LC tanks. In order to extend the frequency range of the SSB mixer, more LC tanks are required leading more area expansion. However, with some modification on the LC tank, the area can be kept while the operation bandwidth can be improved.
Figure 3.8 A SSB mixer with band pass loads
Changing the resonant frequency of the LC tanks is discussed in [10]. The maximum Q attainable is dominated by the on-chip inductor Q in low-cost CMOS process. Therefore, a restricted bandwidth is obtained at high frequency, and that is not enough for wideband applications. An easy way to raise the bandwidth is to decrease the
For LC tanks, the center frequency can be tuned either by inductors or capacitors. The most commonly used approach is to vary the parallel capacitors either by varactors or switched-capacitor arrays. However, since the tank impedance would be degraded with the increased capacitance, the tank impedance is lower at lower frequencies as compared to that at higher frequencies. As a result, either the output swing or the power consumption would need to be compromised.
As a better choice to varying the parallel capacitors, the tank inductance can be varied by employing MOS with the center taped inductors. As shown in Figure 3.9, there is a PMOS switch on the center of the inductor. When the voltage Vc is VDD, the PMOS switch is open, and the effective inductance is L. On the other side, when the
As a better choice to varying the parallel capacitors, the tank inductance can be varied by employing MOS with the center taped inductors. As shown in Figure 3.9, there is a PMOS switch on the center of the inductor. When the voltage Vc is VDD, the PMOS switch is open, and the effective inductance is L. On the other side, when the