Frequency Planning

In order to synthesize all band group of the UWB system, there are more intermediate frequency components generated, and more SSB mixers are required.

Therefore, the unwanted sidebands are accumulated through multi-stage mixing. The output signal will be degraded because of the multi-stage mixing. So the synthesizer must have approaches to suppress spurious signal. For example, the SSB mixer incorporates band-pass loads to suppress sidebands and spurious sinals.

Because the switching time is 9.47ns, and in order to design a UWB frequency synthesizer which can synthesize all band group frequencies, SSB mixers should be used or it will be difficult to synthesize all band group frequencies with less PLLs.

Using multiple PLLs will consume much power and die area. And the LO leakage problem will be worse. So the architecture consisting of SSB mixers is used. In order to reduce the number of phase-locked loops and have a lot of auxiliary frequencies provided for SSB mixers, the frequency of the voltage-controlled oscillator must be chosen carefully. Some possible approaches of the frequency generation in a UWB are discussed in [7]. To generate all band groups, there will be a lot of intermediate frequencies provided for SSB mixers. The intermediate frequencies can be provided by the dividers in the phase-locked loop or the mixers. Using the divider is better because quadrature outputs are easily obtained and no need for power and area wasting mixer

components. In order to have maximum possible intermediate frequencies from a fixed VCO frequency, the division ratio should be with small size such as 2 and 3.

528-MHz is the baseband clock signal in MB-OFDM UWB system. In Figure 2.7, the frequency tree shows the different possible VCO frequencies that can generate a 528-MHz tone by successive division by 2, 3, or both. The SSB mixer requires quadrature signal inputs, and the quadrature signals can be generated by the passive RC polyphase filters or current mode logics. It is not practical by using polyphase filters, because multiple ployphase filters are required to cover all band groups and cost a lot of area. Aside from the problem, at high frequencies, the parasitic capacitances of the resistor are likely to make unacceptable errors in quadrature. In order to generate quadrature frequencies, the reliable way is by restricting all frequency division in the frequency synthesizer to current mode logic which can produce balanced quadrature outputs.

To sum up, in order to have more balanced quadrature intermediate frequencies by the phase-locked loop, choosing the VCO frequency as 8448-MHz and following the path enclosed by the dotted line (in Figure 2.7) is used in the proposed synthesizer design.

Figure 2.7 A frequency tree

The integer-N architecture is chosen in our phase-locked loop. Since the output signals of the frequency dividers are provided for SSB mixers, so they must be a fixed frequency values. The PLL can generate 8448-MHz and 4224-MHz frequencies. From

[1], 8448-MHz and 4224-MHz are upper frequencies of the 3960-MHz and 8184-MHz

channels. Now regard these two as the major frequencies and separate the UWB center frequencies into two parts as shown in Figure.2.8. One part is close to 4224-MHz and the other is close to 8448-MHz. In order to synthesize all band group frequencies, the offset frequencies such as 264, 792, 1320, and 1848-MHz are required.

8448MHz 4224MHz

3432MHz

3960MHz

4488MHz

5016MHz

5544MHz

6072MHz

7128MHz

7656MHz

8184MHz

8712MHz

9240MHz

9768MHz 6600MHz

10296MHz 264MHz

792MHz 1320MHz 1848MHz Offset frequency

Major frequency Major frequency

Figure 2.8 Two parts of the UWB frequency bands

Instead of direct mixing these frequencies, a divide-by-two circuit is inserted after the mixer because the division helps to suppress spurious signals [9]. In order to insert a divide-by-two circuit after the mixer, the offset frequencies must be doubled. Therefore 528, 1584, 2640, and 3696 MHz at the mixer output are required and 528 MHz is already generated in the PLL. Now the intermediate frequencies in the PLL are used to generate the doubled offset frequencies. The mixer output frequency 1584 MHz is generated by down-converting 2112 MHz with 528 MHz. (Note: both 2112 MHz and 528 MHz are generated in the PLL). In the similar way, 2640 and 3696 MHz can be acquired by up-converting 2112 MHz with 528 MHz and by down-converting 4224

MHz with 528 MHz respectively. In Fig. 3, the PLL can generate frequencies of 8448, 4224, 2112, 528, and 264 MHz. The SSB1 mixer output frequency is 1584, 2640, or 3696 MHz, and the offset frequencies can be acquired after the divider following the SSB1 mixer. Hence, the SSB2 mixer and the SSB3 mixer can generate all band group frequencies for UWB systems by the major frequencies (8448 and 4224 MHz) and the offset frequencies (264, 792, 1320, and 1848 MHz).

Figure 2.9 Architecture of this work

Chapter 3 Spurious Suppressing Techniques

Frequency spurious of the LO signal can down-convert in-band signals to the same frequency as the wanted band. To meet the specification on low LO spurs is much more difficult than the specification on low phase noise in the UWB system. Therefore to decrease the spurious in the UWB system is very important. This chapter will introduce some spurious suppressing techniques in this work.

3.1 Using Divide-By-2 Circuit After the Mixer

Literature

[9], presented that the spurs after division-by-2 is lower than spurs

before division-by-2. In Figure 3.1, consider two tones at ω1 and ω2 applied to the divide-by-2 circuit. ω1 is the wanted signal and ω2 is the unwanted spurious whose amplitude is A. The spurious tone ω2= ω1+Δω can be decomposed into equal amplitude modulation (AM) and phase modulated (PM) sidebands by linear

superposition. Each of them is the same amplitude A/2, and they locate symmetrically Δω away from ω1.

The flip-flop (the divide-by-2 circuit) is sensitive only to the threshold crossing of the input signals. (Note: Assume the differential threshold is zero) Therefore, the flip

flop only reacts to the input PM signals.

In Figure 3.2, the input PM signal is applied to the flip-flop. Whenever the differential clock input across zero, the flip-flop output toggles. The appearance is clear in the time-domain input and output waveforms. The output waveform tracks the input waveform whenever the input signal is at positive-slop trigger. The deviation is also tracked by the flip flop. However, the output frequency is half of the input frequency;

the deviation in phase at output is half corresponding to the input signal. Therefore, the PM sidebands at output are half of the input PM sidebands at input. So the amplitude of the output PM sidebands are 0.25A. However, the rate or relative frequency of PM is still the same as before. Therefore, the sidebands are located at

ω _{± Δ} ω

2

1 .

To sum up, when large interesting input tones and small unwanted input spurs are applied to the to the divede-by-2 circuit, the large interesting input tones are divided by two, and each of the small unwanted input spurs is surrounded by two output spurs that are symmetrically disposed around the large tone at the same frequency offset as the single input spur but at 1/4 (-12 dB) the input spur’s relation amplitude. (In Figure 3.3) More frequency division-by-2 conserves the spur separation but lowers the relative levels by 6 dB.

In an SSB mixer followed by frequency division, gain mismatch and phase errors in the I and Q mixers will generate a small unwanted spurs. This is the input of the

divider From above discussing, the divide-by-two circuit can help to suppress spurious.

+Δω

ω

¹

ω

¹

ω

²

1

A

Δ

ω

ω

1

ω

2 0.5A 2ω1-ω2

-Δω

0.5A 0.5A

ω

¹

-Δω

+Δω

0.5A

0.5A 1

Δ

ω

0.5A Δ

ω

A

linear superposition

Figure 3.1 Decomposing a spur into equivalent AM and PM sidebands

Figure 3.2 Output waveforms of a divide-by-2 circuit when PM signal is input

Figure 3.3 Output spectrum of divide-by-2 circuit

Figure 3.4, 3.5, and 3.6 respectively show the output spectrums of the 792-MHz, 1320-MHz, and 1848-MHz generated with and without the divide-by-two circuit. The dot line presents the output without divide-by-two circuit, and the solid line is for that with dive-by-two circuit.

Since the input frequencies of the mixer with and without divide-by-2 are different, the spurs at output are not at the same offset frequency away from carrier frequencies.

But the spurious near the synthesized frequency with divide-by-two circuit is lower than that without divide-by-two circuit.

Figure 3.4 Frequency spectrums of 794-MHz

Figure 3.5 Frequency spectrums of 1320-MHz

Figure 3.6 Frequency spectrums of 1848-MHz

3.2 Single-Sideband Mixer

Single-sideband mixers are employed in the proposed synthesizer. As shown in Figure 3.7, the relation between the output and the input of the mixer is in the following equation.

t t

t t

t

Out = cos( ω

₁

) cos( ω

₂

) ± sin( ω

₁

) sin( ω

₂

) = cos( ω

₁

_m ω

₂

)

(3.1) Therefore, the architecture can make the unwanted sideband lower. But SSB mixers require quadrature inputs and arise two issues which are the mismatches between the quadrature inputs and the nonlinearities. A general way to quantifying the I/Q mismatch in a SSB mixer is to concern two signals V0sin

ω

1

t and V

0cos

ω

1

t to the I

and Q inputs and check the spectrum produced by the adder. In the ideal case, the SSB mixer output is shown as equation 3.2. In equation 3.3, ε is a gain mismatch, and θ is

phase imbalance.

t V

t t

V t t

V

Out

= ₀cos(

ω

₁ )cos(

ω

₂ )+ ₀sin(

ω

₁ )sin(

ω

₂ )= ₀cos(

ω

₂ −

ω

₁) (3.2)

)

In practice, the cross-talk between the two data streams becomes negligible if the above test yields an unwanted sideband about 30dB below the wanted signal.

The mixers are usually designed such that the switching port experiences rapid switching. The switching port is so nonlinear that the RF signal is multiplied by a

rectangular waveform. Therefore, in Figure 3.7, harmonics of ω

₁

and ω

₂

are generated in each port of the mixers, leading to various cross-products after multiplication. The problem will be mitigated by using LC tank. We will introduce in the next section.

Figure 3.7 Ideal SSB mixing

3.3 LC Tank with Switching Inductor

The SSB mixer in Figure3.8 incorporates band pass loads to suppress spurious [5].

The SSB mixer with inductor loads are used to achieve broadband operation. Band selection is accomplished by adding capacitor arrays to adjust the resonances frequency of the tanks. The wide range operation (3-8GHz) of [5] uses multiple LC tanks. In order to extend the frequency range of the SSB mixer, more LC tanks are required leading more area expansion. However, with some modification on the LC tank, the area can be kept while the operation bandwidth can be improved.

Figure 3.8 A SSB mixer with band pass loads

Changing the resonant frequency of the LC tanks is discussed in [10]. The maximum Q attainable is dominated by the on-chip inductor Q in low-cost CMOS process. Therefore, a restricted bandwidth is obtained at high frequency, and that is not enough for wideband applications. An easy way to raise the bandwidth is to decrease the

For LC tanks, the center frequency can be tuned either by inductors or capacitors. The most commonly used approach is to vary the parallel capacitors either by varactors or switched-capacitor arrays. However, since the tank impedance would be degraded with the increased capacitance, the tank impedance is lower at lower frequencies as compared to that at higher frequencies. As a result, either the output swing or the power consumption would need to be compromised.

As a better choice to varying the parallel capacitors, the tank inductance can be varied by employing MOS with the center taped inductors. As shown in Figure 3.9, there is a PMOS switch on the center of the inductor. When the voltage Vc is VDD, the PMOS switch is open, and the effective inductance is L. On the other side, when the voltage Vc is GND, the PMOS switch is turned on, and the effective inductance is about L/2.

Figure 3.9 A switching inductor

We can use switching inductors to change the resonance frequencies of the LC tanks. In this way, we can avoid using large capacitance, and acquire higher impedance

and wider operation bandwidth.

Figure 3.10 shows the impedance of the LC tank with 5-bit capacitor arrays, while Figure 3.11 is the impedance of the LC tank with 3-bit capacitor arrays and 1-bit switching inductor. It is apparent that using switching inductor can operate wider frequency range and have higher and flat impedance.

Figure 3.10 LC tanks with 5-bit capacitor arrays

Figure 3.11 LC tanks with 3-bit capacitor arrays and 1-bit switching inductor

3.4 LC Tank with Negative resistance

To have a band-pass load which can operate all band groups in the UWB system requires a lot of capacitance arrays to change the resonance frequency More capacitance also means more parasitic resistances which degrade the quality factor of the LC tank. In order to have a high quality factor, a negative resistance is put in parallel in the LC tank. The architecture is shown in Figure 3.12. The negative resistance can compensate the parasitic resistance and increase the quality factor.

VT2 VT1 VT0 VT0 VT1 VT2

-R

Figure 3.12 LC tanks with a negative resistance

Figure 3.13 and 3.14 show the impedance of the LC tank without and with negative resistance respectively. With the negative resistance, the resonant impedance is much higher.

Figure 3.13 LC tanks without negative resistance

Figure 3.14 LC tanks with negative resistance

Figure 3.15, 3.16 show the output spectrums respectively when the frequency band is at 4488-MHz, 8712-MHz.

The circle solid line is the output spectrum of the last stage mixer. (SSB1 or SSB2 mixer in Figure 2.9) The star solid line and the solid line are the output spectrums of the LC buffer without and with negative resistance respectively. In Figure 3.15, spurious is suppressed 6.697dB more with using negative resistance than without using negative resistance, when the frequency band is at 4488-MHz. Similarly, when the frequency band is at 8712-MHz, it improves 7.152dB.

Figure 3.15 Output spectrums at 4488-MHz

Figure 3.16 Output spectrums at 8712-MHz

Chapter 4 Frequency Synthesizer Design

4.1 Modeling of the PLL

Figure 4.1 is a linear model of a phase-locked loop. The model can help to evaluate the performance of the PLL, such as phase noise, loop stability, and settling time.

Figure 4.1 Linear model of a generic PLL.

The phase detector can generate a dc value proportional to the phase difference between the input reference signal θREF and the divided signal θDIV.. KPD is the phase detector gain in V/rad. The phase detector can be modeled as a substrator. Therefore, the output signal of the phase detector can be expressed by the following equation.

) ( _{REF DIV}

PD

PD

K

V

=

θ

−

θ

(4.1) Although the phase detector gain KPD is nonlinear, the transfer characteristic of the phase detector can be regarded as linear in its operating region. The phase error signal

V

PD is filtered by the low pass loop filter. which is expressed by Z(s). For example, a

( ) The capacitance Cⁱ contributes a pole at origin, τZ is a zero for stability concern, and τP is a pole for high-frequency spurs filtering.

The output frequency of the VCO is controlled by the voltage VCONT. The relation between the changing frequency of the VCO and the control voltage is Δω=KVCO·VCONT.

K

VCO is the VCO gain (specified in rad/s/V) and it is nonlinear. Since frequency is derivative of phase, the VCO can be modeled by the following equation.

s

Because frequency and phase are related by a linear operator, the division of frequency by a factor N is the same to the division of phase by the same factor. Hence, the frequency divider can be modeled by the following equation.

N

OUT DIV

θ = θ

(4.4)

Based on the linear model of the PLL, the open loop transfer function can be expressed as follows:

( ) 1

This transfer function can estimate the performance of the PLL.

4.1.1 Loop Stability

In Figure 4.1, because the phased-locked loop in this work employs the charge-pump circuit, the phase detector gain is determined by the charge pump output

current (KPD=ICP/2π).

The second order passive loop filter shown in Figure 4.2 consists of a capacitor CZ

for zero phase error, a resistor RZ for stability consideration, and a capacitor CP for high-frequency spurs filtering.

Figure 4.2 A second order passive loop filter.

The impedance of the second order passive loop filter is expressed as

)

The time constants determine the pole and zero frequencies of the loop filter. The open loop transfer function of the system can be expressed as the following equation.

( ) The phase margin is then given by the following equation.

) The Bode plot of the open loop response is shown in Figure 4.3 where the loop bandwidth, ωu, is defined as the corresponding frequency when the magnitude of the open loop gain equals one (i.e., unity-gain frequency). The phase margin is chosen between 50^o and 70^o.

Figure 4.3 Open loop response bode plot.

By setting the derivative of the phase margin equal to zero, the frequency with the maximum phase margin is found, and it is expressed in terms of zero and pole as

equation (4.14) Consider that the maximum phase margin occurs at the unity-gain frequency,

PD VCO p z

The time constants, τZ and τP are expressed in terms of phase margin and loop bandwidth as follows

p The component values of the second order filter are

2

Table 4.1 summarizes the loop parameters of the phase-locked loop The VCO gain is 280 MHz/V. The charge pump current is about 210 μA. In this work, the loop bandwidth and the phase margin are chosen to be 300-kHz and 60 ^o respectively. The values of the loop filter components are RZ = 8.84 kΩ, CZ = 224 pF, and CP = 17.32 pF.

The KVCO of the VCO is from 180MHz/V to 450MHz/V. When Kvco is 180MHz/V, 300MHz/V, and 450MHz/V, the phase margins are 50 degrees, 60 degrees, 40 degrees.

All of the phase margins are lower than 40 degrees.

Parameters Value

Loop Bandwidth ωu 300-kHz Phase Margin φP 60^o

VCO Gain KVCO 280 MHz/V

Charge Pump Current ICP 210 μA

R

Z 8.84 kΩ

C

Z 224 pF

C

P 17.32 pF

Table 4.1 Summary of loop parameters.

4.1.2 Noise Characteristic of the PLL

In the PLL, there are two main noise sources which are from VCO and reference signals. The transfer function of the noise source from the VCO output is a high-pass characteristic. In the same way, the transfer function of the noise source from the reference clock input is a low-pass characteristic. That one or both noise sources are significant depends on the application of the phase-locked loop. Therefore, the optimum choice of the loop bandwidth in the PLL is important. In the wireless frequency synthesizer, due to the high quality of the crystal-based reference signal, the VCO phase noise dominates the noise. Therefore, it is desirable to make the loop bandwidth wider

Since the input reference of the phase-locked loop is crystal-based, phase noise contributions from the reference and frequency dividers are very low and negligible.

Consider the phase noise contribution from the VCO, charge pump, and loop filter. The transfer function from noise sources to the output can be obtained by the linear PLL model. To derive the transfer function, the linear model of the PLL is shown in Figure 4.4.

Figure 4.4 Linear model of the PLL with noise source

The transfer function from the input phase θin to the output phase θout can be expressed as the following equation, and is a low-pass function.

(4.22)

Therefore, the phase noise of the reference is attenuated at large frequency offset.

(Note: The close-in phase noise of the reference signals is also amplified by the division ratio N of the divider)

The transfer function from the VCO noise θn,VCO to the output phase θout can be expressed as the following equation, and is a high-pass function.

s

(4.23)

Hence, the far-offset phase noise of the PLL is dominated by the VCO phase noise.

The transfer function from the charge pump noise current In,CP to the output phase

θ

out can be expressed as the following equation, and is a low-pass function.

(4.24)

In the design of the loop filter, phase noise contribution due to the thermal noise of

In the design of the loop filter, phase noise contribution due to the thermal noise of

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