Chapter 1 Introduction
1.3 Organization of the Thesis
In Chapter 2, we use the capacitance to discus the shift of band diagram due to dipole layer deposition with conventional SONOS-type structure. There are four topics we can discus to. First, we can discuss the influence of the dipole layer deposition between bottom oxide and trapping layer. Second, discuss the influence of the dipole deposition on Si3N4. Third, discuss the influence of the dipole deposition between trapping layer and top oxide.
Last, we can discuss the influence of the double dipole layer deposition both on bottom oxide and trapping layer. By the experiments, we can reasonably infer the impact of band structure.
In Chapter 3, we use the HfSiOx to obtain HfO2 nanocrystal nonvolatile memory after RTA treatment. Using this technique, we can readily isolate the HfO2 nanocrystals from each other within a SiO2-rich matrix. And, we match the high-k material as a blocking oxide. Last, using the structure we may exhibit superior characteristics. Moreover, we can discuss the influence of different high-material as a blocking oxide.
In Chapter 4, we use the Al2O3 and HfO2 as the dipole layer to apply on SANOS nonvolatile memory. We can discuss the impact of dipole layer on program/erase speed with two different operation mechanisms, and data retention time. Through the experiments among above, we hope to help the NVM development.
References (chapter1)
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Chang, B. E. White, and Jr. ,“A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory ,“ in Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International, 2003, pp. 26.2.1-26.2.4
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264–266,
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Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005, pp 323-326
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(a)
Fig. 1.1(a)
(b)
Fig 1.1 (a) Schematic of a basic conventional SONOS Flash memory device. (b) Vertical migration of stored charge in Si3N4 trapping and lateral migration of the stored in the HfO2
trapping layer in SONOS memory device structure.
(a)
(b)
Fig 1.2 (a) Schematic of a basic BE-SONOS [10] Flash memory device. (b) The band structure of BE-SONOS tunneling layer at low electric field during retention and hole tunneling erase at high electric field due to the band offset.
(a)
(b)
Fig 1.3 (a) An illustration of a nanocrystal memory. (b) The nanocrystal can store the charge locally due to the well isolation of nanocrystal from each other and effectively prevents formation of good conductive paths between the adjacent nodes.
(a)
(b)
Fig 1.4 (a) Schematic of a basic TANOS [17] Flash memory device. (b) The band diagram compare with SiO2 and Al2O3 as blocking oxide during erase situation. The Al2O3 can effectively inhibit gate injection than SiO .
(a) (b)
(c) (d)
Fig 1.5 (a) The principle of CHE program. (b)The band diagram of band to band hot hole injection erasing. (c) The band diagram of Fowler-Nordheim tunneling programming.(d) The band diagram of Fowler-Nordheim tunneling erasing.
Fig 1.6 Current-Voltage characteristics of a memory device in the programmed state and erase state display the V shift and memory window.
Chapter 2
Effect of Interfacial Dipole on
SONOS-type Memory Capacitors and Nanocrystals Memory Devices
2.1 Introduction
SONOS-type (Poly Si-Oxide-Nitride-Oxide-Silicon) flash memories have recently attracted much attention as a candidate for the next-generation. As a result of they have many advantages of operation characteristics such as, high P/E speed, low operation voltage, low power consumption, excellent retention, endurance, and disturbance [2.1-2.3]. As people demand more and more electronic technology, the pursuit of high performance and high reliability is the goal of many researchers.
In addition to, a high-k metal gate scheme for metal-oxide-semiconductor field-effect-transistors (MOSFET) above of 45nm technology is considered to replace the traditional SiO2/polysilicon based device due to the poly depletion effect [2.4] and gate leakage for ultra thin oxide. One of serious problem of high-k/metal gate CMOS is to control the threshold voltage (VT). As we know, the VT of n and p MOSFT must be the same in CMOS logic circuits [2.5-2.7]. Recently, the interfacial dipole with high-k/SiO2 interface has a significant role on VFB shift due to the dipole layer formation [2.8-2.13].In they year of 2007, K. Iwamoto et al indicate that the high-k/IL-SiO2 interface plays the significant role in the VFB
control of the high-k MOS device. And Y. Kamimuta et al further use the different material as gate with different high-k material to indicate the relationship such as the Figure 2.1 (a) shows. And the band diagram of high-k/SiO2 with different high-k material is shown in Figure 2.1(b). The energy offsets at the interface of Al2O3, HfO2, and Y2O3 on SiO2 are
estimated to be ±-0.57±0.05, ±0.31±0.05, and 0.23±0.05eV, respectively.
There are three theories about the origin of the dipole layer at high-k/SiO2. In the years of 2007, Sivasubramani et al considered that the dipole magnitude was determined by electronegativitiy and ionic radii of cations [2.11]. In the years of 2008, Kita and Toriumi et al reported that the areal density difference of oxygen atoms was the origin of dipole formation at high-k/SiO2 interface [2.12]. They have predicted an effect of various oxides on VFB in
terms of interface dipole, as show in Figure 2.1(c). And in 2010, Xiolei Wang et al proposes a DCIGS (dielectric contact induced gap states) model to interpret the physical origin of dipole formation for high-k/SiO2 systems [2.13]. Although, they have different point of view on the interfacial dipole, they did confirm that the high-k/SiO2 interface has a significant role on VFB
shift.
2.2 Experiment
Nitride-base SONOS-type memory capacitor are fabricated on a p-type, 20 ~ 30Ω cm, (100) 150-mm silicon substrate. After RCA clean, a 35 Å tunnel oxide was thermally grown at 800 ℃ in a horizontal furnace system. Then an ultra-thin high-k film (Al2O3 5 Å, 10 Å, 20 Å, and 30 Å or HfO2 10 Å, 30 Å) is deposited by MOCVD system or not deposited and continuous to after that step. Next a 90 Å Si3N4 film is deposited by horizontal furnace LPCVD system. Then an ultra-thin high-k film (Al2O3 10 Å, 20 Å, 30 Å or HfO2 10 Å, 20 Å) is deposited by MOCVD system or not deposited and continuous to next step. Afterward a 10nm blocking oxide is then deposited through TEOS precursor by horizontal furnace LPCVD system. Subsequently, we deposited Al as top and bottom electrode by thermal coater as well as the memory capacitor with dipole layer is finished, as the Figure 2.2 shows.
Then an example of the fabrication process of the HfO2 nano-crystal with dipole layer nonvolatile memory devices is demonstrated by a LOCOS isolation process on a p-type,
20-30 Ω cm, (100) 150-mm silicon substrate. First, a 30 Å tunnel oxide was thermally grown at 800℃ in a horizontal furnace system. Then an ultrs-thin high-k layer (HfO2 or Al2O3) is deposited by MOCVD to form dipole layer. The flow rate and pulse number of precursors is carefully modulated to obtain ~ 10 Å high-k film. Next a 120 Å amorphous HfSiOx silicate layer was deposited by MOCVD. The samples were then subjected to RTA treatment in an N2
ambient at 950℃ for 1 min to convert the HfSiOx silicate film into the separated HfO2 and SiO2 phase. Afterward a 100 Å blocking oxide is then deposited through TEOS precursor by horizontal furnace LPCVD system. Subsequently, poly-Si deposition, gate patterning, n+ source/drain (S/D) implantation , p+ body implantation, activation 950℃ for 30 second, and the remaining standard CMOS procedures were completed to fabricate SONOS-type nonvolatile memory devices, as the Figure 2.3 shows.
2.3 Results and Discussion
2.3.1 Effect of Interfacial Dipole on SONOS-type Capacitor
Previously described in our nitride-base SONOS-type memory capacitor experiments, we can discuss the contents of four. First, we can discuss the influence of high-k layer between bottom oxide and trapping layer. Second, we can discuss the influence of the high-k on Si3N4. Third, we can discuss the influence of the high-k between trapping layer and top oxide. At last, we can discuss the influence of the double dipole layer. The Cross-sectional TEM image of Si/SiO2 30 Å / Al2O3 20 Å / Si3N4 150 Å / SiO2 150Å and Si/SiO2 30 Å / Al2O3
15 Å / Si3N4 150 Å / Al2O3 20 Å /SiO2 150 Å are shown in Figures 2.4(a) and (b).
1. Discuss the influence of dipole layer between bottom oxide and trapping layer.
Figures 2.5(a) and 2.5(b) illustrate the structure of capacitors and their Capacitance-Voltage (C-V) characteristics. The samples are deposited with Al2O3 5 Å, 10 Å, 20 Å, 30 Å, and HfO2 10 Å, 30 Å by MOCVD. In Figure 2.5(b), it is found that adding an
Al2O3 or HfO2 layer causes positive VFB shift, compared with conventional SONOS capacitor.
Magnitudes of dipole are ordered in monotonous decrease: Al2O3 5 Å, Al2O3 10 Å, Al2O3 20 Å, Al2O3 30 Å HfO2 10 Å, and HfO2 30 Å. The result is shown in the Figure 2.6(a). The magnitudes of VFB shift of Al2O3 is about twice large than HfO2. Moreover, the magnitudes of VFB shift will saturate at the dipole layer with 20 Å. Here we find that the VFB shifts is larger when the high-k layer is thinner (>5 Å). In the beginning, we speculate that the thickness of dipole layer is more than we imagine. The equation follows as:
ox ox ms
FB
Q C
V /
(2-1) However, we can confirm that the thickness is not different through TEM analysis. The relationship between the VFB shifts and thickness of dipole layer may require further analysis to know why they are different with others experiments. The different of experimental procedure between ours and others are the source of dipole layer. Here, we use MOCVD and others use ALD (Atomic Layer Deposition) to deposit the dipole layer. The band diagram of this structure is shown in Figure 2.6 (b)2. Discuss the influence of the dipole on Si3N4.
Figures 2.7(a) and 2.7(b) show the structure of capacitors and their C-V characteristics.
In Figure 2.7(b) we find the VFB of the sample of Al2O3 10 Å and HfO2 10 Å with conventional SONOS almost the same. With the little different with of VFB, we took that as a variation of process. After all, the gap is much smaller than previous experiments in discussion one. Therefore, we believe the dipole is substantially suppressed on Si3N4 film in place of SiO2 in our experiments and coherence to our expectations.
3. Discuss the influence of the dipole layer between trapping layer and top oxide.
Figures 2.8(a) and 2.8(b) illustrate the structure of capacitors and their C-V characteristics. The samples are deposited with Al2O3 10 Å, 20 Å, and 30 Å by MOCVD. We find that the structures make the dipole to appear a negative VFB shift, and coherence to our
expectations. Finally, we sort out the result showing in the Figure 2.9(a). The band diagram is shown in Figure 2.9(b). However, we still find the same situation with the previous that the VFB shift is larger when the dipole layer is thinner and also saturate at thickness 20 Å. This result is the same as with the previous in discussion one, thus this rationale should exist some physical meaning we should go further analysis to understand why they like this.
4. Discuss the influence of the double dipole layer.
Figures 2.10(a) and 2.10(b) emerge the structure of capacitors and their C-V characteristics. The samples are deposited with Al2O3 10 Å, 20 Å, 30 Å, and HfO2 10 Å, 30 Å by MOCVD. Here, we contrast the sample of conventional SONOS capacitors and the sample of SONOS-type structure with Al2O3 deposition on tunneling layer, and the VFB of these samples are between this two. The VFB shift of Al2O3 is about twice of HfO2. The band diagram is shown in Figure 2.11. The relationship between the VFB shifts and thickness of dipole layer are not clearly, this may be owing to our real thickness lightly thicker than expected. As a result, make this situation has already reached saturation.
2.3.2 Effect of Interfacial Dipole on Nanocrystal Memory Device
In these experiments, we find that our devices have two serious problems which are gate injection and poly-depletion. The serious gate injection problem prohibits us to analyze the device characteristics. However, in later chapters we will address these two issues.
1. Poly depletion
Figure 2.12 illustrates IDS-VGS curve of the nanocrystal flash memory with Al2O3
dipole layer engineering. The on-off ratio can reach eight orders . However, we can find out the subthreshold swing (S.S.) is poor. After calculations, we get subthreshold swing equal to 611mV/dec. The ideal subthersold swing we can calculate by the equation:
dec
Figure 2.13 shows the charge pumping current measurement and used to calculate the value of interface state (Dit). Therefore, we have ideal value equal to 126mv/dec .The actual value is far worse with the ideal. We are reasonable guess that there are poly depletion issues, since use the wrong self-alignment implantation energy. However, we will change the process conditions and solve the problem in later chapters.
2. Gate injection
Figure 2.14(a) shows the IDS-VGS curve of the nanocrystal flash memory with programming time 1s and erasing time 1s. We find out the erasing characteristics which are suppressed by gate injection issues. The band diagram of erasing is shown in Figure 2.14(b).
We even obtain the same outcome as programming characteristics. We consider the quality of blocking oxide we adopting is worse. However, we will change the process conditions and solve the problem in later chapters.
The retention characteristics of nanocrystal flash memory at room temperature (T=25℃) are illustrated in Figure 2.15(a). It results in about 80% memory window loss for 104 second retention time at room temperature. For such a bad result we are not surprised, as a result of the poor blocking oxide. We think the trapping charge is going to escape from blocking oxide, not tunneling oxide. The band diagram of retention is shown in Figure 2.15(b). In the beginning, we are thinking whether the process using is mistake. However, we confirmed that the quality of blocking is poor and use other material in later chapters.
Although the serious gate injection problem prohibits us to analyze the device characteristics. By the C-V characteristics of conventional nanocrystal and the nanocrystal with dipole layer engineering flash memory is shown in Figure 2.16. Obviously, the discovery of positive VFB shift owing to Al2O3 dipole layer engineering.
2.4 Summary
In this chapter, we demonstrate the effect of interfacial dipole on SONOS flash memory capacitors on C-V characteristics. We find that the dipole of ultra thin Al2O3 and HfO2 layer on the SiO2 tunneling layer has a positive VFB shift and on the Si3N4 trapping layer (under SiO2 blocking layer) has a negative VFB. Furthermore, when the high-k layers are deposited on the SiO2 tunneling layer and Si3N4 trapping layer, we can find that the value of VFB is similar to VFB of conventional SONOS capacitors. The shift of Al2O3 is about twice of HfO2.
Moreover, the thinner high-k layer cause a larger VFB shift and saturate at 20 Å. The relationship between the VFB shifts and thickness of dipole layer may require further analysis to know why they are different with others experiments. When the Al2O3 dipole layer applied in Hafnium silicate nanocrystal flash memory device, we can also find out the positive VFB
shift from C-V characteristic. Although there are gate injection and poly depletion problems in our devices, we will tackle these problems in later chapters.
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