Overview of Nonvolatile Memory

The semiconductor industry have made progress continuously with complementary metal-oxide-semiconductor (CMOS) memory technology, thus people’s life have been changed by various kinds of portable electronic products ,such as cell phone, MP3 player, digital camera, notebook computer, and other personal electronic consumed products whatever you can think. It’s apparent to represent memory device, which playing the important role in our life.

It’s simple to distinguish memories into two main categories by whether the stored data will vanish or not with power supply. If they lose stored information once power supply is switch off and it’s called volatile memory, such as DRAM. Otherwise, it is Nonvolatile Memory (NVM) such as ROM. About NVM it let we can stored our picture in our digital camera and store music in MP3 player. Because it keep stored information also when the power is switch off.

With the NVM device continuously developed, we can also divide NVM into non-charge-based memory like MRAM [1.1], RAM [1.2] and charge-based memory like Intel ETOX [1.3].The typical charge-based memory is also called flash memory. As the different trapping layer, there are three types of flash memory including the floating gate (FG) type, SONOS [1.4] (Silicon/Oxide/Nitride/Oxide/Silicon) type, and nano-crystal [1.5] or metal-dot type. Among the types of memories mentioned about, flash memory has the advantage of good program/erase (P/E), low operation, small area ,low power consumption, and low cost.

In 1967,D Kahng and S. M. Sze invented the first floating-gate(FG) nonvolatile

semiconductor memory at Bell Labs[1.6]. These days, a lot of electronic products still adopt the floating-gate structure. Nevertheless, the current floating-gate flash faces a critical scaling challenge due to the floating gate coupling effect [1.7].

The tunnel oxide of floating gate device has to be thick enough (8~10nm) to maintain superior retention and endurance, but it also cause large operation voltage, high power consumption, slow program/erase (P/E) speed, and the most important, hard to be scaled. In addition to, the poly silicon floating-gate is conductive; the total charges stored in floating gate would be easily lost when the tunnel oxide has a single defect or damaged during P/E cycles, such as SILC issues [1.8]. On the other word, the scaling limit of floating-gate memory to lateral and vertical is charge loses due to SILC and the effect of parasitic capacitive coupling. Moreover, the trapping layer is conductive, so it can’t use Multi-Level Cell (MLC) to make data with double density. To overcome these disadvantages mentioned above, new memory structure, such as SONOS type, and nano-crystal or metal-dot type memory, will be the solution to these problems.

SONOS-type (Silicon/Oxide/Nitride/Oxide/Silicon) devices are forecasted as the solution beyond the 45-nm node [1.9] because charge trapping devices are naturally immune to the floating gate coupling interference. The conventional SONOS memory is shown in Figure 1.1(a). It has recently been a promising candidate for the next-generation nonvolatile memory. Contrary to the floating gate device where charge is uniformly stored in the floating gate, the charge is locally trapped in the nitride thin film. It can avoid to SILC issues, coupling effect, and not only SLC (single level cell) operation. However, conventional SONOS memory still has some problems, such as electron vertical and lateral migration show in Figure 1.1(b) and data retention. Next we did some discussion to see others people how to improve. There are three points of SONOS-type flash memory with O/N/O structure that we can discuss which were tunneling layer, trapping layer, and blocking layer.

Tunneling layer

The fist” O” is SiO2 as tunneling oxide (bottom oxide) with normal SONOS-type device.

In 2005 the MXIC use the ultra-thin “ONO” (Oxide/Nitride/Oxide) to replace the tunneling oxide and it named to BE-SONOS (Bandgap-Engineered SONOS) [1.10]. The structure is shown in Figure 1.2(a). The ultra-thin ONO layer provide a modulated tunneling barrier, it reduces direct tunneling at low electric field during retention, but it allows efficient hole tunneling erase at high electric field due to the band offset. The band structure is shown in Figure 1.2(b) .Therefore, this BE-SONOS offers fast hole tunneling erase, while it is immune to the retention problem of the conventional SONOS. And the ultra thin ONO layer is trap free and use the simple material, which may improve the reliability issues with conventional SONOS.

Trapping layer

The “N” is Si3N4 as trapping layer with normal SONOS-type device. In recent years, the trapping layer materials have been investigated to improve the cell data retention. For example, the use of an Al2O3 trapping layer and HfAlOx to replace Si3N4 have been consider since their material band gaps and high trap densities offer superior program/erase speed and data retention [1.11]. Moreover, various kinds of nanocrystal, such as silicon (Si) [1.12], germanium (Ge) [1.13], and metal nanocrystal, may be use to provide charge storage for memory devices. A basic structure for nanocrystal is shown in Figure 1.3 (a). Just like use HfSiOx to forming localized HfO2 for application in high-density two-bit nonvolatile Flash memory [1.12]. And in 1995, Tiwari et al. first proposed a Si nanocrystal nonvolatile at IBM [1.14]. For conventional SONOS memory, erase saturation [1.15] and vertical stored charge migration [1.16] are two major drawbacks. The electron migration is shown in figure.

Therefore, nanocrystal-type memories with very local storage have been invented, as the Figure 1.3(b) shows.

Blocking layer

The second “O” is SiO2 as blocking oxide (top oxide) with normal SONOS-type device.

In 2003 Samsung Electronics use Al2O3 to replace SiO2 for the blocking oxide. And they prose a new device structure with TaN metal gate instead of the n⁺ poly-Si gate which named to TANOS [1.17], the structure is shown in Figure 1.4(a). The electric field across the tunnel oxide can be increased with using high-k material for the blocking oxide. Simultaneously, the electric across blocking oxide is proportionally reduced with its dielectrics, and then the gate injection current is suppressed effectively, as the Figure 1.4(b) shows. Therefore the device can use a thicker tunneling oxide without losing P/E speed. The TaN has high value of work function to suppressed gate injection current, excellent thermal stability to over high temperature process and eliminated the ploy-depletion. Owing to the diligences on search, researches let the SONOS-type can be candidate for next-generation nonvolatile memory application.

Operation principle

About the operating mechanism of nonvolatile memory with programming and erasing, that we have Fowler-Nordheim tunneling and hot carrier injection methods. For floating gate nonvolatile memory is ”written” when we programmed the electrons into floating gate by Channel-Hot-Electron (CHE) [1.18] programming then the threshold voltage(VT) increases for the MOSFET. Otherwise, we erase the stored electrons and restoring VT to its original value by Fowler-Nordheim (FN) tunneling or band to band hot hole injection (BTBHHI) from floating to source. The VT shift between the programmed and erased states is denoted by a quality know as the “memory window”. Unlike floating gate device the trapping is conductive, when SONOS-type nonvolatile memory uses CHE to program and its just only could be erased with BTBHHI; otherwise write electron to nitride with Fowler-Nordheim tunneling and erase electron with Fowler-Nordheim tunneling, too. The principle of CHE program and the and diagram of BTBHHI erase, FN program, and FN-erase are shown in Figures 1.5(a), (b), (c), and (d). The memory state of the device can be determined by the sensing current with read voltage (V ) . The read voltage is set in the range of the memory window, as the

Figure 1.6 shows. It’s simple enough to distinguish the states of “1” or “0”, and make fast operating speed.

Extraordinary fast growing nonvolatile memory market mainly leaded by mobile applications push the nonvolatile memory technology to be cutting edge. As a result of the flexibility and higher effective speed and density which combined with a fast in-system erase capability, these low-power and robust Flash systems are ideal for a myriad of portable applications. It provide single cell electric program and fast simultaneous block electric erase.

They even are going to replace random access memory in many applications. As more and more people's needs, the System-On-Chip (SOC) notion for ultra-large scale integration (ULSI) is more and more important. A complex system can be integrated into a single chip via SOC design methodology and achieve lower power, lower cost, and higher speed than the traditional board level design. Due to the different of device modules such, thermal, material and the ears issues, there are grate challenges wait for us to solve.