Chapter 1 Introduction
1.4 Organization of This Thesis
The organization of this thesis is separated into four chapters. After a brief introduction in Chapter 1, we will introduce the devices fabrication, experimental measurement, the basic property of thin film transistor including the parameter extraction, program/erase mechanism. And we will discuss the influence of floating body drain avalanche in Chapter 2. In Chapter 3, we demonstrated a nonvolatile memory on low temperature polycrystalline silicon TFTs with Ge trapping layer. We will show the basic characteristics of the SOGOS memory and compare the device performance with various channel film thickness and device dimension, including program/erase speed, endurance, data retention, gate disturbance and drain disturbance. Finally, the conclusion and future work are given in Chapter 4.
Fig. 1-1 Schematic of a 3 × 3 partial NOR array with stacked gate cells. One drain contact hole is needed every two cells, leading to a typical unit cell size of 10 F2.
Fig. 1-2 Schematic cross sectional view of stacked gate Flash memory cell along cell channel direction. The channel hot electron programming near drain side and FN-tunneling source erase are symbolized with arrows.
V
CG≤ 0V
BTBT region Source
Depletion layer edge V
S< 0V
Fig. 1-3 Schematic illustration shows the band-to-band tunneling (BTBT) phenomenon in circled region when there is a high gate to source bias.
Chapter 2
Experimental Procedures and Device Operations
2.1 Device Fabrication
The schematic diagram of the fabrication process is illustrated in Fig. 2-1. First, a 550-nm thick oxide was deposited on the (100) 6-inch wafers. Then, a 50-nm and 100-nm thick a-Si layer was deposited as the active layer in a LPCVD system using SiH4 as source at 550°C. The a-Si was crystallized to poly-Si by solid phase crystallization (SPC) process at 600°C for 24 hours. Then the wafers were subjected to photolithography for active region definition. After a standard RCA cleaning, we deposited 11-nm TEOS oxide as tunneling oxide. Then, we deposited a thin a-Si layer, and deposited a thin Ge layer in LPCVD system using GeH4 at low temperature as trapping layer. A blocking oxide about 44nm was then deposited using TEOS oxide. A 200-nm thick a-Si was deposited to serve as the gate electrode by LPCVD. Subsequently, the n+ gate was formed by ion implantation of phosphorous at 10 keV to a dose of 5x1015 cm-2.
Then the a-Si gate electrode and the Ge/Si trapping layer with tunneling oxide were etched by poly-Si dry etcher (TCP- 9400) and the oxide dry etcher (TEL-5000), respectively.
The wafers were ion implanted by phosphorous. The energy and the dose of implantation were 15 keV to dose 5×1015cm-2 and 25kev to dose 5×1015cm-2for channel thickness 50-nm and 100-nm , respectively. Then, the n+ gate, n+ source and n+ drain region were activated at 600oC for several hours (? hour). At the same time, n+ a-Si gate was crystallized to n+ poly-Si gate. During this activation period, the previously deposited Ge trapping layer recrystallized and then formed into nanocrystals, which were embedded in oxide. As shown Fig. 2-2, the cross-sectional TEM image of the gate stack shows Ge nanocrystal embedded oxide. The
nanocrystal size was estimated about diameter of 11 nm in average. Next, a 300-nm thick TEOS oxide was deposited as passivation layer and patterned for contact holes opening. A 500-nm thick Al was immediately thermal evaporated, followed by lithography for Al pad pattern definition. The LTPS TFTs with Ge trapping layer memory was finished.
2.2 Typical Threshold Voltage Parameter Extraction
In this section, the methodology of extracting typical parameters, such as threshold voltage from device characteristics, are briefly introduced. Plenty ways are used to determinate the threshold voltage which is the most important parameter of semiconductor devices. The method to determinate the threshold voltage in my thesis is the constant drain current method that the voltage at a specific drain current INis taken as the threshold voltage.
This technique is easy and can give a threshold voltage close to that obtained by the complex linear extrapolation method. Typically, the threshold current IN= IDN/ (W / L) where IDN is a normalized drain current. Here, IDN is 100 nA and the same for all devices to extract the threshold voltage of TFTs [40].
2.3 Measurement Equipment Setup
The experimental setup for the I-V and threshold voltage characteristics measurement of the LTPS TFTs with Ge nanocrystal is illustrated in Fig. 2-3. As shown in Fig. 2-3, the characterization apparatus with semiconductor characterization system (KEITHLEY 4200), one channel pulse generator (Agilent 81110A), low leakage switch mainframe (KEITHLEY 708A), and a probe station provide an adequate capability for measuring the device I-V characteristics and executing the non-volatile memory cell program/erase operation.
The KEITHLEY 4200 equipped with programmable source-monitor units and provides a high current resolution to pico-ampere range facilitates the gate current measurement, subthreshold characteristics extraction, and the saturation drain current
measurement. The one channel Agilent 81110A with high timing resolution provides one pulse level for transient and P/E cycling endurance characterization. Another pulse level is provided by KEITHLEY 4200. The KEITHLEY 708A configured a 10-input×12-output switching matrix, switches the signals from the KEITHLEY 4200 and the Agilent 81110A to device under test in probe station, automatically. In addition, the C++ is used as the program language to achieve the KEITHLEY 4200 control of these measurement instruments [41].
2.4 Program and Erase Operation
In the past, several methods have been proposed to transport electrons into the trapping layer. The method of BBHE (Band-to-Band Hot Electron), however, is the most widely used one to program the n-channel flash memory wing to its features of higher efficiency and lower power dissipation. By applying a positive drain voltage and a positive control gate voltage to the cell, electron-hole pairs are generated by band-to-band tunneling in the deep depletion region. Subsequently, the electrons are accelerated by a lateral electric field towards the channel region and some of them will gain sufficient energy. The injection of such hot electrons into the trapping layer through the tunnel oxide is called the BBHE programming method. The major advantage of this method is its high efficiency, since electrons are generated by band-to-band tunneling and efficiently accelerated by the lateral electric field in the drain deep depletion region [42]. In our measurement, we use disadvantage of thin-film device that is floating body effect. The floating body effect will cause induced drain avalanche to occur early at high voltage. This behavior, called the floating body drain avalanche, will more improve program speed. In the next chapter, we will discuss this program mechanism particularly.
In general, the erase operation is intended to remove electrons from the trapping layer to bring the device back to its initial low threshold voltage state. Fowler-Nordheim tunneling of electrons is generally used to erase the flash memory. The control gate is applied with a
negative voltage with respect to the substrate so that FN currents flow through the gate oxide more or less uniformly over the entire channel. The charge conduction over the entire channel during the high field FN erase operation will damage the main channel and thus results in the detrimental drawbacks, such as the worse endurance and disturbs in the flash array. In addition, the generation and switching of negative voltages during erase will make the circuit design be more complicate [42]. In our measurement, we use Band-to-Band hot hole that produced by a great deal electron-hole pairs of drain avalanche. This mechanism will more improve erase speed. In the next chapter, we will discuss this erase mechanism particularly.
2.5 Endurance and Retention
Today flash memory cells are requested to guarantee 100,000 program/erase cycles.
Cycling is known to cause fairly uniform wear-out of cell performance due to the oxide damage. This experiment was performed by applying VCG=10V, VD=11V, and VS =0V during programming. After programming, erasing pulses are applied with drain current and with VCG=-11V, VS= 10V, and VS=0. The threshold voltage is measured after some program/erase cycles. The “threshold voltage window closure” is due to the traps and interface states generated during program/erase cycles. The reduction of the programmed threshold with cycling is due to trap generation in the oxide and to interface state generation at the drain side of the channel, which are usually called hot electron degradations. The evolution of erase threshold voltage reflects the dynamics of net fixed charge in the tunnel oxide as a function of the injected charge [43]: the initial lowering of the erased threshold voltage is due to positive trapped charge which enhances tunneling efficiency, while the long term increase of the erased threshold voltage is due to generation of negative traps. The cycled program/erase operations will cause the oxide degradation and lower the potential well barrier surrounding the floating gate. Hence the stored charge loss and gain in the floating gate may limit the tunneling oxide. Retention capability of flash memories has to be checked by using
accelerated test that usually adopts high electric fields and high temperature [44].
2.6 The Disturbance
The first failure phenomenon, called program disturbance, often takes place under the electric stress applied to those neighboring un-programmed cells during programming a specific cell in the array. Two types of program disturbance, gate (word-line) disturbance and drain (bit-line) disturbance need be considered. The schematic circuitry of the memory array is shown in Fig. 2-4. During programming cell A, gate disturbance occurs in the cell B and the same for those cells connected with the same with word-line because the gate stress is applied to the same word-line (WL). This is called gate disturbance. During programming cell A, drain disturbance occurs in the cell C and the same for those cells connected with the same with bit-line because the drain stress is applied to the same bit-line (BL). This is called drain disturbance. For the cell reading, the unwanted electron injection would happen while the word-line voltage and bit-line voltage are under read operation. This phenomenon would result in a significant threshold voltage of the selected cell. This is called read disturbance [45].
Wet Oxidation 550nm on (100) Si Wafer.
Deposited a-Si 50/100nm as Active Layer.
Solid Phase Crystallization at 600oC 24hr and Defined Active Region.
Deposited TEOS 11nm as Tunneling Oxide.
Deposited a-Si /Ge as Trapping Layer.
Deposited TEOS 44nm as Blocking Oxide.
Deposited a-Si 200nm as Gate Layer and P+ Implantation.
Gate Pattern Defined and Soure/Drain P + Implantation.
Fig. 2.1 Process flows of low temperature poly-Si TFTs. After deposited 300nm passvation oxide, dopant activation, metallization, and NH3 plasma treatment, we had finished device fabrication. During the dopant activation step, the Ge trapping layer was recrystallized and Ge nanocrystals embedded oxide were formed.
Ge Nanocrystal Ge Nanocrystal Ge Nanocrystal Ge Nanocrystal
(a)
(b)
Fig. 2.2 (a) Cross-sectional TEM image of the gate stack. (b) The Ge nanocrystals with about diameter of 11nm are formed on the TEOS tunneling oxide.
Poly Poly - - Si Si Gat Gat e e Bloc king Oxi de Bloc king Oxi de
Tun neli ng O xide Tun neli ng O xide
Poly Poly - - Si Si Chan nel Chan nel Poly Poly - - Si Si Gat Gat e e
Bloc king Oxi de Bloc king Oxi de
Tun neli ng O xide Tun neli ng O xide
Poly Poly - - Si Si Chan nel
Chan nel
Fig. 2.3 The experimental setup for the transfer characteristic and program/erase characteristic of LTPS TFTs with Ge nanocrystals memory.
4200 A: SMU 1
B: SMU 2 C: SMU 3 D: SMU 4 : Power
Agilent 81110A ON
OFF
Agilent 81110 A Pulse Generator
KEITHLEY 708 A Switching System Probe Station
KEITHLEY 4200 Semiconductor Characterization System
Fig. 2.4 During Cell A is programmed, the gate disturbance takes place in Cell B and the drain disturbance takes place in Cell C.
Cell A
Cell B
Cell C Gate Disturbance
Drain Disturbance
Chapter 3
Electrical Characteristics of TFT Flash Memory
3.1 Program and Erase Mechanisms
In this section, we will discuss the program and erase injection mechanism. The programming scheme is executed by using floating body induced drain avalanche hot electron and channel hot electron to injection charge into the Ge-NCs trapping layer. This program mechanism is different form drain avalanche hot electron in the bulk MOSFETs. On the other hand, the erasing scheme is executed by using Band-to-Band hot holes injection [43] to combine negative charge in the trapping layer. The injection components and efficiency for different gate bias and drain bias conditions on devices with different channel thickness will be discussed.
3.1.1 Floating Body Effect Induced Drain Avalanche in Poly-Si Thin Film Transistors
The drain avalanche is a kind of junction breakdown mechanism. And it needs different drain bias for the bulk MOSFETs and thin-film device. For the bulk MOSFETs, it must apply large drain voltage to form reverse pn junction bias and then drain avalanche will occur. But for thin-film device, such as SOI or TFTs that has floating body, floating p-base is similar to the known “snap-back” mechanism of MOS transistor [44]. When applying drain bias and zero gate bias, the hole of impact ionization at depletion region of drain-side will flow into source and then additional electron will flow into depletion region of drain-side form source in return. This phenomenon will induce drain avalanche to occur early. So it can be occurred drain avalanche at smaller drain bias for SOI devices or TFTs. In general, we hope to avoid this situation for normal device operations because it will make our device breakdown early. Fig. 3-1 shows illustration of floating body effect in a TFT device, when
VG=VS is 0V and VD is 12V. Applying smaller drain bias, we can get a great deal of electron-hole pairs due to drain avalanche before junction breakdown. We use the mechanism of floating body induced drain avalanche for program mode. Fig. 3-2 shows illustration of floating body effect induced drain avalanche hot electron injection in a TFT memory, when VG=10V, VS=0V and VD=12V. The avalanche current serves as the “base” current and the bipolar action contributes additional current flowing through the drain side and additional hot electrons generated for injection. Some of them with energy higher than the barrier height of SiO2/Si conduction band, so they can surmount the barrier and are injected into the trapping layer. Fig. 3-3 shows drain avalanche current for 50nm channel thickness with different gate width of 1μm and 10μm, and at different VG=0V and VG=10V. (a) When VD is larger than 10V, we can observe a suddenly large drain current for 1μm Gate length. (b) When VD is larger than 8.4V, we can also observe a suddenly large drain current for 0.8μm gate length.
When gate length is smaller, drain avalanche voltage is lower. And we also define program region of drain bias from Fig. 3-3. Fig. 3-4 shows drain avalanche current for 100nm channel thickness with different gate width 1μm and 10μm, and different VG=0V and VG=10V. (a) When VD is larger than 8.4V, we can observe a suddenly large drain current for 1μm gate length. (b) When VD is larger than 8V, we can also observe a suddenly large drain current for 0.8μm gate length. When gate length is smaller, drain avalanche voltage is also lower. The same as 50nm channel thickness, we also define program region of drain bias.
According to all of the above, the floating body effect is more serious for 100nm channel thickness than 50nm. So the floating body induced drain avalanche will occur early for 100nm channel thickness and it has more low programming voltage for 0.8μm gate length and 100nm channel thickness. Fig. 3-5 shows comparison for drain avalanche current of different channel thickness and VG, (a) gate length and width are both 1μm, and (b) gate length and width are both 0.8μm. If program voltage is set at VG=10V, Fig. 3-6 shows the
Gate length and width are both 1μm, and (b) gate length and width are both 0.8μm.
In n-channel, when a negative gate bias and a positive drain bias are applied to the cell, electron-hole pairs are generated in the drain region. The channel hole current will be accelerated by a lateral electric field toward the channel region. And heated holes will be generated and be injected by band-to-band into the gate at the gate-drain overlap region [45].
The injection of such hot holes into Ge-NCs trapping layer through the tunnel oxide is used for erase operation in our TFTs memories.
3.1.2 Transfer Characteristic of Program/Erase State
The floating body effect induced drain avalanche (FBDA) hot electrons injection and Band-to-Band hot holes injection were employed for programming and erasing mode, respectively. Fig. 3-7 shows the transfer characteristic of erase state and program state for 0.8μm gate length and width. (a) Channel thickness is 50nm, and (b) channel thickness is 100nm. We clearly observed that memory window is quite large. Applying VG=10V, VD=11V and VG=VD=10V, a memory window larger than 8V can be easily achieved for TCH=50nm and TCH=100nm, respectively, when program time is 1sec. When channel thickness is 50nm, leakage current of program state is lower. Because it has more defects in thin channel thickness than thick one, the leakage current of 50nm channel thickness is low about 10-12A.
3.2 Characteristics of Program/Erase
In this section, we will discuss the program speed of floating body effect induced drain avalanche hot electrons injection mode and erase speed of band-to-band hot holes injection mode, respectively.
3.2.1 Program Speed
Fig. 3-8(a)-(b) exhibits program speed characteristic for different programming conditions. This gate length and width are both 1μm, and channel thickness is 50nm. We changed drain voltage bias with 11V and 12V to measure program speed at fixed 10V and
12V gate voltage bias, respectively. We can see that the programming time can be as short as 10μs if the windows margin is set about 1V with VD=12V for two cases at fixed 10V and 12V gate bias. Fig. 3-9(a)-(b) shows program speed characteristic, when we changed gate voltage bias with 10V and 12V to measure program speed for fixed 11V and 12V drain voltage bias respectively. For the same VD, that VG is increased doesn’t obviously improve program speed.
Fig. 3-10(a)-(b) exhibits program speed characteristic for different programming conditions.
This gate length and width are both 0.8μm, and channel thickness is 50nm. We also changed drain voltage bias with 10V and 11V to measure program speed for fixed 10V and 12V gate bias respectively. We can also see that the programming time can be as short as 10μs if the windows margin is set about 1V with VD=11V for two cases of fixed 10V and 12V gate bias.
Fig. 3-11(a)-(b) shows program speed characteristic, when we changed gate voltage bias with 10V and 12V to measure program speed for fixed 10V and 11V drain voltage bias respectively.
For the same VD, that VG is increased doesn’t also obviously improve program speed.
Fig. 3-12(a)-(b) exhibits program speed characteristic for applying drain voltage bias with 10V and 11V, then fixed 10V and 12V gate voltage bias respectively. This gate length and width are both 1μm, and channel thickness is 100nm. The programming time can be as short as 10μs if the windows margin is set about 1V when applying VD=11V. Fig. 3-13(a)-(b) shows program speed characteristic for applying gate voltage bias with 10V and 12V, then fixed 10V and 11V drain voltage bias respectively. When applying the same VD, that VG is increased doesn’t also obviously improve program speed. Fig. 3-14(a)-(b) exhibits program speed characteristic for applying drain voltage bias with 9V and 10V, then fixed 10V and 12V gate voltage bias respectively. This gate length and width are both 0.8μm, and channel thickness is 100nm. The programming time can be as short as 10μs if the windows margin is set about 1V when applying VD=10V. Fig. 3-15(a)-(b) shows program speed characteristic for applying gate voltage bias with 10V and 12V, then fixed 9V and 10V drain voltage bias
In conclusion, Table 3-1 and Table 3-2 show summary for program memory window of 1ms program time, and compare fixed VG=10V and VG=12V for all cases of different VD. For all cases, we use two kind of drain voltage bias for strong and weak drain avalanche, respectively. It can be clearly seen that larger drain bias induced strong drain avalanche makes faster program speed. On the other hand, the gate bias only supplies a vertical field to hot electrons for injected into the trapping layer so the influence of increased gate voltage is not conspicuous. The smaller gate length needs only lower program voltage for the same Vt shift.
This is called gate length effect. And the program voltage is lower for 100nm channel
This is called gate length effect. And the program voltage is lower for 100nm channel