Characteristics of Program/Erase

In this section, we will discuss the program speed of floating body effect induced drain avalanche hot electrons injection mode and erase speed of band-to-band hot holes injection mode, respectively.

3.2.1 Program Speed

Fig. 3-8(a)-(b) exhibits program speed characteristic for different programming conditions. This gate length and width are both 1μm, and channel thickness is 50nm. We changed drain voltage bias with 11V and 12V to measure program speed at fixed 10V and

12V gate voltage bias, respectively. We can see that the programming time can be as short as 10μs if the windows margin is set about 1V with VD=12V for two cases at fixed 10V and 12V gate bias. Fig. 3-9(a)-(b) shows program speed characteristic, when we changed gate voltage bias with 10V and 12V to measure program speed for fixed 11V and 12V drain voltage bias respectively. For the same VD, that VG is increased doesn’t obviously improve program speed.

Fig. 3-10(a)-(b) exhibits program speed characteristic for different programming conditions.

This gate length and width are both 0.8μm, and channel thickness is 50nm. We also changed drain voltage bias with 10V and 11V to measure program speed for fixed 10V and 12V gate bias respectively. We can also see that the programming time can be as short as 10μs if the windows margin is set about 1V with V_D=11V for two cases of fixed 10V and 12V gate bias.

Fig. 3-11(a)-(b) shows program speed characteristic, when we changed gate voltage bias with 10V and 12V to measure program speed for fixed 10V and 11V drain voltage bias respectively.

For the same VD, that VG is increased doesn’t also obviously improve program speed.

Fig. 3-12(a)-(b) exhibits program speed characteristic for applying drain voltage bias with 10V and 11V, then fixed 10V and 12V gate voltage bias respectively. This gate length and width are both 1μm, and channel thickness is 100nm. The programming time can be as short as 10μs if the windows margin is set about 1V when applying VD=11V. Fig. 3-13(a)-(b) shows program speed characteristic for applying gate voltage bias with 10V and 12V, then fixed 10V and 11V drain voltage bias respectively. When applying the same VD, that VG is increased doesn’t also obviously improve program speed. Fig. 3-14(a)-(b) exhibits program speed characteristic for applying drain voltage bias with 9V and 10V, then fixed 10V and 12V gate voltage bias respectively. This gate length and width are both 0.8μm, and channel thickness is 100nm. The programming time can be as short as 10μs if the windows margin is set about 1V when applying V_D=10V. Fig. 3-15(a)-(b) shows program speed characteristic for applying gate voltage bias with 10V and 12V, then fixed 9V and 10V drain voltage bias

In conclusion, Table 3-1 and Table 3-2 show summary for program memory window of 1ms program time, and compare fixed V_G=10V and V_G=12V for all cases of different V_D. For all cases, we use two kind of drain voltage bias for strong and weak drain avalanche, respectively. It can be clearly seen that larger drain bias induced strong drain avalanche makes faster program speed. On the other hand, the gate bias only supplies a vertical field to hot electrons for injected into the trapping layer so the influence of increased gate voltage is not conspicuous. The smaller gate length needs only lower program voltage for the same Vt shift.

This is called gate length effect. And the program voltage is lower for 100nm channel thickness than 50nm, because the drain avalanche voltage is lower for 100nm channel thickness, as shown in Fig. 3-5. According to all of the above, we can clearly observe that FBDA can improve injection efficiency and get faster program speed.

3.2.2 Erase Speed

Fig. 3-16(a)-(b) shows erase speed characteristic for different erasing conditions. The gate length and width are both 1μm, and channel thickness is 50nm. We changed drain voltage bias with 11V and 12V to measure erase speed for fixed -10V and -12V gate voltage bias respectively. We can see that erasing time can be as short as μs in order to combine negative charge in the trapping layer. Fig. 3-17(a)-(b) exhibits erase speed characteristic when we changed gate voltage bias with -10V and -12V to measure erase speed for fixed 11V and 12V drain voltage bias respectively. The increased gate bias does not obviously accelerate erase speed. Fig. 3-18(a)-(b) shows erase speed characteristic for different erasing conditions.

This gate length and width are both 0.8μm, and channel thickness is 50nm. We changed also drain voltage bias with 10V and 11V to measure erase speed for fixed -10V and -12V gate voltage bias respectively. We can clearly see that the μs order of erasing time can combine negative charge in the trapping layer. Fig. 3-19(a)-(b) exhibits erase speed characteristic when we changed gate voltage bias with -10V and -12V to measure erase speed for fixed 10V and 11V drain voltage bias respectively. The erase speed of different gate bias is almost the same.

Fig. 3-20(a)-(b) shows erase speed characteristic for applying drain voltage bias with 10V and 11V, then fixed -10V and -12V gate voltage bias respectively. The gate length and width are both 1μm, and channel thickness is 100nm. Fig. 3-21(a)-(b) exhibits erase speed characteristic for applying gate voltage bias with -10V and -12V, then fixed 10V and 11V drain voltage bias respectively. Fig. 3-22(a)-(b) shows erase speed characteristic for applying drain voltage bias with 9V and 10V, then fixed -10V and -12V gate voltage bias respectively.

The gate length and width are both 1μm, and channel thickness is 100nm. Fig. 3-23(a)-(b) exhibits erase speed characteristic for applying gate voltage bias with -10V and -12V, then fixed 9V and 10V drain voltage bias respectively.

In conclusion, Table 3-3 and Table 3-4 show summary for erase Vt shift of 100ms erase time, and compared at fixed VG=-10V and VG=-12V for all cases of different VD. The gate bias supplies only a vertical field to collect hot holes for combined negative charge in the trapping layer so the influence of increased gate voltage is not obvious. On the other hand, for all cases, we use two kind of drain voltage bias for strong and weak impact ionization at depletion of drain-side, respectively. It can be clearly seen that larger drain bias induced strong impact ionization makes faster erase speed. The erase voltage is lower for 100nm channel thickness than 50nm ones. And the smaller gate length needs only lower erase voltage for the same Vt shift. According to all of the above, we can clearly observe that our LTPS TFT memory with Ge-NCs trapping layer has very higher hot holes injection efficiency and faster erase speed.