Chapter 1 Introduction
1.4 Organization of This Thesis
The organization of this thesis is separated into four chapters.
In Chapter 1, A brief introduction are introduced.
In Chapter 2, we introduced the capacitance fabrication, and experimental measurement.
In Chapter 3, we demonstrated a SONOS memory with Si-NCs trapping layer. We will show the basic characteristics of the Si-NCs SONOS memory and compare the capacitance performance with various tunnel oxide film thickness and quality, including program window, data retention. We will discuss the influence of different tunnel oxide.
In Chapter 4, the conclusion is given.
Fig. 1-1 The cell structure of a nitride storage flash memory cell.
Fig. 1-2 Schematic representation of a NROM cell with physically 2-bits storage.
The shaded area in the nitride layer represents stored charges.
Table 1-1 Operation bias conditions of a NROM cell.
Fig. 1-3 The device structure of nanocrystal non-volatile memory.
Chapter 2
Experiment Procedures
and Electric Characteristic of Capacitor
2.1 Capacitor Fabrication
The schematic diagram of the fabrication process is illustrated in Fig.2-1.Three different types of tunnel oxide are grown on p-type (100) silicon substrates after RCA cleaning. (1) 3-nm thick SiO2 film was thermally grown in dry N2O atmosphere by horizontal-furnace. (2) 2.5-nm thick SiO2 film was thermally grown in dry N2O atmosphere by vertical-furnace. (3) 2.5-nm thick SiO2 film was thermally grown in dry O2 atmosphere by vertical-furnace. Then, a 3-nm thick silicon nitride films was deposited as the trapping layer in a LPCVD system using SiH2Cl2 and NH3 as source for 30 and 130 sccm, respectively. Si-NCs were formed on the 3-nm thick silicon nitride films immediately by LPCVD for 2-min and 1-min and 30-sec.
The deposition of amorphous silicon nucleation was kept at 550°C and the pressure was controlled at 100-mTorr. The flow rate of the reaction gas of SiH4 was 85-sccm. Then, the silicon nitride capped on the Si-NCs was 4-nm. During this high temperature period, the previously deposited thin amorphous silicon nucleation was crystallized and then formed into poly-Si nanocrystals, which were embedded in silicon nitride films as show in Fig. 2-2. The formation of Si-NCs was confirmed by atomic force microscopy (AFM) as shown in Fig’s.2-3 (a)-(c). We estimated size and density of Si-NCs_1m30s and Si-NCs_2min sample in Table 2-1. A blocking oxide about 20-nm was then deposited using high density plasma chemical vapor deposition (HDPCVD) oxide. A 200-nm thick poly-Si was deposited to serve as the gate electrode by LPCVD. Subsequently, the n+ poly-Si gate was formed by phosphorous ion implanted at 40-keV to a dose of 5x1015 cm-2. Also, the sample without Si-NCs was fabricated as a control sample.
After phosphorous implantation, activation was formed at 900°C for 30 minutes. Then, the poly-Si gate electrode and the Si-NCs trapping layer with blocking oxide were etched by poly-Si dry etcher (TCP- 9400) and the oxide dry etcher (TEL-5000). The capacitance with Si-NCs memory was made.
2.2 Typical Program Window Parameter Extraction
In this section, the methodology of extracting typical parameters, such as program window from device characteristics, are briefly introduced. Plenty ways are used to determinate the program window which is the most important parameter of memory devices.
The method to determinate the program window in my thesis is the constant capacitance method that the voltage at a specific gate voltage VGis taken as the program window. This technique is easy and can give a program window close to that obtained by the capacitance-voltage hysteresis method. Typically, the program window △VFB = VFB’-VFB where VFB is a normalized flat-band voltage. Here, VFB’ is the flat-band voltage after program condition for all capacitance to extract the program window of Si-NCs memory.
2.3 Measurement Equipment Setup
The experimental setup of for the I-V and threshold voltage characteristics measurement of the SONOS is illustrated in Fig.2-4. As shown Fig.2-4, the characterization apparatus with semiconductor characterization system (KEITHLEY 4200), one channel pulse generator (Agilent 81110A), low leakage switch mainframe (KEITHLEY 708A), and a probe station provide an adequate capability for measuring the device I-V characteristics and executing the SONOS memory cell program/erase operation.
The KEITHLEY 4200 equipped with programmable source-monitor units (SMU) and provides a high current resolution to pico-ampere range facilitates the gate current measurement, subthreshold characteristics extraction, and the saturation drain current
measurement. The one channel Agilent 81110A with high timing resolution provides one pulse level for transient and P/E cycling endurance characterization. Another pulse level is provided by KEITHLEY 4200. The KEITHLEY 708A configured a 10-input×12-output switching matrix, switches the signals from the KEITHLEY 4200 and the Agilent 81110A to device under test in probe station, automatically. In addition, the C++ is used as the program language to achieve the KEITHLEY 4200 control of these measurement instruments [27].
2.4 Characteristic of Program/Erase
2.4.1 Program Mechanism
Fowler-Nordheim tunneling is a field-assisted carrier tunneling mechanism [28], when a large positive voltage is applied across a poly-ONO-substrate structure, its band structure will be influenced as indicated in Fig.2-5. Due to high electrical field, electrons in the Si conduction band as triangular energy barrier with a width dependent on applied electric field. At sufficient high fields, the width of barrier becomes small enough to tunnel through the barrier from the Si conduction band into Si-NCs electron trap center or nitride trap layer.
Fig.2-6 shows program window characteristic of different samples. The program window of control, Si-NCs_1m30s and Si-NCs_2min are about 3.58-V, 6.25-V and 8.98-V, respectively. Summary for program window of different sample when program voltage VG=25-V and 10-sec program time in Table 2-2. The program window of Si-NCs is larger for control sample. And the larger Si-NCs size has more trapping sites for large memory window. Fig’s.2-7 (a)-(c) exhibit program window characteristic of different samples when program voltage was set at 15-V, 20-V and 25-V and stressed for 1-sec, 5-sec and 10-sec, respectively. The tunnel oxide is dry N2O 3-nm by horizontal-furnace.
Fig’s. 2-8 (a)-(c) show program window characteristic of different samples when program voltage was set at 15-V, 20-V and 25-V and stressed for 1-sec, 5-sec and 10-sec,
respectively. The tunnel oxide is dry N2O 2.5-nm by vertical-furnace. And Fig’s. 2-9 (a)-(c) exhibit program window characteristic of different samples when program voltage was set at 15-V, 20-V and 25-V and stressed for 1-sec, 5-sec and 10-sec, respectively.
The tunnel oxide is dry O2 2.5-nm by vertical-furnace. Summary for program window of different sample when program voltage 15-V, 20-V and 25-V and stress 1-sec, 5-sec and 10-sec, respectively. The program window of Si-NCs is larger for control sample. The tunnel oxide is dry N2O 3-nm by horizontal-furnace.
2.4.2 Erase Mechanism
Fig. 2-10 exhibit erase characteristic of different negative gate bias. The gate bias VG= -15-V, t=10-sec,can be erased △VFB shift about -0.5-V. But, when the gate bias increasing -20-V, t=1-sec, because gate injection effect be programmed △VFB shift about 0.8-V.
Fowler-Nordheim tunneling is a field-assisted carrier tunneling mechanism, when a large negative voltage is applied across a poly-ONO-substrate structure, its band structure will be influenced as indicated in Fig.2-11.
Because the capacitor can only be programmed/ erased by Fowler-Nordheim tunneling mechanism, the quality of blocking oxide is important for this high field stressing. We found that the quality of our blocking oxide is not so good, causing electron injection into oxide which makes the erasing not so easy. To look for some other material or better quality blocking oxides is necessary. Using high-k material (Al2O3, HfO2 …etc) or HTO to replace already existed blocking oxide and using p+ poly-Si gate or larger work function metal gate would to replace n+ poly-Si gate be helpful[29-32].
2.5 Characteristic of Retention
2.5.1 Characteristic of Retention for Different Temperature
Data retention is an important reliability issue of SONOS memories. In general, retention capability of SONOS memories has to be checked by using accelerated test that
usually adopts high electric fields and high temperature [33]. In this section, we will discuss data retention of capactior after programming with different temperature. In general, the flash memory cells are required for a long 100,000 seconds. Timing is known to cause fairly uniform wear-out of cell performance due to the oxide damage.
Fig’s. 2-12 (a)-(c) show retention characteristic of different temperature for △ VFB=2-V. The tunnel oxide of 3-nm was grown in dry N2O by horizontal-furnace. Fig’s. 2-13 (a)-(c) exhibit retention characteristic of different temperature for △VFB=2-V. The tunnel oxide of 2.5-nm was grown in dry N2O by vertical-furnace. Fig’s. 2-14 (a)-(c) show retention characteristic of different temperature for △VFB=2-V. The tunnel oxide of 2.5-nm was grown in dry O2 by vertical-furnace. We can clearly see that the memory window narrows to about 2-V after 104 seconds for all samples.
2.5.2 Characteristic of Retention for Different Si-NCs Sizes
In this section, we will discuss data retention for capactior after programming with different Si-NCs sizes. In general, the flash memory cells are required to keep the charge for 104 seconds. Timing is known to cause fairly uniform wear-out of cell performance due to the oxide damage.
Fig’s. 2-15 (a)-(c) show retention characteristic of different Si-NCs sizes for △VFB=2-V.
The tunnel oxide of 3-nm was grown in dry N2O by horizontal-furnace. Fig’s. 2-16 (a)-(c) exhibit retention characteristic of different Si-NCs sizes for △VFB=2-V. The tunnel oxide of 2.5-nm was grown in dry N2O by vertical-furnace. Fig’s. 2-17 (a)-(c) show retention characteristic of different Si-NCs sizes for △VFB=2-V. The tunnel oxide of 2.5-nm was grown dry O2 by vertical-furnace. The memory window narrows to about 2-V after 104 seconds for all samples. We can clearly see that the best data retention is Si-NCs_1-min and 30-s sample.
2.5.3 Characteristic of Retention for Different Tunnel Oxide
In this section, we will discuss data retention for capactior after programming with
different tunnel oxide. In general, the flash memory cells are required to keep the charge for 104 seconds. Timing is known to cause fairly uniform wear-out of cell performance due to the oxide damage.
Fig’s. 2-18 (a)-(c) show retention characteristic of different tunnel oxide thickness for
△VFB=2-V at T=25°C. Fig’s. 2-19 (a)-(c) exhibit retention characteristic of different tunnel oxide thickness for △VFB=2-V at T=85°C. Fig’s. 2-20 (a)-(c) show retention characteristic of different tunnel oxide thickness for △VFB=2-V at T=150°C. The memory window narrows to about 2-V after 104 seconds for all samples. It is clearly to see that the best data retention is tunnel oxide for dry N2O 3-nm by horizontal-furnace.
2.6 Summary
For the program window, Si-NCs has more trapping sites than SONOS memory. The program window of Si-NCs is larger for control sample. And the larger Si-NCs size has more trapping sites similar to floating gate for large memory window.
For the data retention, thermionic emission, direct tunneling and trap-to-trap tunneling, in relating to the data loss, are the three dominant leakage components [34-35]. The reduction of the programmed flat band voltage is due to trap generation in the oxide and also interface state generation between tunnel oxide and channel interface, which are usually called electron degradations. In our capacitor, the Si-NCs memory window still maintains quite about 2-V even through stressed for 104 seconds.
At temperature T=25oC and T=85oC, all cases presented good retention characteristics but charge loss is serious for control sample than Si-NCs of capacitor sample at high temperature. This also shows that the trapping capability of Si-NCs trapping layer is very excellent. On the other hand, we observed larger charge loss percentage for ten years when using accelerated test at temperature T=150oC. This charge loss is due to the poor quality of tunnel oxide which results in many leakage current paths.
For different tunnel oxides, all cases presented good retention characteristics but charge loss is serious for tunnel oxide by dry O2 2.5-nm than N2O 2.5-nm and 3-nm sample. This also shows that the quality of tunnel oxide of 3-nm grown by dry N2O is very excellent. On the other hand, we observed larger charge loss percentage for ten years when using accelerated test for tunnel oxide of 2.5-nm grown in dry O2 sample. Based on the above result, we know the quality of dry N2O 3-nm by horizontal-furnace is better than that of dry O2 2.5-nm by vertical-furnace [36-37].
Fig. 2-1 Structure of Si-NCs SONOS memory. During the nitride deposition step, the Si-NCs trapping layer was crystallized and Si-NCs embedded in Si3N4 were formed.
Tunneling Oxide
and Nitride 3nm at 780 °C
a-Si nucleation : 1m30s ~ 2min At 550°C, P = 100mTorr, SiH4 = 85sccm
Poly-Si-NCs after Nitride 4nm at 780 °C
Fig. 2-2 Si-NCs formation. During the 4-nm nitride deposition step, the a-Si nucleation convert to poly-Si-NCs and Si-NCs embedded in Si3N4 were formed.
(a)
(b)
(c)
Fig. 2-3 AFM pictures of Si nanocrystals deposited on Si3N4 (a) control sample (b) Si-NCs_1m30s sample and (c) Si-NCs_2min sample, with the same growth conditions. The densities are, respectively, 6.7x1011 and 3x1011 cm2. The diameters are about, respectively, 8 and 10 nm.
Table 2-1 Size and density of Si-NCs_1m30s and Si-NCs_2min sample.
3x10
11~10 Si-NCs_2min
6x10
11~8 Si-NCs_1m30s
Density( 1/cm
2) Size( nm )
sample
3x10
11~10 Si-NCs_2min
6x10
11~8 Si-NCs_1m30s
Density( 1/cm
2) Size( nm )
sample
Fig. 2-4 The experimental setup for the transfer characteristic and program/erase characteristic of SONOS with Si nanocrystals memory.
Fi
program. Energy band representation of Fowler-Nordheim tunneling. Electron in Si conduction band tunnel through the triangular energy barrier.
g. 2-5 Positive gate voltage applied when use Fowler-Nordheim tunneling to
Program Window@tunnel oxide N2O 3nm VG=25V , t=10sec Program Window@tunnel oxide N2O 3nm VG=25V , t=10sec
Fig. 2-6 Program window characteristic of different sample. The program window of control, Si-NCs_1m30s and Si-NCs_2min sample are about 3.58V, 6.25V and 8.98V, respectively.
Table 2-2 Summary for program window of different sample when program voltage VG=25-V and program time 10-sec. The program window of Si-NCs is larger for control sample. And the larger Si-NCs size has more trapping sites for large memory window. Tunnel Oxide_N2O 3nm Control Sample
Program Voltage ( V )
0
(b)
Fig. 2-7 Program window characteristic of different sample when program voltage (c)
15, 20 and 25V stress 1sec, 5sec and 10sec, respectively. (a) control sample, (b) Si-NCs_2min sample and (c) Si-NCs_1m30s sample. The tunnel oxide is dry N2O 3nm by horizontal-furnace.
Program Window Tunnel Oxide_N2O 3nm Si-NCs_2min
Program Voltage ( V )
0 2 4 6 8
1sec 5sec
V FB shift ( V ) 10sec
15 20 25
Program Window Tunnel Oxide_N2O 3nm Si-NCs_1m30s
Program Voltage ( V )
0 2 4 6 8
1sec
V FB shift ( V )
5sec 10sec
15 20 25
0 2 4 6 8 10
Program Window Tunnel Oxide_N2O 2.5nm Control Sample
Program Voltage ( V ) (a)
(b) 1sec
V FB shift ( V )
5sec 10sec
15 20 25
0 2 4 6 8 10
Program Window Tunnel Oxide_N2O 2.5nm Si-NCs_2min
Program Voltage ( V ) 1sec
V FB shift ( V )
5sec 10sec
15 20 25
0 2 4 6 8 10
(c)
Fig. 2-8 Program window characteristic of different sample when program voltage 15, 20 and 25V stress 1sec, 5sec and 10sec, respectively. (a) control sample, (b) Si-NCs_2min sample and (c) Si-NCs_11m30s sample. The tunnel oxide is dry N2O 2.5nm by vertical-furnace.
(a) Program Window Tunnel Oxide_N2O 2.5nm Si-NCs_1m30s
Program Voltage ( V ) 1sec
V FB shift ( V )
5sec 10sec
15 20 25
Program Window Tunnel Oxide_O2 2.5nm Control Sample
Program Voltage ( V )
15 20 25
V FB shift ( V )
0 2 4 6
1sec 5sec 10sec
Fig. 2-9 Program window characteristic of different sample when program voltage (b)
(c)
15, 20 and 25V stress 1sec, 5sec and 10sec, respectively. (a) control sample, (b) Si-NCs_2min sample and (c) Si-NCs_1m30s sample. The tunnel oxide is dry O2
2.5nm by vertical-furnace.
Program Window Tunnel Oxide_O2 2.5nm Si-NCs_1m30s
Program Voltage ( V )
15 20 25
V FB shift ( V )
0 2 4 6
1sec 5sec 10sec Program Window Tunnel Oxide_O2 2.5nm Si-NCs_2min
Program Voltage ( V )
0 2 4 6
1sec 5sec
V FB shift ( V ) 10sec
15 20 25
able 2-3 Summary for program window of different sample when program voltage 15, 20 T
and 25V and stress 1sec, 5sec and 10sec, respectively. The program window of Si-NCs is larger for control sample. The tunnel oxide is dry N2O 3nm by horizontal-furnace.
8.98
Program Window_N2O 3nm
8.98
Program Window_N2O 3nm
Fig. 2-10 Erase characteristic of different negative gate bias. The gate bias VG=-15V, 0
t=10sec,can be erased △VFB shift about -0.5V. Because gate injection effect, when the gate bias VG=-20V, t=1sec, be programmed △VFB shift about 0.8V.
Fig. 2-11 Negative gate voltage applied when use Fowler-Nordheim tunneling to erase. Energy band representation of Fowler-Nordheim tunneling. Electron in Si-NCs trapping layer and poly-Si gate are tunnel through the energy barrier.
(a) (a) Retention
Different Temperature Tunnel Oxide N2O 3nm Control Sample
Time ( sec )
100 101 102 103 104
-0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00
ΔV FB shift ( V )
25oC 85oC 150oC
Fig. 2-12 Data retention characteristic of different temperature for △VFB=2V. The (b)
(c)
tunnel oxide is dry N2O 3nm by horizontal-furnace. (a) control sample, (b) Si-NCs_2min sample and (c) Si-NCs_1m30s sample.
Retention
(a)
(b) Retention
Different Temperture Tunnel Oxide N2O 2.5nm Control Sample
Different Temperture Tunnel Oxide N2O 2.5nm Si-NCs_2min
(c)
Fig. 2-13 Data retention characteristic of different temperature for △VFB=2V. The tunnel oxide is dry N2O 2.5nm by vertical-furnace. (a) control sample, (b) Si-NCs_2min sample and (c) Si-NCs_1m30s sample.
(a) Retention
Different Temperture Tunnel Oxide N2O 2.5nm Si-NCs_1m30s
Different Temperture Tunnel Oxide O2 2.5nm
Fig. 2-14 Data retention characteristic of different temperature for △VFB=2V. The (b)
(c)
tunnel oxide is dry O2 2.5nm by vertical-furnace. (a) control sample, (b) Si-NCs_2min sample and (c) Si-NCs_1m30s sample.
Retention
Different Temperture Tunnel Oxide O2 2.5nm
Different Temperture Tunnel Oxide O2 2.5nm
(a)
(a)
(c)
Fig. 2-15 Data retention characteristic of different sample for △VFB=2V. The tunnel oxide is dry N2O 3nm by horizontal-furnace. (a) At 25℃, (b) At 85℃ and (c) Tunnel Oxide N2O 2.5nm Program ΔVFB : 2V
Fig. 2-16 Data retention characteristic of different sample for △VFB=2V. The Tunnel Oxide N2O 2.5nm Program ΔVFB : 2V Tunnel Oxide N2O 2.5nm Program ΔVFB : 2V
(a)
(c)
Fig. 2-17 Data retention characteristic of different sample for △VFB=2V. The tunnel oxide is dry O2 2.5nm by vertical-furnace. (a) At 25℃, (b) At 85℃ and (c)
Different Tunnel Oxide Thickness Control Sample
Fig. 2-18 Data retention characteristic o ferent tunnel oxide film for △VFB=2V (b)
(c) f dif
at T=25℃. (a) control sample, (b) Si-NCs_2min sample and (c) Si-NCs_1m30s sample.
Retention@25oC
Different Tunnel Oxide Thickness Si-NCs_2min
Different Tunnel Oxide Thickness Si-NCs_1m30s
(a)
(b) Retention@85oC
Different Tunnel Oxide Thickness Control Sample
Time ( sec )
100 101 102 103 104
-0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00
ΔV FB shift ( V )
N2O 3nm N2O 2.5nm O2 2.5nm
Retention@85oC
Different Tunnel Oxide Thickness Si-NCs_2min
Time ( sec )
100 101 102 103 104
-0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00
ΔV FB shift ( V )
N2O 3nm N2O 2.5nm O2 2.5nm
(c)
Fig. 2-19 Data retention characteristic of different tunnel oxide film for △VFB=2V at T=85℃. (a) control sample, (b) Si-NCs_2min sample and (c) Si-NCs_1m30s sample.
(a) Retention@85oC
Different Tunnel Oxide Thickness Si-NCs_1m30s
Different Tunnel Oxide Thickness Control Sample
Fig. 2-20 Data retention characteristic o ferent tunnel oxide film for △VFB=2V (b)
(c) f dif
at T=150℃. (a) control sample, (b) Si-NCs_2min sample and (c) Si-NCs_1m30s sample.
Retention@150oC
Different Tunnel Oxide Thickness Si-NCs_2min
Different Tunnel Oxide Thickness Si-NCs_1m30s
Chapter 3
Experiment Procedures
and Electric Characteristic of Device
3.1 Device Fabrication
The schematic diagram of the fabrication process is illustrated in Fig.3-1.Three different types of tunnel oxide are grown on p-type (100) silicon substrates after RCA cleaning. (1) 3-nm thick SiO2 film was thermally grown in dry N2O atmosphere by horizontal-furnace. (2) 2.5-nm thick SiO2 film was thermally grown in dry N2O atmosphere by vertical-furnace. (3) 2.5-nm thick SiO2 film was thermally grown in dry O2 atmosphere by vertical-furnace. Then, a 3-nm thick silicon nitride films was deposited as the trapping layer in a LPCVD system using SiH2Cl2 and NH3 as source for 30 and 130 sccm, respectively. Si-NCs were formed on the silicon nitride films immediately by LPCVD for 2-min and 1-min and 30-sec. The deposition of amorphous silicon nucleation were kept at 550°C and the pressure was controlled at 100-mTorr. The flow rate of the reaction gas of SiH4 was 85-sccm. Then, the silicon nitride capped on the amorphous silicon nucleation was 4-nm. During this high temperature period, the previously deposited amorphous silicon nucleation was crystallized and then formed into poly-Si nanocrystals,, which were embedded in silicon nitride films. A blocking oxide about 20-nm was then deposited using high density plasma chemical vapor deposition (HDPCVD) oxide. A 200-nm thick poly-Si was deposited to serve as the gate electrode by LPCVD. Subsequently, the n+ poly-Si gate was formed by ion implantation of phosphorous at 40-keV to a dose of 5x1015 cm-2. The sample without Si-NCs was fabricated as a control sample.
Then, the poly-Si gate electrode and the Si-NCs trapping layer with blocking oxide were