Typical Threshold Voltage Parameter Extraction

In this section, the methodology of extracting typical parameters, such as threshold voltage from device characteristics, are briefly introduced. Plenty ways are used to determinate the threshold voltage which is the most important parameter of semiconductor devices. The method to determinate the threshold voltage in my thesis is the constant drain current method that the voltage at a specific drain current I_ONis taken as the threshold voltage.

This technique is easy and can give a threshold voltage close to that obtained by the complex linear extrapolation method. Typically, the threshold current I_ON= I_DN/ (W / L) where I_DN is a normalized drain current. Here, IDN is 100 nA and the same for all devices to extract the threshold voltage of SONOS memory.

3.3 Characteristic of Program/Erase

In this section, we will discuss the program/erase injection mechanism. In this thesis, the programming scheme is executed by using Fowler-Nordheim tunneling and channel hot electron to injection charge into the Si-NCs trapping layer. On the other hand, the erasing scheme is executed by using Band-to-Band hot holes injection [38] to combine negative charge in the trapping layer. The injection components and efficiency for different gate or drain bias and program time conditions on different size Si-NCs trapping layer device will be

discussed.

3.3.1 Program Speed

The Fowler-Nordheim tunneling hot electrons injection was employed for programming mode. Fig. 3-2 shows the transfer characteristic of fresh state and program state for Si-NCs_1m30s sample. We clearly observed that memory window is quite large. Applying V_G=20-V, a memory window about 2-V can be easily achieved for Si-NCs_1m30s sample, when program time is 1sec.The leakage current of Si-NCs_1m30s sample is low about 10^-12A.

Fig’s. 3-3 (a)-(b) exhibits program speed characteristic for different samples, when we applying gate voltage bias at 20-V. We can see that the programming time when time reaching 0.1s if the windows margin is set about 1.5-V for two cases of control sample and Si-NCs_1m30s sample. The tunnel oxide of 3-nm was grown in dry N2O by horizontal-furnace. For the same gate voltage bias, that different tunnel oxide film is increased does obviously improve program speed. Summary for program window of different tunnel oxide film when V_G=20-V and stress 1-sec. The program window of Si-NCs_1m30s is larger for control sample in Table 3-1.

The channel hot electron injection was employed for programming mode. Fig’s. 3-4 (a)-(c) exhibits program speed characteristic for different programming conditions. We changed drain voltage bias and gate voltage bias with 5-V, 6-V and 7-V to measure program speed. We can see that the programming time can be as short as 10-μs if the windows margin is set about 1-V with V_G=6-V, V_D=6-V. For all cases, we use three kind of drain voltage bias for strong and weak drain avalanche. It can be clearly seen that larger drain bias induced strong drain avalanche makes faster program speed. On the other hand, we use three kind of the gate bias for strong and weak vertical field to hot electrons for injected into the trapping layer so the influence of increased gate voltage is conspicuous. According to all of the above, we can clearly observe that channel hot electron injection can improve injection efficiency and get faster program speed.

3.3.2 Erase Speed

Fig’s. 3-5 (a)-(c) shows erase speed characteristic for different erasing conditions. We changed gate voltage bias with -8-V, -9-V and -10V to measure erase speed for fixed 7-V drain voltage bias. We can see that erasing time can be as short as μs in order to combine negative charge in the trapping layer. The increased gate bias does not obviously accelerate erase speed. The erase speed of different gate bias is almost the same. Fig’s. 3-6 (a)-(c) exhibits erase speed characteristic when we changed drain voltage bias with 6-V, 7-V and 8-V to measure erase speed for fixed -9-V gate voltage bias.

In conclusion, show summary for erase Vt shift of 1s erase time, and compared at fixed V_G=-9-V for all cases of different V_D. The gate bias supplies only a vertical field to collect hot holes for combined negative charge in the trapping layer so the influence of increased gate voltage is not obvious. On the other hand, for all cases, we use three kind of drain voltage bias for strong and weak impact ionization at depletion of drain-side. It can be clearly seen that larger drain bias induced strong impact ionization makes faster erase speed. According to all of the above, we can clearly observe that SONOS memory with Si-NCs trapping layer has very higher hot holes injection efficiency and faster erase speed.

3.4 Characteristic of Retention

3.4.1 Characteristic of Retention for Different Temperature

Data retention is an important reliability issue of SONOS memories. In general, retention device of SONOS memories has to be checked by using accelerated test that usually adopts high electric fields and high temperature [33]. In this section, we will discuss data retention for device after programming with different temperature. The flash memory cells are required the charge for 100,000 seconds to be kept. Timing is known to cause fairly uniform wear-out of cell performance due to the oxide damage.

Fig’s. 3-7 (a)-(c) show retention characteristic of different temperature for △V_t=2-V.

The tunnel oxide of 3-nm was grown in dry N2O by horizontal-furnace. Fig’s. 3-8 (a)-(c) exhibit retention characteristic of different temperature for △V_t=2-V. The tunnel oxide of 2.5-nm was grown in dry N2O by vertical-furnace. And Fig’s. 3-9 (a)-(c) show retention characteristic of different temperature for △V_t=2-V. The tunnel oxide of 2.5-nm was grown in dry O2 by vertical-furnace. We can clearly see that the memory window narrows to about 1.8-V after 10⁴ seconds for all samples. But there is worse retention at the high temperature.

3.4.2 Characteristic of Retention for Different Si-NCs Sizes

In this section, we will discuss data retention for device after programming with different Si-NCs sizes. In general, the flash memory cells are required to keep the charge for 100,000 seconds. Timing is known to cause fairly uniform wear-out of cell performance due to the oxide damage.

Fig’s. 3-10 (a)-(c) show retention characteristic of different Si-NCs sizes for △V_t=2-V at different temperature. The tunnel oxide of 3-nm was grown in dry N2O by horizontal-furnace. Fig’s. 3-11 (a)-(c) exhibit retention characteristic of different Si-NCs sizes for △Vt=2-V at different temperature. The tunnel oxide of 2.5-nm was grown in dry N2O by vertical-furnace. And Fig’s. 3-12 (a)-(c) show retention characteristic of different Si-NCs sizes for △Vt=2-V at different temperature. The tunnel oxide of 2.5-nm was grown dry O2 by vertical-furnace. The memory window narrows to about 2-V after 10⁴ seconds for all samples.

We can clearly see that the best data retention is Si-NCs_1-min and 30-s sample at each temperature.

3.4.3 Characteristic of Retention for Different Tunnel Oxide

In this section, we will discuss data retention for device after programming with different tunnel oxide. In general, the flash memory cells are required to keep the charge for 100,000 seconds. Timing is known to cause fairly uniform wear-out of cell performance due to the oxide damage.

Fig’s. 3-13 (a)-(c) show retention characteristic of different tunnel oxide thickness for

△Vt=2-V at T=25°C. Fig’s. 3-14 (a)-(c) exhibit retention characteristic of different tunnel oxide thickness for △ V_t=2-V at T=150°C. And Fig’s. 3-15 (a)-(c) show retention characteristic of different tunnel oxide thickness for △Vt=2-V at T=250°C. The memory window narrows to about 2-V after 10⁴ seconds for all samples. We can clearly see that the best data retention is tunnel oxide of 3-nm in dry N2O by horizontal-furnace. This charge loss is due to the poor quality of tunnel oxide which results in many leakage current path.

3.4.4 Characteristic of Retention for Different Program Window

In this section, we will discuss data retention for device after programming with different program window. The flash memory cells are required the charge for 100,000 seconds to be kept. Timing is known to cause fairly uniform wear-out of cell performance due to the oxide damage.

Fig’s. 3-16 (a)-(c) show retention characteristic of different program window at T=25°C.

The tunnel oxide of 3-nm was grown in dry N2O by horizontal-furnace. Fig’s. 3-17(a)-(c) exhibit retention characteristic of different program window at T=150°C. The tunnel oxide of 3-nm was grown in dry N2O by horizontal-furnace. And Fig’s. 3-18 (a)-(c) show retention characteristic of different program window at T=250°C. The tunnel oxide of 3-nm was grown in dry N2O by horizontal-furnace. The memory window narrows to about △Vt=1.5-V after ten years for all samples. We observed larger charge loss percentage for ten years when using accelerated test at the high state.