Chapter 3 Experiment Procedures and Electric Characteristic of Device
3.5 Characteristics of Disturbance
The first failure phenomenon, called program disturbance, often takes place under the electric stress applied to those neighboring un-programmed cells during programming a specific cell in the array. Two types of program disturbance, gate (word-line) disturbance and drain (bit-line) disturbance need be considered. The schematic circuitry of the memory array is shown in Fig. 3-19. During programming cell A, gate disturbance occurs in the cell B and
the same for those cells connected with the same with word-line because the gate stress is applied to the same word-line. This is called gate disturbance. During programming cell A, drain disturbance occurs in the cell C and the same for those cells connected with the same with bit-line because the drain stress is applied to the same bit-line. This is called drain disturbance. For the cell reading, the unwanted electron injection would happen while the word-line voltage and bit-line voltage are under read operation. This phenomenon would result in a significant threshold voltage of the selected cell. This is called read disturbance [39].
Fig. 3-20 shows programming gate disturbance characteristic of device with VG=6-V for control, Si-NCs_1m30s and Si-NCs_2min, respectively. The Vt shift of gate disturbance is lower than 0.1-V for 1000s stress with VG=6-V. And Fig. 3-21 exhibits programming gate disturbance characteristic of device with VG=8-V for control, Si-NCs_1m30s and Si-NCs_2min, respectively. The Vt shift of gate disturbance can also be controlled lower than 0.4V for 1000s stress with VG=8-V. After gate electrical stress applied for a long time, it resulted in threshold voltage arising. We proposed due to bad quality of blocking oxide result in the electrons gate injection.
And Fig. 3-22 shows drain disturbance characteristic of device with VD=6-V for control, Si-NCs_1m30s and Si-NCs_2min, respectively. The Vt shift of drain disturbance is lower than 0.04-V at the worse condition of 1000sec stress. Fig. 3-23 exhibits drain disturbance characteristic of device with VD=7-V for control, Si-NCs_1m30s and Si-NCs_2min, respectively. The Vt shift of drain disturbance is lower than 0.1-V at the worse condition of 1000sec stress. After drain electrical stress applied a long time, it resulted in a increase of threshold voltage. It might be due to two factors: The first is due to poor quality of blocking and tunnel oxide result in the gate injection. The other is due to that drain electrical stress applied along long time resulted in the traps and interface states generated at drain-side, and sub-threshold swing became larger.
P-Well Formation
LOCOS Formation
Gate Oxide Formation
1. Dry N2O Oxide 3nm by Horizontal-Furnace 2. Dry Oxide 2.5nm by Vertical Furnace
a.N2O b.O2
Trapping Layer Formation:
1. Nitride: 3nm at 780°C 2. a-Si: 2min / 1m30s at 550°C 3. Nitride : 4nm at 780°C HDPCVD Oxide 20nm as Blocking Oxide
Gate Oxide Formation
1. Dry N2O Oxide 3nm by Horizontal-Furnace 2. Dry Oxide 2.5nm by Vertical Furnace
a.N2O b.O2
Trapping Layer Formation:
1. Nitride: 3nm at 780°C 2. a-Si: 2min / 1m30s at 550°C 3. Nitride : 4nm at 780°C HDPCVD Oxide 20nm as Blocking Oxide
Gate Pattern Defined
Source/Drain was implanted As and Dopant Activation
Deposited Poly-Si 200nm as Gate Layer and n+implantation
Deposited Poly-Si 200nm as Gate Layer and n+implantation
Gate Pattern Defined
Source/Drain was implanted As and Dopant Activation
Fig. 3-1 Process flows of Si-NCs SONOS memory. After dopant activation, eposited 400nm passivation oxide, and metallization, we had finished device d
fabrication. During the nitride deposition step, the Si-NCs trapping layer was crystallized and Si-NCs embedded in Si3N4 were formed.
Fig. 3-2 30s
samp time
Transfer characteristic of fresh state and program state for Si-NCs_1m le. A memory window about 2.5V can be easily achieved, when program is 1sec. The leakage current of Si-NCs_1m30s sample is about 10-12A.
(a)
Fig. 3-3
20V and tunnel oxide by dry N2O 3nm horizontal-furnace. The programming time
Table 3-1 Summary for program window of different tunnel oxide film when VG=20V and stress 1sec. The program window of Si-NCs_1m30s is larger for
0
Program speed characteristic for different sample. This gate voltage bias is be 1s if the windows margin is set about 3V with VG=20V for control sample.(a) control sample and (b) Si-NCs_1m30s sample.
control sample.
Program Window for 1s at V =20VG
5
Program Window for 1s at V =20VG
5
0 2 4 6 8 10
(a)
(b) Program Speed Tunnel Oxide O2 2.5nm Control Sample
Program Time ( sec ) VG=5V,VD=5V
V t shift ( V )
VG=6V,VD=6V VG=7V,VD=7V
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
0 2 4 6 8
10 Program Speed Tunnel Oxide O2 2.5nm Si-NCs_2min
Program Time ( sec ) VG=5V,VD=5V
VG=6V,VD=6V
V t shift ( V ) VG=7V,VD=7V
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
0
Program speed characteristic for different programming conditions at Fig. 3-4
different VG and VD. The programming time can be as short as 10μs if the windows margin is set about 1V with VG=6V, VD=6V. This tunnel oxide is dry O2 2.5nm vertical-furnace. (a) control sample, (b) Si-NCs_2min sample and (c) Si-NCs_1m30s sample.
Fig. 3-5 Erase speed characteristic for different erasing conditions at VD=7V and different VG. The erasing time can be as short as μs order. This tunnel oxide is dry Si-NCs_1m30s sample.
(b)
(c)
O2 2.5nm vertical-furnace. (a) control sample, (b) Si-NCs_2min sample and (c) Erase Speed
1
Fig. 3-6 and
diff D
O2 2.5nm vertical-furnace. (a) control ple, (b) Si-NCs_2min sample and (c) (c)
Erase speed characteristic for different erasing conditions at VG=-9V erent V . The erasing time can be as short as μs order. This tunnel oxide is dry
sam
trol sam
is dry N2O 3nm by horizontal-furnace.
(b)
(c)
Fig. 3-7 Data retention characteristic of different sample for △Vt=2V. (a) con ple, (b) Si-NCs_2min sample and (c) Si-NCs_1m30s sample. The tunnel oxide
Retention
(a)
(b) Retention
Different Temperature Tunnel Oxide N2O 2.5nm Program ΔVt : 2V Tunnel Oxide N2O 2.5nm Program ΔVt : 2V
Fig. 3-8 trol samp
is dry N
(c)
Data retention characteristic of different sample for △Vt=2V. (a) con le, (b) Si-NCs_2min sample and (c) Si-NCs_1m30s sample. The tunnel oxide
2O 2.5nm by vertical-furnace.
(a) Retention
Different Temperature Tunnel Oxide N2O 2.5nm Program ΔVt : 2V
Fig. 3-9 trol samp
is dry O
(b)
(c)
Data retention characteristic of different sample for △Vt=2V. (a) con le, (b) Si-NCs_2min sample and (c) Si-NCs_1m30s sample. The tunnel oxide
2 2.5nm by vertical-furnace.
Retention
(a)
(b) Retention@25oC Tunnel Oxide_N2O 3nm Program ΔVt : 2V
Time ( sec )
0.00
100 101 102 103 104
-0.30 -0.25 -0.20 -0.15 -0.10 -0.05
ΔV t shift ( V )
control Si-NCs_2min Si-NCs_1m30s
Retention@150oC Tunnel Oxide_N2O 3nm Program ΔVt : 2V
Time ( sec )
100 101 102 103 104
-0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00
ΔV t shift ( V )
control
Si-NCs_2min Si-NCs_1m30s
Fig. 3-10 3nm by
horizon 50℃
and (c)
(c)
Data retention characteristic of different temperature for dry N2O tal-furnace when programming △Vt=2V. (a) At T=25℃, (b) At T=1 At T=250℃.
(a) Retention@250oC Tunnel Oxide_N2O 3nm Program ΔVt : 2V Tunnel Oxide N2O 2.5nm Program ΔVt : 2V
Fig. 3-1 nm by and (c) At
(b)
(c)
1 Data retention characteristic of different temperature for dry N2O 2.5 vertical-furnace when programming △Vt=2V. (a) At T=25℃, (b) At T=150℃
T=250℃.
Retention@150oC Tunnel Oxide N2O 2.5nm Program ΔVt : 2V Tunnel Oxide N2O 2.5nm Program ΔVt : 2V
(a)
(b) Retention@25oC Tunnel Oxide O2 2.5nm Program ΔVt : 2V
Time ( sec )
100 101 102 103 104
-0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00
ΔV t shift ( V )
control
Si-NCs_2min Si-NCs_1m30s
Retention@150oC Tunnel Oxide O2 2.5nm Program ΔVt : 2V
Time ( sec )
100 101 102 103 104
-0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00
ΔV t shift ( V )
control
Si-NCs_2min Si-NCs_1m30s
Fig. 3-12 5nm by and (c) At
(c)
Data retention characteristic of different temperature for dry O2 2.
vertical-furnace when programming △Vt=2V. (a) At T=25℃, (b) At T=150℃
T=250℃.
Different Tunnel Oxide Thickness Control Sample
oxide in sam
(b)
(c)
Fig. 3-13 Data retention characteristic of different sample for different tunnel film when programming △Vt=2V at T=25℃. (a) control sample, (b) Si-NCs_2m
ple and (c) Si-NCs_1m30s sample.
Retention@25oC
Different Tunnel Oxide Thickness Si-NCs_1m30s
Different Tunnel Oxide Thickness Si-NCs_2min
(a)
(b) Retention@150oC
Different Tunnel Oxide Thickness Control Sample
Different Tunnel Oxide Thickness Si-NCs_2min
oxide le, (b) (c)
Fig. 3-14 Data retention characteristic of different sample for different tunnel film when programming △ Vt=2V at T=150 ℃ . (a) control samp Si-NCs_2min sample and (c) Si-NCs_1m30s sample.
(a) Retention@250oC
Different Tunnel Oxide Thickness Control Sample
Different Tunnel Oxide Thickness Si-NCs_1m30s
Program ΔVt : 2V
N2O 2.5nm O2 2.5nm
Fig. 3-15 oxide le, (b) (b)
(c)
Data retention characteristic of different sample for different tunnel film when programming △ Vt=2V at T=250 ℃ . (a) control samp Si-NCs_2min sample and (c) Si-NCs_1m30s sample.
Time ( sec )
Different Tunnel Oxide Thickness Si-NCs_1m30s
Different Tunnel Oxide Thickness Si-NCs_2min
Program ΔVt : 2V
N2O 2.5nm O2 2.5nm
(a) 6
(b) Retention@25oC Tunnel Oxide_N2O 3nm Control Sample
Time ( sec )
100 101 102 103 104 105 106 107 108 109 0
1 2 3 4 5
ΔV t ( V )
Retention@25oC Tunnel Oxide_N2 nm Si-NCs_2min
Time ( sec ) O 3
100 101 102 103 104 105 106 107 108 109 0
1 2 3 4 5 6
ΔV t ( V )
Fig. 3-16 O 3nm ple and (c) Si-NCs_1m
(c)
Data retention characteristic of high state and low state for dry N2 by horizontal-furnace at T=25℃. (a) control sample, (b) Si-NCs_2min sam
30s sample.
(a) Retention@25oC Tunnel Oxide_N2O 3nm Si-NCs_1m30s
Time ( sec )
100 101 102 103 104 105 106 107 108 109 0
1 2 3 4 5 6
ΔV t ( V )
Retention@150oC Tunnel Oxide_N2O 3nm Control Sample
Time(sec)
100 101 102 103 104 105 106 107 108 109 0
1 2 3 4 5 6
ΔV t ( V )
Fig. 3-17 O 3nm ple and (c) Si-NCs_1m
(b)
(c)
Data retention characteristic of high state and low state for dry N2 by horizontal-furnace at T=150℃. (a) control sample, (b) Si-NCs_2min sam
30s sample.
Retention@150oC Tunnel Oxide_N2 nm Si-NCs_2min Tunnel Oxide_N2 nm Si-NCs_1m30s
6
(a)
(b) Retention@250oC Tunnel Oxide_N2O 3nm Control Sample
Time(sec)
100 101 102 103 104 105 106 107 108 109 0
1 2 3 4 5
ΔV t ( V )
Retention@250oC Tunnel Oxide_N2O 3nm Si-NCs_2min
Time(sec)
100 101 102 103 104 105 106 107 108 109 0
1 2 3 4 5 6
ΔV t ( V )
Fig. 3-18 O 3nm ple and (c) Si-NCs_1m30s sample.
(c)
Data retention characteristic of high state and low state for dry N2 by horizontal-furnace at T=250℃. (a) control sample, (b) Si-NCs_2min sam
Fig. 3-19 During Cell A is programmed, the gate disturbance takes place in Cell B and the drain disturbance takes place in Cell C.
Retention@25
Tunnel Oxide_N2O 3nm Si-NCs_1m30s
Time(sec) 0oC
100 101 102 103 104 105 106 107 108 109 0
1 2 3 4 5 6
ΔV t ( V )
Cell A
Cell C:Drain disturbance Cell B:Gate disturbance
Cell A Cell A
Cell B:Gate disturbance
Cell C:Drain disturbance
Fig. 3-20 Programming gate disturbance characteristic of different sample at VG=6V.
This gate length and width are 0.4μm and 10μm. The tunnel oxide is dry O 2.5nm s
2
by vertical-furnace. The Vt shift of gate disturbance is lower than 0.1V for 1000 stress with VG=6V.
Fig. 3-21 Programming gate disturbance characteristic of different sample at VG=7V.
This gate length and width are 0.4μm and 10μm. The tunnel oxide is dry O2 2.5nm by vertical-furnace. The Vt shift of gate disturbance is lower than 0.4V for 1000s stress with VG=7V.
Gate Disturbance Tunnel Oxide_N2O 3nm VG = 6V VD = 0V Tunnel Oxide_N2O 3nm VG = 7V VD = 0V
Fig. 3-22 Drain disturbance characteristic of different sample at VD=6V. This gate length and width are 0.4μm and 10μm. The tunnel oxide is dry O2 2.5nm by vertical-furnace. The Vt shift of drain disturbance is lower than 0.04V at the worse condition of 1000sec stress.
Fig. 3-23 Drain disturbance characteristic of different sample at VD=7V. This gate length and width are 0.4μm and 10μm. The tunnel oxide is dry O2 2.5nm by vertical-furnace. The Vt shift of drain disturbance is lower than 0.1V at the worse condition of 1000sec stress.
Drain Disturbance
Chapter 4 Conclusions
In this thesis, we have studied embedded Si-NCs in Si3N4 of SONOS memories device application. We have successfully demonstrated the feasibility of fabricating embedded Si-NCs in Si3N4 of SONOS memories with excellent characteristics. The size of Si-NCs can be easily controlled by deposition time.
For the program window, Si-NCs SONOS memories has more trapping sites than conventional SONOS memory. The program window of Si-NCs is larger for control sample.
And the larger Si-NCs size has larger trapping sites size similar to floating gate, so the memory window of Si-NCs_2min is larger than Si-NCs_1m30s memory window. For the different tunnel oxide film, dry N2O 2.5-nm by vertical-furnace and dry O2 2.5-nm by vertical-furnace of memory have thinner thickness than dry N2O 3-nm by horizontal-furnace of memory. The program window of thinner tunneling oxide is larger for tunneling oxide of dry N2O 3-nm by horizontal-furnace.
For the data retention, thermionic emission, direct tunneling and trap-to-trap tunneling, in relating to the data loss, are the three dominant leakage components. The reduction of the programmed flat band voltage is due to trap generation in the oxide and also interface state generation between tunnel oxide and channel interface, which are usually called electron degradations. In our device, the Si-NCs memory window still maintains quite about 2-V even through stressed for 104 seconds.
At temperature T=25oC, T=85oC and T=150oC, all cases presented good retention characteristics but charge loss is serious for control sample than Si-NCs of capacitor sample at high temperature. Program windows can maintain 1.9-V at 25℃. We can find that will make our data retention drop at high temperature. Due to thermionic tunneling is violent at high temperature. So program window has been reduced to 1.5-V. This also shows that the
trapping capability of Si-NCs trapping layer is very excellent. On the other hand, we observed larger charge loss percentage for ten years when using accelerated test at temperature T=250oC. This charge loss is due to the poor quality of tunnel oxide which results in many leakage current paths.
For different tunnel oxides, all cases presented good retention characteristics but charge loss is serious for tunnel oxide by dry O2 2.5-nm than N2O 2.5-nm and 3-nm sample. This also shows that the quality of tunnel oxide of 3-nm grown by dry N2O is very excellent. On the other hand, we observed larger charge loss percentage for ten years when using accelerated test for tunnel oxide of 2.5-nm grown in dry O2 sample. Based on the all above result, we know the quality of dry N2O 3-nm by horizontal-furnace is better than that of dry O2 2.5-nm by vertical-furnace. We find tunnel oxide that utilizing dry N2O 3-nm by horizontal-furnace will be performance of reliability. Because the thickness that horizontal-furnace grows is thicker. And the quality that horizontal-furnace grows is better.
In conclusion, according to our research we have demonstrated that embedded Si-NCs in nitride for SONOS memories have faster program and erase speed, lower operation voltage for scaled device, and multi-level per one memory cell. If we can improve the quality of blocking oxide in order to promote the erase speed and reliability, we believed this embedded Si-NCs in nitride for SONOS memories are very promising for the future flash memory application.
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作者簡介
姓名：劉美君
性別：女
出生地：台灣省新竹市
出生地：台灣省新竹市