Chapter 1 Introduction
1.2 Organization of the Thesis
The organization of this thesis consists of six chapters. After a brief introduction in Chapter 1, we will introduce the experimental devices and experimental setup in Chapter 2, which includes the operating schemes, program and erase, and the measuring method of charge pumping. In Chapter 3, we will introduce the mechanisms of FBEI and FBHHI and we will compare the performance and reliability with different program/erase schemes. In Chapter 4, we will explain the phenomenon of charge-pumping method in planar SONOS devices, which led to a development of a new monitor, defined as A. As a consequence, we will study the different operation combinations with this new parameter area A. In Chapter 5, we will focus on the
operation in different pulse series type will be discussed. Finally, the summary will be presented in Chapter 6.
Chapter 2
Device Fabrication and Equipment Setup
2.1 Introduction
This chapter is divided into four sections. First of all, both split-gate SONOS and the conventional SONOS cells used in this study will be described. Second, the instruments setup and the experimental techniques to accurately control these instruments are illustrated. Third, we will discuss the new programming and erasing schemes of these cells. Finally, charge pumping measurement technique setup used in this study will be demonstrated.
2.2 Device Fabrication
Figure 2.1 is the schematic diagram illustrating the fabrication of split-gate SONOS. As shown in Fig. 2.1(a), a substrate is provided, and a P well is formed in the substrate. Then, a plurality of control gate structure is formed on the P well. Each control-gate structure from bottom to top includes a gate insulating layer, a control gate oxide (65Å), and a cap nitride layer. As shown in Fig. 2.1(b), a silicon oxide layer (not shown), a nitride layer (not shown) is deposited on the substrate and control gate structure, and an etching back process is then performed to form a plurality of sacrificial spacers alongside each control gate structure. Meanwhile, a plurality of opening is formed between any two adjacent sacrificial spacers to expose the P well.
Afterward, an implantation process is performed via each opening to form a plurality of N doped regions, serving as buried bit line, in the P well. As shown in Fig. 2.1(c),
composite dielectric layer is formed on the P well, the control-gate structure, and the N doped regions. In this embodiment, the composite dielectric layer is an ONO tri-layer dielectric including a bottom oxide layer (60Å), a nitride layer (90Å), and a top oxide layer (90Å). As shown in Fig. 2.1(d), a conductive layer is entirely deposited on the composite dielectric layer, and a photolithography and etching process is performed to define a plurality of parallel word line, which are perpendicular to the control-gate structure, as shown in Fig. 2.1(e) [11]. The SEM image and the 2D-TCAD simulation structure of dual-bit split-gate SONOS are shown in Fig. 2.2 (a) and Fig. 2.2 (b). The gate width is 0.2um, and the channel length is 0.18um under control-gate and three different word gate length (LWG) splits (0.13um, 0.12um, 0.10um) under the word-gate.
The conventional SONOS cell used in this study is first grown by thermal oxidation with thicknesses of 50 Å. Next, a layer of 60 Å LPCVD nitride film is grown. Finally, the LPCVD blocking oxide is grown with thickness of 50 Å.
(W/L=0.7/0.26 um)
2.3 Equipment Setup
The experimental setup for the I-V and transient characteristics measurement of SONOS is illustrated in Fig. 2.3. Based on the PC controlled instrument environment via HP-IB (GP-IB, IEEE-488 Standard) interface, the complicated and long-term characterization procedures during analyzing the intrinsic and degradation behaviors in SONOS cells can be easily achieved. As shown in Fig. 2.3, the characterization
station provides an adequate capability for measuring the device I-V characteristics and executing the SONOS cell program/erase operation.
Source-monitor units (SMU) and provided the high current resolution to 10-15A range facilitates the gate current measurement, sub-threshold characteristics extraction, and the saturation drain current measurement. The HP E5250A equipped with a 10-input (6 SMU ports and 4 AUX ports) × 12-output switching matrix, switches the signals from the HP 4156C and the HP 8110A to device under test (DUT) in probe station, automatically. In addition, the HT-Basic are used as the program languages to achieve the personal computer (PC) control of these measurement instruments.
2.4 Programming and Erasing Setup
The general programming and erasing schemes for the conventional SONOS are Channel Hot Electron Injection (CHEI) and Band-to-Band Tunneling Hot Hole Injection (BBTHHI). For CHEI programming, source and substrate are grounded, while gate and drain are connected to the pulse generator as shown in Fig. 2.4 (a). The pulse timing diagram for both gate and drain are shown in Fig.2.4 (b). For BBTHHI erasing, substrate is grounded, and gate and drain are connected to the pulse generator just like CHEI, but keeps bulk floating this time as shown in Fig. 2.5 (a). The pulse timing diagram for both gate and drain are shown in Fig.2.5 (b). The novel programming scheme and erasing scheme for the split gate SONOS are Forward Bias assisted Electron Injection (FBEI) and Forward Bias assisted Hot Hole Injection (FBHHI). For FBEI programming, source is floating and substrate is ground, while gate and drain are connected to the pulse generator as shown in Fig. 2.6 (a) The pulse
is floating and gate is grounded, while gate and substrate are connected to the pulse generator as shown in Fig. 2.7 (a). The pulse timing diagram for both gate and drain are shown in Fig.2.7 (b). The operation mechanism and relevant measurement of FBHHI will be discussed after this chapter.
Dual-bit split-gate SONOS operates as conventional does, but adding a control-gate bias in the middle of the cell. The control-gate keeps a small constant bias for programming, while floating for erasing. And the other terminals are just the same as conventional operation.
2.5 Charge Pumping Measurement Technique Setup
The charge pumping measurement technique setup is shown in Fig. 2.6, which we called fixed based charge pumping, but with minor difference from the traditional one. The pulse generator is connected to the gate, and with the substrate and drain connecting to the HP4156C, while source is kept floating. Fig. 2.8 (a) shows the pulse series type sending out from the pulse generator used by this setup. By using this setup, we can measure the charge pumping current from drain. If one wants to measure the charge pumping from drain (/source), we should connect the HP4156C with them and open the source (/drain) to get the information of the charge pumping current. The second scheme for charge pumping measurement technique setup is shown in Fig. 2.8 once again. However, the pulse series type is different this time. As shown in Fig. 2.8 (b), we used likely the traditional fixed top charge pumping pulse series to do our measurement.
(a)
(b)
Fig. 2.1 The schematic diagram illustrating of forming the dual-bit split-gate SONOS.
(c)
(d)
Fig. 2.1 The schematic diagram illustrating of forming the dual-bit split-gate SONOS.
(e)
Fig. 2.1 The schematic diagram illustrating of forming the dual-bit split-gate SONOS.
(a)
(b)
Fig. 2.2 (a) The SEM image and (b) the simulation structure of the dual-bit split-gate SONOS.
Fig. 2.3 The experimental setup of the current-voltage and the transient characteristics measurement. An automatic controlled characterization system is setup based on the PC controlled instrument environment.
01000
Probe Station Personal Computer
HP 81110A Pulse Generator
Parameter Analyzer HP 4156C
Switch Matrix HP 5250 A
(a)
(b)
Fig. 2.4 (a) The operation scheme and (b) timing diagram for CHEI program.
S D
VG: pulse
VD: pulse BOX
TOX Nitride
P-sub Poly-Gate
(a)
(b)
Fig. 2.5 (a) The operation scheme and (b) timing diagram for BTBHHI erase.
S D
VG: pulse
VD: pulse
BOX TOX
Nitride VS: floating
P-sub Poly-Gate
(a)
(b)
Fig. 2.6 (a) The operation scheme and (b) timing diagram for FBEI program.
S D
VG: pulse
VD: pulse
BOX
TOX
Nitride VS: floating
P-sub Poly-Gate
(a)
(b)
Fig. 2.7 (a) The operation scheme and (b) timing diagram for FBHHI erase.
S D
VG: pulse
VD: pulse
BOX
TOX
Nitride VS: floating
P-sub Poly-Gate
(a)
(b)
Fig. 2.8 The operation scheme for charge pumping with (a) fixed base pulse series measurement and (b) fixed top sketch.
S D
VG: pulse
VD: Icp,d
BOX TOX Nitride VS: floating
P-sub Poly-Gate
(or Icp,s) (or floating)
S D
VG: pulse
VD: Icp,d
BOX TOX Nitride VS: floating
P-sub Poly-Gate
(or Icp,s) (or floating)
Chapter 3
A Novel Operating Scheme and Properties of Split-Gate SONOS
3.1 Introduction
In chapter 3, we will propose a new mode of pulse operation to compete with the conventional operation scheme in split-gate SONOS. A novel operation concept used the multi-cycle pulse series and suitable forward-bias to enhance the efficiency of program/erase. Finally, several cell reliability issues by using the new operation scheme, such as forward-bias current disturbance, transient, endurance, and stress induced leakage current will be discuss in this chapter.
3.2 Basic Mechanism and Optimized Bias Condition of the Novel Operation Scheme
3.2.1 The Operating Mechanisms of FBEI and FBHHI
First, two modes of pulse operation are shown in Fig. 3.1, in which Fig. 3.1(a) shows the typical unit-pulse for conventional operation scheme, e.g., SSI or BTBHHI etc., and Fig. 3.1(b) shows a multi-cycle pulse series for new operation scheme, e.g., FBEI or FBHHI. In Fig. 3.1(b), the drain voltage was negative in 0 state, in which p-n+ diode was forward-biased to generate lots of carriers for increasing operating
floating, during emitting phase T1, the drain/bulk was forward biased and electrons were injected into the bulk. Subsequently, at T2, the junction was reverse biased which will cause the previously injected electrons in the bulk to be accelerated across the depletion region and injected into the gate oxide.
FBHHI erase is shown in Fig. 3.2(b), substrate was grounded, while gate and drain bias used multi-cycle pulse series. Erase speed decays, for the pulse structure in Fig. 3.2(a), due to the trapping holes at the bottom oxide which leads to a decreasing FN field. The different emitting time T2 can compensate the degradation of erase speed. During T1, a large number of holes were injected into the drain side. Above all, we will get higher density of holes to enhance erase speed and keep the better quality of bottom oxide than that of BTBHHI erase (will be discussed in the next chapter).
3.2.2 Optimized V
highand V
lowof FBEI Program
Figure 3.3 shows the characteristics of FBEI as a function of VD,low for a VG=6.5V. We found that the ∆Vth have a peak value at VD,low= -2V and it will not be increased even if it is less than -2V. A suitable forward-bias is used to generate programming electron rather than to accelerate electron speed. Fig. 3.4(a) shows that a VD,high of over 5.5V is required for optimized injection voltage, due to the fact that hot electrons must surmount the ∆Ec of the Si/SiO2 interface (~3.1eV). The threshold voltage shift decreases when the voltage is over 5.5V, since the lateral electric field is larger than the vertical electric field. In Fig. 3.4(b), the ∆Vth was increased with raising VG. By using these optimized voltages, we can achieve an efficient operation
3.2.3 Optimized V
D,lowof FBHHI Erase
Figure 3.5 shows the characteristics of FBHHI as a function of VD,low. The shift in the threshold voltage was saturated against increases in the forward-bias. Because the holes accumulated in the n+ drain will be recombined with electrons. Therefore, it is no useful by adding too large forward-bias at p-n+ diode and larger forward current will cause lots of reliability issues [12].
3.2.4 Program/Erase Transient for Different Modes of Operation
The programming speed of SSI and FBEI are compared in Fig. 3.6, which reveals that the new scheme, FBEI, achieving a faster programming speed and low voltage. In Fig. 3.7, it shows the most noticeable result in that the erase speed was greatly increased when Vhigh of drain voltage are 4V and 5V, respectively, and the low voltage of VD was set at -2V. We understood that the larger Vhigh of drain voltage made more serious band bending to generate lots of band-to-band tunneling hot holes [4]. From the result of erase transient, we can estimate that the number of erasing hole by using forward-bias -2V at p-n+ diode is larger than that by using reverse-bias drain voltage 4V and 5V and are comparable when the drain diode is reverse-biased at 6V.
Generally, it induces lots of hot holes by using a slight forward-bias, even if the Vhigh
is too low. We know the large reverse-bias will stress the PN junction and a huge current also made the problem of circuit design and junction breakdown [13]. In the next section, we will discuss the reliability issue of FBHHI and BTBHHI erase.
3.3 Reliability for Non-Cycled Split-Gate SONOS
3.3.1 Operating Mode of P-N+ Diode
Figure 3.8 shows two different modes of measurement scale. On the left hand side of Fig. 3.8, the drain current as a function of the negative drain voltage for the VG= 0V and VD was varied from 0V to -3V. This bias condition was be used to realize the current of T1 phase in FBHHI erase and we got ID= 3.15 uA, while the forward-bias is -2V. In contrast, the right hand side of Fig. 3.8 shows the drain current of T2 phase which is a function of the positive drain current and VD was swept from 0V to 6V, the bias condition is equal to BTBHHI erase. The ID is only near 10 nA even if VD= 6V, so we can compare the currents from different operating modes to feel the benefits of FBHHI.
3.3.2 The Comparison with FBHHI and BTBHHI Erase
We have known that FBHHI has a better erase speed and enough erasing holes even if at low drain bias. By using multi-cycle pulse series, it only used a half of erase time (Fig. 3.9) to stress high voltage on the cell and remaining time is be used to generate the operating carriers. As a consequence, multi-cycle pulse series can enhance the operating speed and reduce the stress time because the mechanism of generated carriers in Fig. 3.10 are far away from the SiO2/Si interface while we forward-bias the current at p-n+ diode. At T2 phase of FBHHI, we set the drain and gate voltages equal to BTBHHI erase, then it is easy to compare the results with two kinds of pulse series. Above all, we have successfully achieved that hole stress time
3.3.3 Reliability for FBHHI
A large drain current will induce some problems about junction leakage or breakdown, but Fig. 3.11 will solve the concern about forward-bias current. We attempted to stress device under a long-term forward mode on the p-n+ diode. The result in Fig. 3.11 exhibits the stable value of leakage current and threshold voltage at VD= -2V, even if it is until a thousand seconds. Generally, a suitable diode current will not destroy the implant p-n+ junction and will not cause an increase of the leakage current through the diode. In other words, threshold voltage was not disturbed while the drain voltage is negative and the storage node was not be erased at T1 phase.
In chapter 4, we will discuss the oxide degradation and interface traps under different erase conditions. It shows that FBHHHI erase can reduce the oxide decay. In [14], the positive oxide charge assisted tunneling was dominated to be a serious SILC in a hot hole stressed cell. We estimated the negative bias at T2 phase can annihilate the positive oxide charge at the bottom oxide and reduce the SILC.[15]
Fig. 3.1 (a) The conventional unit-cycle pulse series for CHEI or BTBHHI.
(b) The multi-cycle pulse series for FBEI or FBHHI.
(a)
(b)
Fig. 3.2 The operation scheme and timing diagram for (a) FBEI program and (b) FBHHI erase. The FBEI pulse series were combined with the same pulse width, but the FBHHI series used a varying pulse width.
Fig. 3.3 The characteristics of FBEI as a function of VD,low
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Threshold voltage shift,∆∆∆∆V th (V)
V
D,low(V)
V
D,high=4.5V,V
G
=6.5V
Period=1us
Pulse width=10ns Tr=T
f=10ns
(a)
(b)
Fig. 3.4 (a) The characteristics of FBEI as a function of VD,high
(b) The characteristics of FBEI as a function of VG
Throshold voltage shift,∆∆∆∆V th(V)
V
D,high(V)
Throshold voltage shift,∆∆∆∆V th(V)
V
G(V) V
D,low=-2V,V
D,high
=5.5V
Fig. 3.5 The characteristics of FBHHI as a function of VD,low
-5 -4 -3 -2 -1 0
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
Period=0.1ms
Pulse width=0.1us~10us T
r=T
f
=10ns
Threshold voltage shift,∆∆∆∆V th(V)V
D,lowFBHHI V
G
=-6V,V
D,high
=5V
Fig. 3.6 The programming transient of SSI and FBEI programs for split-gate SONOS with multi-level cell application.
FBEI VG=6.5V
Threshold voltage shift,∆∆∆∆V th(V)
Program Time (S)
Dependence of Vth shift on pulse count FBEI: VD,low/VD,high= -2/5.5V SSI:VD,low/VD,high= 0/5.5V
Fig. 3.7 The erasing transient of BTBHHI and FBHHI erases for split-gate SONOS with multi-level application.
1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1 10 -6
-5 -4 -3 -2 -1 0
Threshold voltage shift,∆∆∆∆V th(V)
Erase time (S)
FBHHI VD,low/VD,high=-2/4V FBHHI VD,low/VD,high=-2/5V FBHHI VD,low/VD,high=-2/6V BTBHHI VD,low/VD,high=0/4V BTBHHI VD,low/VD,high=0/5V BTBHHI VD,low/VD,high=0/6V Used V
G =5V
Fig. 3.8 Two different modes of measurement for split-gate SONOS.
-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6
D ra in C u rr e n t ,I D ( A )
Drain Voltage,VD (V)
Fig. 3.9 By using multi-cycle pulse series, it only used a half of operating time to be stressed at high voltage and remaining time be stressed at low voltage.
Fig. 3.10 The mechanism of multi-cycle pulse series operation. The generation of carrier is far away from the channel and reduces the oxide degradation.
Fig. 3.11 The value of leakage current and threshold voltage at VD=-2V, even if it is until a thousand seconds.
10-8 10-7 10-6 10-510-4 10-3 10-210-1 100 101 102 103 104
1.0x102 1.5x102 2.0x102 2.5x102 3.0x102
Le a c k a ge C ur re nt ( p A )
Total Forward Bias Time (S)
Read:VG=0V,VD=1.8V
T h re s h o ld V o lt a g e , V th ( V )
Forward Bias V
D
=-2V
0 2 4 6 8 10
CC-Vth :I
D=56nA
Chapter 4
The Monitoring of Stored Charges and Oxide Traps in a Planar SONOS
4.1 Introduction
In this chapter, we will discuss the different operation combinations in a planar SONOS and analyze the reliability issue for a P/E cycling device using different operating schemes. We will use the charge-pumping techniques to detect the misalignment between the distribution of electrons and holes. The charge distribution profiling in charge-trapping memory have been studied by various methods of charge-pumping [8][9], but it became more inaccurate after P/E cycles. We will propose a monitor to understand the hole-electron misalignment and degradation of operation. [10]
4.2 Principle of Charge Profile by Charge Pumping Method
4.2.1 Principle of Charge Pumping Method
The charge pumping method has been widely used for hot-carrier-related reliability characterization in MOSFETs. During a typical charge pumping measurement, a pulse string is applied to the gate terminal of a MOSFET while the substrate current (commonly called the “charge pumping current”) is monitored.
the substrate when the gate is biased between flat-band and accumulation) with the trapped minority carriers at the interface (coming from the source/drain when the gate is biased to inversion), to first order the charge pumping current (Icp) is nonzero only if the high level (Vh) and the base level (Vb) of the gate pulses cover both the threshold voltage (Vt) and the flat-band voltage (Vfb) [8][16].
Unlike the conventional charge pumping (CP) method, the other two basic ways of charge pumping test to obtain the profile are demonstrated. First one is the fixed base CP (fixed base level and varying the top level) method with one side of drain (or source) floating and the other one is the fixed top CP (fixed top level and varying the base level) method with also one side of drain (or source) floating, which are defined as FVb and FVt, respectively.
In FVb CP method, the setup is shown in Fig. 2.8 (a) in chapter 2, the gate is applied with a pulse string, as shown in Fig. 2.8 (a), and the Icp can be measured from drain or source side with source or drain floating respectively. When measuring the charge pumping current Icp,d from the drain side, the minority carrier only contributed from the drain side and vice versa with Icp,s. Therefore, we can obtain more precise information about the drain and source side from Icp,d and Icp,s. By combining these two currents, we can profile the asymmetrical Vt along the channel for both virgin and programmed cells [9][18]. In FVt CP method, the setup and gate pulse are shown in Fig. 2.8(b). The equipment setup is similar to FVb CP method instead of the gate pulse string which is fixed on a constant level upon the threshold voltage.
4.2.2 Fixed Base Charge Pumping Method
Figure 4.1 (a) illustrates the Vt profile of a programmed nitride storage memory cell, which contains a narrow Vt peak near the drain side. Four regions are marked in this figure, and they are consistent with the Icp curve tested from FVb CP method in Fig. 4.1 (b). Fig. 4.1 (b) corresponds to the drain or source junction area in Fig. 4.1 (a).
After the programming, localized trapped charges enhance the threshold voltage near drain side, which forms the asymmetrical Vt profile in Fig. 4.1 (a). Therefore, the Icp,d
and Icp,s curves can be shifted toward the right, which corresponds to the regions B and C in Fig. 4.1 (b). The difference between curves B and C indicates the location and profile of the injected charges. As Fig. 4.1 (b) shows, the injection is closer to the drain side. It needs to be pointed out that Icp keeps shifting rightward in region D, indicating a Vt peak here. Moreover, Icp,d and Icp,s overlap in this region, which means
and Icp,s curves can be shifted toward the right, which corresponds to the regions B and C in Fig. 4.1 (b). The difference between curves B and C indicates the location and profile of the injected charges. As Fig. 4.1 (b) shows, the injection is closer to the drain side. It needs to be pointed out that Icp keeps shifting rightward in region D, indicating a Vt peak here. Moreover, Icp,d and Icp,s overlap in this region, which means