Applications to Two-Bit Programming Cells

characteristic of endurance, and the retention for two-bit operation. First, Fig. 5.11 shows the programming speed for first bit and second bit by SSI and FEBI program.

We found the second bit transient was decelerated on using SSI, because the electron of bit-1 increased the channel potential and reduced the electric field along the channel. So far, we understood the advantage of using multi-cycle pulse series, e.g., FBEI is the two-bit operation is mutual containment during programming by superiority of one-side operating.

In chapters 3 and 4, it has been realized that the FBHHI can reduce the oxide degradation. In order to decrease the erasing breakdown, we tried two operating combinations, FBEI/FBHHI and SSI/FBHHI, for endurance measurement. The cycle sequence is program bit-1 => program bit-2 => erase bit-2 => erase bit-1, which is the worst operating sequence [28]. Fig. 5.12 shows endurance characteristics of two-bit per cell application, using SSI program and FBHHI erase. The window of SSI/FBHHI closed gradually by second bit transient slowing down. Fig. 5.13 shows the endurance characteristics of two-bit per cell, by using FBEI program and FBHHI erase. The FBEI/FBHHI kept the window of 2V and the same ∆Vth shift on bit-1 sand bit-2.

Next, Fig. 5.14 shows retention behaviors after 10k P/E cycles of bit-1 and bit-2 in different states, respectively for split-gate SONOS with SSI and FBEI program. As we can see, FBEI has 1.6V window after ten years in Fig. 5.14 and is larger than the window (~1.4V) of SSI retention.

More importantly, the retention behavior shows the reliability of the bottom oxide, which leads to with using by multi-cycle mode, e.g. FBEI, FBHHI, less

Fig. 5.1 The schematic structure of the split-gate SONOS.

-1 0 1 2 3 4 5 6 7 8 1E-15

1E-13 1E-11 1E-9 1E-7 1E-5 1E-3

V

_WG

:Sweep V

CG

=0.9V

D ra in C u rr en t ,I

D

( A )

V

WG

I_D-V_G;Reverse Read(V_S=1.8V) I_D-V_G;Forward Read(V_D=1.8V)

Fig. 5.2 The drain current versus gate voltage under forward read and reverse read when the VCG was biased at 0.9V in a split-gate SONOS.

(a)

(b)

Fig. 5.3 (a) The threshold voltage shift with varying V_CG . (b) The ID-VG curves with different VCG conditions.

D ra in C u rr e n t ,I

D

( A )

V

WG

-0.2 -0.1 0.0 0.1 0.2 VCG=0.6V, 0.7V and 0.8V conditions at CC-Vth=56nA.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

T h re s h o ld Vo lt a g e , V

th

( V)

V

_D

(V)

Fig. 5.5 (a) The threshold voltage shift with varying VD.

(b) The negative channel potential along lateral location with

Fig. 5.6 The diagram for the forward read and reverse read modes.

Forward Read Reverse Read

Bit-1 Bit-2

V

^D

V

^S

Fig. 5.7 The window versus Vth shift of bit-1 for split-gate SONOS with LWG=0.1 and 0.13 um.

0.0 0.6 1.2 1.8 2.4 3.0

0.0 0.6 1.2 1.8 2.4 3.0

O p e rat io n W in d o w , V

TH,RR

- V

TH,FR

(V )

Threshold Voltage Shift (bit-1), _∆∆∆∆ VTH (V)

FBEI@L_WG=0.1um FBEI@L_WG=0.13um SSI@L_WG=0.1um SSI@L_WG=0.13um

V_Sor V_D=1.8V V_CG=0.9V

Read: V_WG:Sweep

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Fig. 5.8 The window for various read voltage with different ∆Vth (bit-1), using (a) SSI program and (b) FBEI program. The star symbol

0.50 0.75 1.00 1.25 1.50 1.75

0.50 0.75 1.00 1.25 1.50 1.75

0.0

Fig. 5.10 The terminals setup for sampling by Analyzer HP4156C.

V ^D V ^WG

V ^CG

ground

V ^WG

V ^D

floating

T ¹ T ²

FBEI

SSI

Fig. 5.11 The programming speed for first bit and second bit by FBEI and SSI programs.

1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1 2.5

3.0 3.5 4.0 4.5 5.0 5.5 6.0

Thr e s hold V o lta g e ,V

TH

(V )

Program Time (S)

FBEI @ First Bit transient FBEI @ Second Bit transient SSI @ First Bit transient SSI @ Second Bit transient

FBEI SSI V_G= 8.5V ; 9.5V V_D=-2~5.5V ; 5.5V

Dependence of Vth shift on bit-1

Fig. 5.12 Endurance characteristics of two-bit per cell application, using SSI program and FBHHI erase.

1 10 100 1000 10000

2.0

Fig. 5.13 Endurance characteristics of two-bit per cell application, using FBEI program and FBHHI erase.

1 10 100 1000 10000

2.5

FBEI:V

_G

=8.5V,V

_D

=-2~5.5V ,Time=100us FBHHI:V

_G

=-5V,V

_D

=-2~6V,Time=3ms

FBEI/FBHHI

10¹ 10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ 10⁸ 3.0

3.5 4.0 4.5 5.0 5.5

T h re s h o ld V o lt a g e ,V

TH

( V )

Retention Time (S) FBEI/FBHHI @ Vth

_high

FBEI/FBHHI @ Vth

_low

SSI/FBHHI @ Vth

_high

SSI/FBHHI @ Vth

_low

1.6V 1.4V

Fig. 5.14 Retention behaviors after 10k P/E of Bit-1 at Vth _high and Vth _low states with FBEI/FBHHI and SSI/FBHHI combinations.

Chapter 6

Summary and Conclusion

In this thesis, a novel operating scheme has been propose for 2-bit/cell split-gate SONOS. We proposed a new mode of pulse operation to compare it with the conventional operation scheme in split-gate SONOS. A novel operation concept used the multi-cycle pulse series and suitable forward-bias to enhance the efficiency of program/erase. The multi-cycle pulse type can achieve a superior operation efficiency, even it only needs half of time for the charge injection. The reliability for junction leakage was dominated by forward-bias stress, while it exhibits a stable value of the leakage current in the new operating scheme. Above all, threshold voltage was not disturbed with a suitable forward-bias current.

Next, we discussed the different operation combinations in planar SONOS and analyzed the reliabilities for a P/E cycling device using different operating schemes.

By calculating a new parameter ∆A/Ao, we found the multi-cycle pulse series, e.g., FBEI and FBHHI, can reduce the misalignment in the trapping memory, and by calculating ∆ICP,MAX/ICPo,MAX, FBHHI can suppress efficiently the oxide degradation in comparison to BTBHHI.

On the other hand, we did the test about the multi-cycle pulse type for two-bit per cell operation reliability in split-gate SONOS. We used the unique double-gate structures to discuss the second-bit-effect and different programming scheme induced charge distribution in the dielectric layer. FBEI could inject the electrons near the drain side, although it had wider distribution location than SSI in the nitride, but it can

keep a stable endurance window by using the FBHHI erase. More importantly, for the two-bit per cell operation, the new operating scheme exhibited much better program speed, endurance, and retention characteristics in split-gate SONOS and achieved a better alignment between the two bits.

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