Organization of the Thesis

The organization of this thesis consists of six chapters. After a brief introduction

Chapter 2, which includes the operating schemes, the program and erase schemes and the measuring method for charge pumping. In chapter 3, we will show the physical mechanism and the basic characteristics of the dual-bit split-gate SONOS. In Chapter 4, we will discuss the misalignment and retention loss model for conventional SONOS. In Chapter 5, we discuss the retention mechanism for split-gate SONOS by altering the word-gate length of the devices and demonstrate an erasing scheme for split-gate SONOS to achieve low retention loss. Finally, the conclusions will be presented in chapter 6.

Chapter 2

Device fabrication and Equipment Setup

2.1 Introduction

This chapter is divided into four sections. First of all, both split-gate SONOS and the conventional SONOS cells used in this study will be described. Second, the instruments setup and the experimental techniques to accurately control these instruments are illustrated. Third, we will discuss the programming and erasing schemes of these cells. Finally, charge pumping measurement technique setup used in this study will be demonstrated.

2.2 Device Fabrication

Figure 2.1 is the schematic diagram illustrating of forming the split-gate SONOS.

As shown in Fig. 2.1(a), a substrate is provided, and a P well is formed in the substrate. Then, a plurality of control gate structure is formed on the P well. Each control-gate structure from bottom to top includes a gate insulating layer, a control gate oxide (65Å), and a cap nitride layer. As shown in Fig. 2.1(b), a silicon oxide layer (not shown), a nitride layer (not shown) is deposited on the substrate and control gate structure, and an etching back process is then performed to form a plurality of sacrificial spacers alongside each control gate structure. Meanwhile, a plurality of opening is formed between any two adjacent sacrificial spacers to expose the P well.

Afterward, an implantation process is performed via each opening to form a plurality of N doped regions, serving as buried bit line, in the P well. As shown in Fig. 2.1(c),

composite dielectric layer is formed on the P well, the control-gate structure, and the N doped regions. In this embodiment, the composite dielectric layer is an ONO tri-layer dielectric including a bottom oxide layer (60Å), a nitride layer (90Å), and a top oxide layer (90Å). As shown in Fig. 2.1(d), a conductive layer is entirely deposited on the composite dielectric layer, and a photolithography and etching process is performed to define a plurality of parallel word line, which are perpendicular to the control-gate structure, as shown in Fig. 2.1(e) [9]. The SEM image and the 2D-TCAD simulation structure of dual-bit split-gate SONOS are shown in Fig. 2.2 (a) and Fig. 2.2 (b). The gate width is 0.2um, and the channel length is 0.18um under control-gate and three different word-length(LWG) splits (0.13um, 0.12um, 0.10um) under word-gate.

The conventional SONOS device used in this study is first grown by thermal oxidation with thicknesses of 50 Å. Next, a layer of 60 Å LPCVD nitride film is grown. Finally, the LPCVD blocking oxide is grown with thickness of 50 Å.

(W/L=0.7/0.26 um)

2.3 Equipment Setup

The experimental setup for the I-V and transient characteristics measurement of SONOS is illustrated in Fig. 2.3. Based on the PC controlled instrument environment via HP-IB (GP-IB, IEEE-488 Standard) interface, the complicated and long-term characterization procedures during analyzing the intrinsic and degradation behaviors in SONOS cells can be easily achieved. As shown in Fig. 2.2, the characterization

station provides an adequate capability for measuring the device I-V characteristics and executing the SONOS cell program/erase operation.

Source-monitor units (SMU) and provided the high current resolution to 10^-15A range facilitates the gate current measurement, sub-threshold characteristics extraction, and the saturation drain current measurement. The HP E5250A equipped with a 10-input (6 SMU ports and 4 AUX ports) × 12-output switching matrix, switches the signals from the HP 4156C and the HP 8110A to device under test (DUT) in probe station, automatically. In addition, the HT-Basic are used as the program languages to achieve the personal computer (PC) control of these measurement instruments.

2.4 Programming and Erasing Setup

The general programming and erasing schemes for the conventional SONOS are Channel Hot Electron Injection (CHEI) and Band-to-Band Tunneling Hot Hole Injection (BBTHHI). For CHEI programming, source and substrate are grounded, while gate and drain are connected to the pulse generator as shown in Fig. 2.4 (a). The pulse timing diagram for both gate and drain are shown in Fig.2.4 (b). For BBTHHI erasing, substrate is grounded, and gate and drain are connected to the pulse generator just like CHEI, but keeps bulk floating this time as shown in Fig. 2.5 (a). The pulse timing diagram for both gate and drain are shown in Fig.2.5 (b).

Another erase scheme called Substrate Transient Hot Hole Injection (STHHI) is also used in this study. For STHHI, source and drain keep floating and gate is

The operation mechanism and relevant measurement of STHHI will be discussed after this chapter.

Dual-bit split-gate SONOS operates as conventional does, but adding a control-gate bias in the middle of the cell. The control-gate keeps a small constant bias for programming, while floating for erasing. And the other terminals are just the same as conventional operation.

2.5 Charge Pumping Measurement Technique Setup

The charge pumping measurement technique setup is shown in Fig. 2.6, which we called fixed based charge pumping, but with some method unlikely the traditional one. The pulse generator is connected to the gate, and with the substrate and drain connecting to the HP4156C, while source is kept floating. Fig. 2.7 (a) shows the pulse series type sending out from the pulse generator used by this setup. By using this setup, we can measure the charge pumping current from drain. If one wants to measure the charge pumping from drain (/source), we should connect the HP4156C with them and open the source (/drain) to get the information of the charge pumping current. The second scheme for charge pumping measurement technique setup is shown in Fig. 2.7 once again. However, the pulse series type is different this time. As shown in Fig. 2.7 (b), we used likely the traditional fixed top charge pumping pulse series to do our measurement.

(a)

(b)

(a)

(b)

(e)

Fig. 2.1 The schematic diagram illustrating of forming the dual-bit split-gate SONOS.

(a)

(b)

Fig. 2.2 The SEM image (a) and the simulation structure (b) of the dual-bit split-gate

Fig. 2.3 The experimental setup of the current-voltage and the transient characteristics measurement. An automatic controlled characterization system is setup based on the PC controlled instrument environment.

01000

Probe Station Personal Computer

HP 81110A Pulse Generator

Parameter Analyzer HP 4156C

Switch Matrix HP 5250 A

(a)

(b)

Fig. 2.4 The operation scheme (a) and time diagram (b) for CHEI programming.

S D

VG: pulse

V_D: pulse B_OX

T_OX Nitride

P-sub Poly-Gate

(a)

(b)

Fig. 2.5 The operation scheme (a) and time diagram (b) for BBTHHI erasing.

S D

VG: pulse

V_D: pulse

BOX

TOX

Nitride V_S: floating

P-sub Poly-Gate

(a)

(b)

Fig. 2.6 The operation scheme (a) and time diagram (b) for STHHI erasing.

S D BOX

TOX

Nitride

VS =VD: floating

P-sub Poly-Gate

VB: pulse

(a)

(b)

Fig. 2.7 The operation scheme for charge pumping with fixed base pulse series sketch (a) and fixed top sketch (b).

S D

Chapter 3

Basic Characteristics of Dual-Bit Split-Gate SONOS

3.1 Introduction

In this chapter, first, we will introduce the basic physical mechanism of split-gate SONOS and find the optimized bias condition for both programming and erasing. Then, some reliability issues for non-cycled cell, such as gate disturbance, drain disturbance, second bit effect, and one shot retention will be discussed in this chapter.

3.2 Basic Mechanism and Optimized Bias Condition of Split-Gate SONOS

3.2.1 Source Side Injection Programming

Channel hot electron injection has been widely used as a programming mechanism in flash memory. Based on Lucky-Electron model, the programming efficiency of flash memory is evaluated with the gate current or the substrate current as the figure of merit. Source side injection has a higher programming efficiency than drain-side programming by using-split gate structure to achieve high CHE generation and optimal electron collection at the same time. As shown in Fig. 3.1, under the programming condition, the word-gate is biased at a higher potential than the drain.

that the channel electrons are accelerated in this gap region and become hot enough to inject into the ONO layer underneath the word-gate as shown in Fig. 3.2 [5, 10-11].

The drain current as a function of the control-gate voltage (VCG) for the word-gate voltage (V_WG) of 10V is shown in Fig. 3.3. The parameter was the drain voltage (VD) varied from 0.5V to 2V. This bias condition makes the channel resistance beneath the word-gate negligible small. Thus, the programming current was limited by the control-gate and is could be estimated to be 0.3uA in Fig. 3.3. Fig. 3.4 compares the drain current versus drain voltage curve between split-gate SONOS and conventional SONOS. It was found that the drain current for split-gate SONOS by using SSI is about 100~1000 times lower than conventional SONOS by using CHEI [4-5].

3.2.2 Optimized Control-Gate Voltage (VCG)

Figure 3.5 shows the simulated and measured result with different control-gate bias under programming. It shows the property bell-shape with respect to the V_CG. In split-gate SONOS memory device, the control-gate can limit the programming current, as mentioned above. This programming characteristic indicates that the control-gate can dominate not only the programming current but also the programming properties.

When a large voltage than the threshold voltage against the channel beneath the control-gate is applied to the control-gate, the potential beneath the control gate is dropped down due to the effect of the drain voltage. This potential drop induces a fall in the lateral electric field, which is a derivative of the potential, in the gap between

channel. However, when a smaller voltage then threshold voltage of the control-gate is applied to the control-gate, the drain voltage does not induce a potential drop beneath the control-gate. This indicates that the drain voltage does not induce the drop of the lateral electric field in the gap. Instead the electric field formed at the gap is high enough to inject electron, however, the control-gate shuts off the programming current. Thus, electron can not be injected, even though a high electric field is formed at the gap. Therefore, to achieve high efficiency programming operation, both the programming current and the electric field must be obtained by applying the bias condition appropriately [5-6, 10].

3.2.3 Optimized Drain Voltage (VD)

Figure 3.6 shows the simulated and measured result with different drain bias under programming. The shift in the threshold voltage was saturated against increases in the drain voltage. In the simulation result, drain voltage of over 3V does not affect the electric field at the gap except for increases the electric field at the junction.

Therefore, it is no use by adding a too large voltage at junction but a proper voltage can achieve the same efficient as large drain voltage does [5-6].

3.2.4 Programming, Erasing Transient and Readout

Figure 3.7 shows the programming (VWG= 9V, 10V, 11V VD= 4V VCG= 0.9V V_S= V_B= 0V) and erasing (V_WG= -5V V_D= 6V V_CG= V_B= 0V) transient for multi-level

different read bias conditions. It was found that, if the read voltage is not large enough (o.1V), there is no threshold voltage difference between forward read and reverse read, since the program charge can not be completely depleted or the surface potential can not be pull down. Therefore, a large reverse read voltage (1.8V) is needed for readout for this type of memory cell to suppress the potential barrier, causing a local DIBL effect that screen out the potential barrier [4-5, 12-13]. The suggestion of programming, erasing and readout bias condition is shown in table 1.1.

3.3 Reliability for Non-Cycled Split-Gate SONOS

3.3.1 Second bit Effect

Figure 3.10 shows the second bit effect of the dual-bit split-gate SONOS. It was found that the left and right bit will not interfere with the other bit, since the two storage bit position is already separated by the control-gate. And the readout voltage of 1.8V is large enough to screen out the potential barrier [13].

3.3.2 Gate and Drain Disturbance

Fig. 3.11 and Fig. 3.12 show the gate and drain disturbance of the split-gate SONOS respectively. During programming and erasing, the selected row (column) applies to a word-gate (drain) voltage. Therefore, non-selected cell will suffer from gate (drain) disturbance as shown in Fig. 3.11 (a) and Fig. 3.12 (a). Fig. 3.11 (b) and Fig. 12 (b) show that it needs a large enough word-gate voltage and long enough

3.3.3 Another Erasing Method (Positive BBTHHI Erase)

There is another erase method like drain disturbance for split-gate SONOS.

However, the erase speed for drain disturbance in Fig. 12 is too slow. Fig. 13 shows the contour plots of the potential distribution around the gap between the gates at the drain voltage of 6V. The voltage of the control-gate was small (0.9V) in Fig13 (a) and large (6V) in Fig13 (b). The potential for holes beneath the region where the electrons were trapped was lower than that around the region. It means that most of holes generated at the drain flow toward not only the substrate but also the electron trapped region. By comparing with Fig13 (a) and Fig13 (b), the potential induced by the voltage applied to the control-gate tend to spread beneath the gap by applying the higher voltage of the control-gate. This spread potential makes a path where hot holes generated at the drain region moving toward the substrate narrower than the path without the bias to the control-gate. This introduces more hot holes move toward the region where electrons are trapped than toward the substrate. Therefore, the larger positive voltage is applied to the control-gate, the more effectively the erasing operation using hot holes can be achieved without a negative bias [5].

Figure 14 shows the positive bias erasing transient with different positive bias applying to the control gate. For small positive control-gate bias (3V), most of the holes are flowing to the substrate. While large positive control-gate bias (6V), the holes are flowing into the nitride layer to achieve more efficient erase operation.

However, large control-gate bias positive BBHH erase still need more time to

3.3.4 Retention Loss

Figure 15 shows the retention loss at program state for fresh and cycled cell. It was found that there is no loss for fresh cell but not for cycled cell. It is because after cycling, the bottom oxide is heavily damaged and a large amount of holes accumulate near junction causing both vertical and lateral retention loss, which will be discussed in the following chapters in detail.

Fig. 3.1 Schematic illustration of source-side injection for split-gate structure SONOS flash memory.

pinch-off

Control-Gate Word-Gate

virtual drain

Drain

(a)

(b)

Fig. 3.2 The electric potential (a) and the normalized electric temperature (b) for split-gate SONOS during programming.

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3

Fig. 3.3 The drain current versus control-gate voltage with various drain voltage.

0 1 2 3 4

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

Id ( A )

VCG(V)

VD=0.5V

VD=1V

VD=1.5V

VD=2V

Fig. 3.4 The drain current versus drain voltage of conventional SONOS (red) and split-gate SONOS (black).

0 1 2 3 4 5

0 1x10

^-4

2x10

^-4

3x10

^-4

4x10

^-4

5x10

^-4

6x10

^-4

0

2x10

^-7

4x10

^-7

6x10

^-7

8x10

^-7

Conventional

Id (A )

VD (V)

Split-Gate

(a)

(b)

Fig. 3.5 Simulated lateral electric field versus lateral position under (a) different

0.0 0.5 1.0 1.5 2.0 2.5

Late ral Ele c tr ic Field (V/cm )

Location (um)

(a)

(b)

Fig. 3.6 Simulated lateral electric field versus lateral position under (a) different drain voltage and (b) measured programming window versus drain voltage.

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3

Latera l Ele c tric Fie ld (V/cm)

Location (um)

Fig. 3.7 The programming and erasing transient for split-gate SONOS with multi-level cell application.

10

^-7

10

^-6

10

^-5

Fig. 3.8 The drain current versus gate voltage for split-gate SONOS with multi-level application.

0 2 4 6 8

10

^-11

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

Initial State Window=1V Window=2V Window=3V

Id (A )

VG (V)

Fig. 3.9 The drain current versus gate voltage under forward read (open) and reverse read (void) for dual-bit split-gate SONOS.

0 2 4 6 8 10

SSI BBHH STHH Read V

G

9/10/11 -5 0 Sweep V

_CG

0.9 floating floating 2.1

V

_D

4 6 floating 0 V

S

0 floating floating 1.8 V

B

0 0 10-2 0

Table 1.1 Suggest bias conditions for dual-bit split-gate SONOS cell operation.

Fig. 3.10 The second-bit effect measurement for dual-bit split-gate SONOS.

0.0 0.5 1.0 1.5 2.0 2.5 3.0 2.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Vth of bit 2 (V)

Vth of bit 1 (V)

(a)

(b)

Fig. 3.11 Illustration of gate disturbance (a) and the measured gate disturbance (b) for split-gate SONOS.

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

10

¹

10

²

3.0

3.5 4.0 4.5 5.0

Vth(V)

Time(s)

VG=14V VG=13V VG=12V VG=11V

Select

VG=11,12,13,14V VB=0V VSG,VD,VSfloating

(a)

(b)

Fig. 3.12 Illustration of drain disturbance (a) and the measured drain disturbance (b)

Select

VG= floating VB=VS=0 VSG=0.9 VD=4,5,6

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

10

¹

2

3 4 5 6

Vth (V)

Time(s)

VBL=6V VBL=5V VBL=4V

(a)

(b)

Fig. 3.13 Illustrate Contour plot of potential distribution around gap between gates for a small control-gate voltage (a) and a large control-gate voltage (b).

1V

6V

6V

6V

(a)

(b)

Fig. 3.14 The positive erasing transient with different control-gate voltage (a) and

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

Fig. 3.15 The retention loss measurement for one shot fresh cell (red) and 10⁴ P/E (black) at 85C.

10

⁰

10

¹

10

²

10

³

10

⁴

-2.0 -1.5 -1.0 -0.5 0.0 0.5

Fresh cell cycled cell

Delta Vth (V)

Retention Time (s)

Chapter 4

Misalignment of Distributions and Retention Loss Mechanisms for Conventional SONOS

4.1 Introduction

In this chapter, we will discuss the misalignment between the distribution of electrons and holes and the retention mechanisms for conventional SONSO flash memory. First, we discuss the mismatch distribution by using floating S/D charge pumping method. Next, we still use charge pumping method to analyze holes migration in the nitride storage layer. Finally, we explain both vertical and lateral retention loss mechanisms.

4.2 Principle of Charge Profile by Charge Pumping Method

4.2.1 Principle of Charge Pumping Method

The charge pumping method has been widely used for hot-carrier-related reliability characterization in MOSFETs. During a typical charge pumping measurement, a pulse string is applied to the gate terminal of a MOSFET while the substrate current (commonly called the “charge pumping current”) is monitored.

Since this current is a result of the recombination of majority carriers (coming from

is biased to inversion), to first order the charge pumping current (I_cp) is nonzero only if the high level (Vh) and the base level (Vb) of the gate pulses cover both the threshold voltage and the flat-band voltage [14-15].

Unlike the conventional charge pumping (CP) method, the other two basic ways of charge pumping test to attain the profile scheme are demonstrated. First one is the fixed base CP (fixed base level and varying the top level) method with one side of drain (or source) floating and the other one is the fixed top CP (fixed top level and varying the base level) method with also one side of drain (or source) floating, which are defined as FVb and FVh, respectively.

In FVb CP method, the setup is shown in Fig. 2.5 (a) in chapter 2, the gate is applied with a pulse string, as shown in Fig. 2.5 (b), and the I_cp can be measured from drain or source side with source or drain floating respectively. When measuring the charge pumping current I_cp,d from the drain side, the minority carrier only contributed from the drain side and vice versa with Icp,s. Therefore, we can obtain more precious information about the drain and source side from I_cp,d and I_cp,s. By combining these two currents, we can profile the asymmetrical threshold voltage along the channel for both virgin and programmed cells [16-17].

4.2.2 Fixed Base Charge Pumping Method

Figure 4.1 (a) illustrates the threshold voltage profile of a programmed nitride storage memory cell, which contains a narrow threshold voltage peak near the drain

source junction area in Fig. 4.1 (a). After programming, localized trapped charges enhance the threshold voltage near drain side, which forms the asymmetrical threshold voltage profile in Fig. 4.1 (a). Therefore, the I_cp,d and I_cp,s curves shift toward the right, which corresponds to the regions B and C in Fig. 4.1 (b). The difference between curves B and C indicates the location and profile of the injected charges. As Fig. 4.1 (b) shows, the injection is closer to the drain side. It needs to be pointed out that I_cp keeps shifting rightward in region D, indicating a threshold voltage peak here. Moreover, Icp,d and Icp,s overlap in this region, which means the minority carrier coming from drain or source is passing through the peak region under the channel. For this reason, the equivalent interface traps are sensed and contribute the same I_cp,d and I_cp,s. Thus, in FV_b CP method, data obtained in region D cannot be used to extract the exact profile of threshold voltage in large current region. We can, however, extract the accurate location using this method.

4.2.3 Fixed Top Charge Pumping Method

On the other hand, the equipment setup is similar to FV_b CP method instead of the gate pulse string which is fixed on a constant level upon the threshold voltage. In contrast, the I_cp curve shift caused by the threshold voltage peak, takes place in the low current region and has higher precision in FVh CP method. Fig. 4.2 (a) illustrates I_cp test with FV_h CP method in logarithmic scale. Correspondently, region B, C and D in Fig. 4.2 (a) and Fig. 4.1 (b) also can be seen herein. Icp in region D can be used to

On the other hand, the equipment setup is similar to FV_b CP method instead of the gate pulse string which is fixed on a constant level upon the threshold voltage. In contrast, the I_cp curve shift caused by the threshold voltage peak, takes place in the low current region and has higher precision in FVh CP method. Fig. 4.2 (a) illustrates I_cp test with FV_h CP method in logarithmic scale. Correspondently, region B, C and D in Fig. 4.2 (a) and Fig. 4.1 (b) also can be seen herein. Icp in region D can be used to

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