Chapter 3 Basic Characteristics of Dual-Bit Split-Gate SONOS
4.5 Retention Loss Mechanisms
4.4.1 Retention Loss Mechanisms for Conventional SONOS
Two main model types have been published to explain the retention mechanism.
The first model explains the retention loss by lateral redistribution of charge as discuss above. During cycling, both holes and electrons accumulate in the nitride layer due to mismatch between the distributions resulting from the program and erase operation. The holes are de-trapped by thermal activation in the nitride layer and move toward the electron before recombining [21, 24-26].
The second model of retention is the vertical loss of charge through the bottom oxide. During cycling, the bottom oxide is progressively degraded by successive programming and erasing operation, which allows a trap assist tunneling through the bottom oxide [26-28]. Fig. 4.7 explains the generation of trap sites in the bottom oxide during P/E cycling and opens a vertical leakage path between the nitride layer and the substrate. Every trapped charge builds up a potential barrier for the inversion channel charges. After the loss of one of the trapped charge, an additional percolation path can be generated and therefore a higher drain current will flow as shown in Fig.
4.8 [29-30].
4.4.2 Retention Loss Mechanisms for Split-Gate SONOS
Different from conventional SONOS by using drain side CHEI programming,
can adjust the word-gate length to improve the mismatch and suppress the lateral retention loss, which we will discuss in the next chapter. However, the vertical direction retention loss is inevitable. Fig. 4.10 shows the threshold voltage evolution with retention time in a fresh Fig. 4.10 (a) and in a cycled Fig. 4.10 (b) split-gate cell with different gate bias are applied. No charge loss is observed for the fresh cell, since the bottom oxide is clean for a fresh cell. While the retention loss for a cycled cell is dependant on applied gate bias caused by vertical direction retention loss.
(a)
(b)
Fig. 4.1 Diagram of VT profile in a programmed nitride storage memory cell (a) and the illustration of Icp curves versus Vh before and after programming (b).
(a)
(b)
Fig. 4.2 Diagram of VT profile in a programmed nitride storage memory cell (a) and the illustration of Icp curves versus Vb before and after programming (b).
(a)
(b)
Fig. 4.3 The charge pumping current versus Vh of program state (a) and erase state (b) after 1PE cycle (left) and 10kPE cycles (right) for conventional SONOS.
2 4 6 8
tested from drain tested from source tested from drain
tested from source
Vh (V)
tested from drain tested from source tested from drain
tested from source
Vh (V)
Fig. 4.4 The charge pumping current versus Vh of a programmed cell after different numbers of P/E cycles for conventional SONOS.
3 4 5 6 7
0 100p 200p 300p 400p
500p P:CHEI E:BBHH
I cp
(A)
Vh (V)
1P
10PE
100PE
1000PE
10000PE
(a)
(b)
Fig. 4.5 Forward read threshold voltage for various drain voltages (a). The accumulated electrons and holes may alter the current flowing path and
0.4 0.8 1.2 1.6 2.0
With increasing PE cycle numbers
e h Before cycling
After cycling
(a)
(c)
Fig. 4.6 Charge pimping characteristics (a), GIDL measurement (b) and deduced hole distribution (c) of a over-erasing fresh cell, and subsequently after bake of 20k seconds at 150C.
Fig. 4.7 Schematic description of neutral trap formation in the bottom oxide.
(a)
(b)
Fig. 4.8 Schematic of charge loss of thermal activated electron trapped in the nitride trough traps inside the bottom oxide (a). After loss of one of the trapped
Fig. 4.9 The schematic of misalignment between SSI and BBHH for split-gate SONOS.
Control gate
L
WGWord gate
Drain
electron
hole
(a)
(b)
Fig. 4.10 Dependence of threshold voltage on retention time in a fresh cell (a) and a 10k PE cell (b). The gate bias is 0V, -3V and -5V.
1 10 100 1000 10000
-2.0
Chapter 5
Retention Loss Mechanism and Methods to Suppress Lateral Retention Loss for Split-Gate SONOS
5.1 Introduction
Different from conventional SONOS, the split-gate SONOS can adjust the word-gate length (sacrifice spacer length) or the control-gate bias under the erase operation to reduce the misalignment and suppress the lateral retention loss. By comparing the split-gate SONOS with different word-gate length, we can separate the vertical and lateral retention loss, which can not be achieved in conventional SONOS.
In this chapter, we will first compare the retention loss with different word-gate lengths. Next, we compare the retention loss by using positive and negative erase method, which is introduced in chapter three. Then, we contrast the retention loss by applying different control-gate bias under erase operation. Finally, we demonstrate an erasing scheme to suppress the lateral retention loss for all kind of word-gate length devices and discuss the retention loss mechanism for the split-gate SONOS device.
5.2 Retention Loss with Different Word-Gate Length
Fig. 5.1 shows the programming and erasing transient for word-gate length
operation does. It is because the shorter word-gate length device makes the injected electron more close to the junction. Thus, a shorter word-gate length is favorable for the compensation of electron by hole. Fig. 5.2 shows the VGIDL versus Vchannel for the split-gate SONOS with different word-gate lengths. Since the GIDL current is sensitive to the charge above the junction, we can use this method to compare the injected electron distributions. In Fig. 5.2 (b), the shorter word-gate length device has larger slope, since the program charge is injected more close to the junction than long word-gate length device [4, 31-33]. It is worth noting that under GIDL measurement, the drain pulse is applied of 3V to suppress another impact ionization in the junction, which has been discussed in chapter three.
Fig. 5.3 shows the endurance of the three devices. An important increase of erase state threshold voltage is observed, and the situation becomes better for shorter word-gate length device because of the different injection point of electrons and holes.
While for the program state, the threshold voltage has only a little decreasing at first than increasing at last. The incensing of program state threshold voltage is also induced by misalignment, but the decreasing of threshold voltage is cause by interface degradation and non-uniform nitride charge distribution [34]. Fig. 5.4 shows the drain curve versus gate voltage for program state and erase state after different P/E cycles.
It was found that the sub-threshold swing is strongly degraded after large number of successive programming and erasing operation for program state, resulting from the generation of interface state near the junction and resulting in decreasing of the threshold voltage. However, for erase state, the sub-threshold swing has only a little difference. It is because the “local inversion” region induced by excess holes in the
cycling for long word-gate device. It is due to hole accumulated in the nitride, or in the bottom oxide at the drain side, that cause a repulsive effect to the injection of holes in the next cycling as shown in Fig. 5.6 (b).
Since we utilize the same programming and erasing condition for all three devices during cycling, we can assume the bottom oxide are equally damaged. Then, the program state retention loss between two devices is caused by lateral retention loss as shown in Fig. 5.7. It can be said that, vertical retention loss should dominate the total retention loss, however, under a large misalignment situation, the lateral retention loss will give an other non-negligible loss portion. For erase state, the retention loss first increase than decrease a little. The increasing of threshold voltage is cause by drift of holes jump out from bottom oxide into substrate, while the decreasing of the threshold is cause by lateral redistribution of holes in the nitride layer. The larger misalignment between electrons and holes distributions, the more serious of holes drift and lateral move can be observed.
5.3 Retention loss with different Control-Gate Bias
5.3.1 Positive Erase Versus Negative Erase
Fig. 5.8 shows the endurance between the negative and positive erasing scheme.
Although the large positive control-gate bias can narrower the potential contour to make the hot hole injecting into the nitride layer, it will repulse the positive charge
5.3.2 Negative Erase with Adding a Control-Gate Bias
Therefore, we can change the holes distribution by using negative erase but adding a small control-gate bias instead of floating it. Fig. 5.9 shows the erase transient with applying different control-gate bias. A small negative control-gate bias can attract the holes close to the control-gate to make a faster erasing operation, on the contrary, a small positive control-gate bias may repulse the hot holes away from the control-gate to make a slower erasing operation [32]. Fig. 5.10 and Fig 5.11 show the endurance and retention. The misalignment of electrons and holes distribution can be improved by adding a small negative bias and degrade by adding a small positive bias.
The lateral retention loss can be split off again, which verifies the lateral retention is caused by misalignment distribution of electrons and holes.
All in all, the spilt-gate SONOS is very flexible for adjusting the electrons and holes distributions, no meter by altering the word-gate length or by adding different control-gate bias.
5.4 An Erasing Scheme to Suppress Lateral Retention Loss
5.4.1 The mechanism of STHH Erase
Here, we propose an erase scheme to suppress the lateral retention loss. The set up is shown in Fig 2.6. The gate is grounded, and the source and drain are kept floating while apply a pulse to the substrate. The mechanism of this erasing scheme is
in voltage between drain and substrate. As time goes from T2 to T3, the substrate bias immediately back to Vbase, while the floating drain can not catch up but slowly back to the initial position. Therefore, a large band banding occurs at the time from T2 to T3 and generates hot holes to achieve erasing operation. Although the applied pulse width can be micro-second or less, the real erasing time is the time for floating drain move from Vtop-Vbi to Vbase-Vbi. Therefore, we call this erase scheme Substrate Transient Hot Hole erase [7-8, 35].
Fig. 5.13 shows the time versus voltage tested from substrate and drain during erasing at the same Vtop=9V but different Vbase. The lager Vbase –Vtop induces large voltage drop to generate more hot holes. In Fig. 5.13, we can observe that the breakdown voltage of the p-n junction is about 7V, that is, the largest voltage drop is 7V. Fig 5.13 (a) is the case that allows 7V of drop, and the erase window is about 2.2V.
However, the erase window in Fig 5.13 (b) is 2.8V with the same voltage drop of 7V.
It is because the Vbase induces an electric field, making the hole more easily to inject into the nitride layer. Although the larger Vbase induces the stronger electric field and makes hole easily to jump into the nitride layer, the large Vbase could reduces the voltage drop and reduces the erase window as shown in Fig 5.13 (c).
Fig. 5.14 shows the erasing window versus pulse width and pulse counts. Since the real erasing time is the RC time constant, the erase window has no relation with the pulse width. Fig. 5.15 shows erase window versus various of Vbase and Vtop. At Vbase =0V, the four Vtop cases drop the same voltage of 7V, and have the same erase
Vbase =2V, the enhancement of electric field become more stronger to make hole injecting into nitride. However, the voltage drop is decreasing to decrease the erase window for Vtop=8V and 9V cases. The same result happens to Vbase =3V or higher.
All in all, the three important components determine the erase efficient: the voltage drop, the electric filed builds by Vbase and the RC time constant.
5.4.2 STHH Erase for Conventional SONOS
Fig. 5.16 shows the charge pumping measurement for conventional SONOS using CHEI programming and STHH erasing before and after cycling as discussed in chapter four. It was found that the curve does not change their position before and after cycling, which indicates less holes accumulation as shown in Fig 5.17 compared to Fig 4.4. Fig 5.18 shows the forward read threshold voltage of a programming cell after P/E cycle. The curves only have a little shift indicates less electrons accumulation in the channel. A great match between electrons and holes distributions can be achieve by utilizing the STHH erasing scheme to completely erase the program charges in the nitride layer. The interface state can also be calculated by using Fig. 4.4 and Fig 5.17. A small number of STHH will be generate is observed.
5.4.3 STHH Erase for Split-Gate SONOS
Fig. 5.20 shows the endurance of the split-gate SONOS with different word-gate length by using STHH erasing scheme. The erase state threshold voltage is almost independent of word-gate length because the STHH erasing scheme has a widely
state, both of them are independent of word-gate length because of a good match between electrons and holes. For program state, no split off between two curves indicates the suppression of the lateral retention loss. And because of low misalignment between electrons and holes, the remaining hole in the bottom oxide is low, too. Therefore, a small hole drift and lateral redistribution can be observed in the retention loss of erase state.
2.0 2.5 3.0 3.5 4.0 4.5
Fig. 5.1 Schematic for Vt(channel) and Vt(GIDL) (a) and the measured VtGIDL versus Vtchannel with different word-gate length of split-gate SONOS (b).
Vt (channel)
Fig. 5.2 The programming and erasing transient of split-gate SONOS with different
Fig. 5.3 Endurance of split-gate SONOS with different word-gate length.
10
010
110
210
310
41.5
2.0 2.5 3.0 3.5 4.0 4.5
LWG=0.13um LWG=0.13um LWG=0.12um LWG=0.12um LWG=0.10um LWG=0.10um
Vth (V)
Number of PE Cycle
(a)
(b)
Fig. 5.4 The drain current versus gate voltage at program state (a) and erase state (b)
0 1 2 3 4 5 6
(a)
(b)
Fig. 5.5 Illustration of electrons, holes and interface state charge in cycled device being read at program state (a) and erase state (b).
Q e
Q it
N
+Q h
N
+Local Inversion
(a)
(b)
Fig. 5.6 The erasing transient for fresh cell (void) and 10k cycled cell (open) (a), and
10
-610
-510
-410
-310
-2Hard for Hole Injection
Fig. 5.7 Retention loss for split-gate SONOS with different word-gate lengths at 85C.
Fig. 5.8 Endurance for split-gate SONOS using positive BBHH erasing.
10
010
110
210
310
42
3 4
5 P:CHEI E:Positive BBHH
Vth (V)
Number of PE cycle
(a)
(b)
Fig. 5.9 The erasing transient with different control-gate voltage (a), and the schematic diagram for the misalignment with different control-gate voltage
10
-610
-510
-410
-310
-2Fig. 5.10 Endurance for split-gate SONOS with different control-gate voltages during erasing.
10
010
110
210
310
42.0
2.5 3.0 3.5 4.0 4.5
VCG=1 VCG=1 VCG=0 VCG=0 VCG=-1 VCG=-1
Vth (V)
Number of PE Cycle
Fig. 5.11 Retention loss for split-gate SONOS with different control-gate voltages during erasing at 85C.
10
010
110
210
310
410
510
610
710
810
9-2.00
-1.75 -1.50 -1.25 -1.00 -0.75 -0.50 -0.25 0.00
VCG=1V VCG=0V VCG=-1V
Del ta Vth (V)
Retention Time (s)
(a)
(b)
Fig. 5.12 Experiment set up and timing diagram for STHH erasing, and its band
(a)
mesasure from Bulk measured from S/D
Vo ltage (V)
mesasure from Bulk measured from S/DVolta g e (V)
time (s)
Fig. 5.13 The oscilloscope trace of the amplitude of the voltage tested from drain (red) and substrate (black) for the case of Vbase =0V (a) Vbase =1V (b) Vbase
=2V (c) with the same V =9V.
0.0 1.0m 2.0m 3.0m 4.0m 0
2 4 6 8 10
Delta Vth=2.7V mesasure from Bulk measured from S/D
Volta g e (V)
time (s)
(a)
(b)
Fig. 5.14 The oscilloscope trace of the amplitude of the voltage tested from drain with pulse width of 50us (red) and 10us (black) (a), and the erasing
0 1 2 3 4
Fig. 5.15 The threshold voltage shift with varying Vbase and Vtop.
0 1 2 3 4
-1 0 1 2 3 4
Vtop=8V Vtop=9V Vtop=10V Vtop=14V
Delta Vth (V)
Vbase (V)
Fig. 5.16 The charge pumping current versus Vh of fresh cell (black) and 10k cycled cell (b) for conventional SONOS using STHH erasing scheme.
1 2 3 4 5 6 7
0 2x10
-104x10
-106x10
-108x10
-101x10
-91P Tested form Drain 1P Tested from Source 10kPE Tested from Drain 10kPE Tested from Source
Icp (A)
Vh (V)
Fig. 5.17 The charge pumping current versus Vh of a programmed cell after different numbers of P/E cycles for conventional SONOS using STHH erasing scheme.
3 4 5 6 7
0 250p 500p 750p
1n P:CHEI E:STHH
1P 10PE 100PE 1000PE 10000PE
Icp (A)
Vh (V)
Fig. 5.18 Forward read threshold voltage for various drain voltages for conventional SONOS using STHH erasing scheme.
0.4 0.8 1.2 1.6 2.0
Fig. 5.19 Evolution of Dit with the number of P/E cycles endured by the device by using BBHH erase (black) and STHH (red).
10
010
110
210
310
40
1x10
122x10
123x10
124x10
125x10
12P:CHEI E:BBHH P:CHEI E:STHH
Nit (cm
-2)
Number of PE Cycle
Assumption of 40nm width Nit
Fig. 5.20 Endurance for split-gate SONOS with different word-gate lengths by using STHH erasing scheme.
1 10 100 1000 10000
1.5 2.0 2.5 3.0 3.5 4.0 4.5
LWG=0.13um LWG=0.13um LWG=0.12um LWG=0.12um LWG=0.10um LWG=0.10um
Vth (V)
Number of PE Cycle
Fig. 5.21 Retention loss for split-gate SONOS with different word-gate lengths by using STHH erasing scheme at 85C.
Vertical’ + lateral’
10
010
110
210
310
410
510
610
710
810
9Chapter 6
Summary and Conclusion
In this study, a very promising solution for near future flash memory has been proposed. The dual-bit split-gate SONOS allows high density thanks to dual-bit or multi-level/cell storage, and is easily scalable with the bit areas which are physically isolated. The performances are comparable to NROM, but with much lower power consumption because of the use of a more efficient programming mechanism. Most important of all, the split-gate SONOS can improve the misalignment between distributions by adjusting the word-gate length or the control-gate bias condition.
Retention loss mechanism for split-gate SONOS includes both vertical and lateral directions. The best way to improve the vertical retention loss is to make a better quality of bottom oxide, which has no relation to split-gate structure. However, the lateral retention loss is caused by the mismatch of distribution, which can be easily improved by adjusting the word-gate length or the control-gate bias condition of a split-gate structure.
Finally, the substrate transient hot hole erasing scheme is proposed to suppress the misalignment of distributions and improve the lateral retention loss. The charge retention loss mechanism can be said that the vertical retention loss should dominate the total loss, however, under a large misalignment situation, the lateral retention loss will give a non-negligible loss for nitride-based localized trapping memory cell.
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