Organization of the Thesis

This thesis is divided into six chapters. In chapter 1, we introduce the motivation of this study. In chapter 2, we introduce the device fabrication, the setup of experimental instruments, and the basic principle of flash memories. The fundamental principle and basic I-V characteristics are shown in Chapter 3. The mechanism and characteristic of this new program scheme (FBADHE) is described in Chapter 4. The reliability of FBADHE on p-channel flash memories is discussed in Chapter 5. Finally, the summary and conclusion will be given in Chapter 6.

Chapter 2 Device Fabrication and Experimental Setup

This chapter is divided into two sections. First, the semiconductor devices we used in this study will be described. Second, the instrument setup and the experimental techniques to accurately control these instruments are illustrated.

2.1 Device Fabrication

Figure Fig. 2.1 (a) shows the layout of the stacked-gate flash memory cell. The cross-sectional views of the cell in length and width directions are illustrated in Fig. 2.1 (b) and Fig. 2.1 (c), respectively. As shown in Fig. 2.1 (a), the floating gate and the control gate are patterned in the width direction and the length direction, respectively. Moreover, in order to increase the gate coupling coefficient, the floating gate is extended into the Local Oxidation of Silicon (LOCOS) region for enhancing the fringing capacitance between control-gate and floating-gate as given in Fig. 2.1 (c). In addition, the dummy cell with shorted floating gate and control gate is also used for gate current measurement.

In this work, the flash memory cells are prepared based on standard 0.35µm CMOS process and with conventional stacked-gate flash memory cell. The cell sizes which we used in this study are W/L = 0.7/0.65 µm and 0.7/0.45 µm respectively. The floating gate width WFG = 1.2 µm, tunnel oxide thickness TOX = 90 Å, and effective ONO inter-poly dielectric thickness TONO = 165 Å (The individual thickness of interpoly ONO is TTop-Oxide/ TSiN/ TBottom-Oxide=65Å/90Å/55 Å). Interpoly dielectric thickness heavily influences program/erase speed and the magnitude of read current for an industry-standard flash cell [8]. MDD

Substrate

Fig. 2.1 Sketch and cross-sectional view of stacked-gate flash memory. (a) Layout of experimental stacked-gate flash memory. (b) The cross-sectional view of the flash cell in the length direction. (c) The cross-sectional view of the flash cell in the width direction.

(Medium Doped Drain) is used for applying the asymmetric electric field. There are two different doping types of floating gate. The detailed device parameters are summarized in Table 2.1.

2.2 Experimental Setup

The experimental setup for the I-V and transient characteristics measurement of flash memory is illustrated in Fig. 2.2. Based on the PC controlled instrument environment via HP-IB (GP-IB, IEEE-488 Standard) interface, the complicated and long-term characterization procedures during analyzing the intrinsic and degradation behaviors in flash memory cells can be easily achieved. As shown in Fig. 2.2, the characterization equipments, including semiconductor parameter analyzer (HP 4156C), dual channels pulse generator (HP 8110A), low leakage switch mainframe (HP5250A Switching Matrix), and a probe station, provide an adequate capability for measuring the device I-V characteristics and carrying out the flash cell program/erase operations.

The HP 4156C is equipped with four programmable source/monitor units, two source units, and two monitor units for supplying or monitoring the voltage and the current. It provides a high current resolution up to pico-ampere range which facilitates the very low current measurement such as gate current measurement, subthreshold characteristics extraction, DCIV and GIDL measurement for oxide damage characterization. The dual channels HP 8110A with high timing resolution provides two different pulse levels simultaneously for transient and P/E cycling endurance characterization. The Switching Matrix, which is equipped with an 8-input x 12-outoupt switching matrix (with one output module), switches the signals from the HP 4156B and the HP 8110A to device under test (DUT) in probe station, automatically. In addition, the computer language-HP VEE is used to achieve the PC control of these measurement instruments via HP-IB interface.

In order to precisely control the pulse timing of HP 8110A during transient and P/E cycling endurance characterization, we select the triggered pattern mode to achieve this requirement. Fig. 2.3 (a) and Fig. 2.3 (b) show the timing diagrams of the triggered pattern mode method during program and erase operations, respectively. By taking the program timing diagram as an example, the triggered pattern mode method can be explained as follows.

In Fig. Fig. 2.3 (a), the VSMU1 of HP 4156B (illustrated in Fig. 2.2) generates a voltage signal which is equal to the low voltage of HP 8110A. This approach can provide a substrate bias during programming and prevent additional stress to device during programming. The patterned pulses (defined as 01000 in Fig. 2.3 (a) with the minimum period of 10ns) from HP 8110A are then sent and programming of a flash memory cell is performed. In our experience with the HP 8110A, we must set the period of pulse larger than 50 ~ 100ns to obtain a good square pulse and the leading or trailing edge larger than 25 to 50 ns to prevent the over-shoot and under-shoot of output pulse.

In-Situ BF

₂

20keV 5E13

Floating Gate Doping

T.O/SiN/B.O=65/90/55

T _ONO (Å) T _ox (Å) 90

N P

Table 2.1 The spilt table of stacked-gate flash memories used in this study.

HP 8110A Pulse Generator

Probe Station

Switching Matrix KEITHLEY 707 Parameter Analyzer HP 4156B PC

HP 8110A Pulse Generator

Probe Station

Switching Matrix KEITHLEY 707 Parameter Analyzer HP 4156B PC

HP 8110A Pulse Generator

Probe Station

Switching Matrix KEITHLEY 707 Parameter Analyzer HP 4156B PC

Fig. 2.2 The experimental setup of the current-voltage and the transient characteristics measurement in flash cells. Automatic controlled characterizations system is setup based on the PC controlled instrument environment.

Width

Fig. 2.3 The timing diagram of the trigged pattern mode method during (a) program and (b) erase operation.

Chapter 3 Basic I-V Characteristics and Capacitance Coupling

Model of P-channel Flash Memories

This Chapter involves the extraction of MOSFET device basic parameters, threshold voltage, and the coupling model of floating gate memories to extract the parameter. Finally, we show the basic I-V Measurement of flash cells and dummy cells.

In floating gate memory, the floating gate is fully isolated. The voltage of floating gate (VFG) is determined by the coupling of the voltages of other terminals (Control-Gate, Substrate, Source and Drain). Usually, the flash memory cell is modeled by a capacitance equivalent circuit, called the capacitance model [9] [10]. Based on this model, the equation of floating-gate voltage can be determined, from which we can extract the coupling ratio.

3.1 Threshold Voltage Determination

In this study, the threshold voltage VTH is determined from its ID-VG characteristic.

Based on the following drain current equation [11]:

D

in which we can choose an arbitrary drain current level, and set the gate voltage at this drain current level as the device threshold voltage. However, by taking the device geometry into consideration, we need to normalize the device drain current with its channel length and width. This can be done by transforming Eq. (3.1) into

D

Here, we set the threshold voltage as the gate voltage at which the normalized current (ID0) is 0.1µA.

3.2 Capacitance Model and Extraction of Coupling Ratio

It is required for an accurate prediction of the associated coupling ratio in the design of the flash memory cell. We will describe how to extract these parameters in this section.

Besides, we will derive the equations for calculating the floating gate potential.

Fig. 3.1 shows the conventional capacitance model for the flash memory cell. According to this model, the charge balance of floating gate can be derived based on the electrostatic potential Ψ in the various regions of the cell. From

Fig. 3.2, we know that the electrostatic potential Ψ equals to (V+ψ) where V is applied voltage and ψ is flat-band voltage for each terminal, respectively. However, the electrostatic potential ΨFG of floating gate is equal to the voltage VFG. Therefore, the floating gate voltage can be expressed as the following equation

TOTAL

Here, αCG is the gate coupling coefficient, αB is the substrate coupling coefficient, αS is the

source coupling coefficient, and αD is the drain coupling coefficient. Then we assume

The coupling coefficients will be determined in Eq. (3.6). Fig. 3.3 shows the subthreshold characteristics of flash and dummy cells at drain voltage of 0.1 and 1V. Dummy cells show the identical subthreshold characteristic but flash cells are different. This is because the effect of coupling between electrodes. By selecting any two different drain current level (such as IDS

= 10^-5 and 10^-6 A) at VDS = 0.1V, the control gate coupling coefficient can be obtained as

3.3 GIDL Measurement

Gate Induced Drain Leakage Current (GIDL) is one of the major approaches to detect the damage of the oxide and silicon interface in the gate-drain overlap region. [12] [17]. The GIDL current is due to direct band-to-band tunneling in the Off-state MOSFETs. For flash memories, the effect of Band-to-Band tunneling can be also used to inject charges into floating gate [5]. Please refer to section 4.2 for the detailed description of Band-to-Band tunneling.

Fig. 3.4 Shows the GIDL measurements of P-channel flash and dummy cells. For flash cells, the more negative drain voltage causes electrons to be injected into floating gate via Band-to-Band tunneling and then gives rise to the threshold voltage shifts.

The GIDL current is sensitive to trapped charge in the tunneling oxide at the overlap region between the gate and drain, so that we can monitor the qualitative or the quantitative analysis of these Qox and Nit. The analytic model of the GIDL current [18] is shown as follows:

E ) exp( B E

A I

surface surface

GIDL −

×

×

= (3.8)

where Esurface is the electric field at silicon interface. The parameters A and B are defined in ref. [18], and basically they are the fitting parameters in most measurements.

Control Gate

Fig. 3.1 The schematic cross section of a flash cell showing a four-capacitance model.

Ψ

B

Fig. 3.2 Energy band diagram of a flash cell at the onset of inversion (with no charge in the floating gate).

-4 -2 0 1E-15

1E-13 1E-11 1E-9 1E-7 1E-5 1E-3 0.1

Flash Cell

Dummy Cell

@V

_D

= -0.1V

@V

_D

= -1V

@V

_D

= -0.1V

@V

_D

= -1V

DrainCurrent, I

D

(A)

Gate Voltage,V

_G

(V)

Fig. 3.3 The subthreshold characteristic of p-channel flash cell and dummy cell with different drain voltages.

-6 -4 -2 0 2 4 6

Drain Current, I D (A)

Gate Voltage, V_G (V)

Drain Current, I D (A)

Gate Voltage, V_G (V)

Fig. 3.4 GIDL current of (a) dummy cell and (b) flash cell in p-channel cells. For flash cells, the more negative drain voltage causes electrons inject into floating gate by Band-to-Band tunneling so the threshold voltage shifts.

(a)

(b)

Chapter 4 Mechanism and Characteristics of Forward Bias

Assisted Drain Hot Electron Injection

4.1 Introduction

In this chapter, first we describe the mechanism of familiar program schemes used in p-channel flash cells, Band-to-Band tunneling Hot Electron Injection (BBHE), and Drain Avalanche Hot Electron Injection (DAHE). Then, we propose a new program scheme called Forward Bias Assisted Drain Hot Electron Injection (FBADHE). We will investigate the mechanism and the effect on different programming conditions. Finally, we compare the characteristics of the above programming schemes.

4.2 Mechanism of BBHE and DAHE in P-channel Flash cells

In the past, BBHE and DAHE are the popular methods used for programming in P-channel Flash cells. In this section, we will investigate the difference of mechanism between them.

First, we discuss Band-to-Band tunneling Hot Electron Injection [5]. BBHE is used in P-channel Flash cells. For n-channel cells, if we change the structure of MOSFET, i.e., buried a p+ region in the channel, BBHE can also be achieved [7].

When a negative drain voltage and a positive control-gate voltage are applied, the energy band is bended by the difference of the two side of the insulator and band-to-band tunneling

tunneling means that: in the strong band bending, electrons in the valence band edge can move to conduction band, and holes are left on the valence band so that electron-hole pairs generate. Generated carriers will be accelerated by the horizontal electric field and some of them gain sufficient energy. The energetic electrons then inject into floating gate by the effect of vertical field. Fig. 4.1 shows the schematic illustration and the band diagram of BBHE.

Drain Junction avalanche hot carrier (DAHC) historically denotes the emission of free carriers towards the gate generated by impact ionization in the deep depletion region of p-n junction. In p-channel flash cells, when a large negative drain voltage is applied and substrate is grounded, the drain-substrate p-n junction is in strong reverse-bias, the avalanche breakdown occurs. Electrons with high energy cause more and more impact ionization when moving from p region to n region and generate a large amount of electron-hole pairs. Carriers are accelerated by the strong electric field in depletion region so that the energy of these carriers is high enough to surmount the oxide barrier and inject into floating gate even without the assistance of vertical electric field. Fig. 4.2 shows the illustration and band diagram of DAHE. Vertical field determines which carrier will be injected. We measure the relationship of gate voltage and gate current at the condition of drain avalanche breakdown, as shown in Fig. 4.3. We can easily appear that only in the strong negative gate bias is applied (~-8V) that hot holes will inject into floating gate. In other condition, electron current is dominated. So the DAHE Programming Scheme is easily to be achieved in p-channel flash cells. DAHE is a high speed, self-convergent programming scheme [20]. Besides, if a positive gate voltage and a strong drain voltage are applied, a large electric field is generated in the gate-drain overlap region. Band-to-Band tunneling will occurs and electron will inject into floating gate. It is called Gate Induced Drain Leakage (GIDL) current [12].

From the above description, it is realized that the mechanism of BBHE and DAHE is quite different. First, the generation region of carriers (electron-hole pair) of BBHE is in the gate-drain overlap region, and the DAHE is in the deep depletion region of drain-substrate

junction. Second, the energy of generated carriers of BBHE is lower than those in DAHE.

Thus the stronger vertical field is needed for BBHE in order to surmount the oxide barrier.

The advantage of BBHE is high injection efficiency (IG/ID). Fig. 4.4 shows the relationship of IG, ID and VD under the BBHE and DAHE condition respectively. In Fig. 4.4 (a), the Gate current rises at the drain junction breakdown (~-7V). It is realized as DAHE injection. In Fig.

4.4 (b), the Gate current involves F-N tunneling current and band-to-band tunneling current.

The Gate current rises as the increasing of band bending. Because the F-N tunneling current is fixed, the increasing part is band-to-band tunneling current. Fig. 4.5 shows the injection efficiency (IG/ID) of BBHE and DAHE. The efficiency of BBHE (~10^-3) is high than DAHE (~10^-7). It is noticed that in the injection efficiency has a maximum at VD= 0V. It is because there is a little tunneling current (~10^-11@ VG= 10V) but no drain current (~10^-13@ VG= 10V).

So, the magnitude of gate and drain current should be also notified when measuring the injection efficiency. The higher efficiency means the less power consumption. It is noticed than the definition of injection efficiency (IG/ID). For CHEI Programming in N-Channel Flash cells, The MOS is turned on, so the ID is drain current. On the other hand, using either BBHE or DAHE on p-channel flash cells, the MOS isn’t turn on, so the ID is drain leakagecurrent.

The other advantage of BBHE is the better drain disturb characteristics. The serious problem in reliability of p-channel flash is drain disturb [21], which impedes its practical applications for mass production purpose. Larger drain voltage causes more serious drain disturbance. The comparison of BBHE and DAHE is listed in Table 4.1.

P ⁺ Drain (-) FG (+)

BTBT

D (P ⁺ )

Band-to-Band tunneling

e ^- : h ⁺ :

FG

Fig. 4.1 Schematic illustration and Band Diagram of BBHE on the p-channel flash cells.

Electrons in the valence band edge can move to conduction band, and holes are left on the valence band so that electron-hole pairs generate.

Impact Ionization

To FG

P

⁺

Drain (-) N Substrate (+) D (P

⁺

)

Impact Ionization

FG

Depletion region

e

^-

: h

⁺

:

Fig. 4.2 Schematic illustration and band diagram of DAHE on the p-channel flash cells.

Electrons with high energy cause more and more impact ionization when moving from p (Drain) region to n (Substrate) region and generate a large amount of electron-hole pairs.

-15 -10 -5 0 5 10 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4

Programming Region

@ Junction Breakdown (V

_D

= -7V)

DAHE

Ga te C urrent, I (A )

G

DAHH

Gate Voltage,V

_G

(V)

Fig. 4.3 The relationship of gate voltage and gate current under the condition of drain junction breakdown on p-channel flash cells.

-8 -6 -4 -2 0

Drain Voltage,V

_D

(V)

-7 -6 -5 -4 -3 -2 -1 0 1

Drain Voltage,V

_D

(V)

Fig. 4.4 The relationship of drain current, gate current and drain voltage under different gate voltage ((a) VG= 0V and (b) 9V respectively).

(a)

(b)

-8 -6 -4 -2 0 1E-8

1E-6 1E-4 0.01 1 100

DAHE BBHE

V

G

= 0V V

G

= 10V Injection E fficiency, I

G

/ I

D

(A)

Drain Voltage,V

_D

(V)

Fig. 4.5 Injection efficiency (IG/ID) with different gate voltages. The injection efficiency of BBHE (~10^-3) is better than DAHE (~10^-7).

BBHE DAHE Program Speed Slow Fast

Fast

Self-convergence No Yes

Gate Disturb Not serious No Drain Disturb Worse Worst

Table 4.1 Comparison of BBHE and DAHE in p-channel flash cells.

4.3 Mechanism of Forward Bias Assisted Drain Hot Electron Injection in N-Channel Flash Cell

The concept of forward bias assisted programming is proposed by Z. Liu in 1999 [13].

The sample is N-Channel floating gate cells. This program scheme is called “Pulse Agitated Substrate Hot Electron Injection” (PASHEI). The illustration of Program setup is shown in Fig. 4.6. The programming pulse is divided into two parts, emitting time and collect time. The emitting is used to make the substrate-drain diode in forward bias (a negative drain voltage Ve

is applied) and the diffusing current is taking place. Then, changing the diode to reverse bias mode (a positive drain voltage Vwr is applied), and the electrons which are flowing into substrate will be injected into floating gate. The gate voltage VG keeps positive during emitting and collecting time. Please refer to Fig. 4.7 for the injection mechanism. The advantage of this programming technique is only a small programming voltage (~5V as gate voltage and 4V as drain writing voltage) is needed. The disadvantage is a multiple pulse is needed in a program procedure, such as: 100 pulse per programming. It makes the long period of programming time and a complicated circuit design is needed in order to apply this continuous pulse.

We modify the pulse pattern in this study. As shown in Fig. 4.8. We call the new scheme

“Forward Bias Assisted Substrate Electron Injection” (FBASEI). The difference is that the gate voltage is zero during the emitting period and is positive during collecting period. The mechanism is similar as PASHEI, so the injection current is from the substrate too. The performance comparison of CHE, PASHEI and FBASEI is shown in Fig. 4.9. The characteristic of FBASEI is also pulse count dependent, pulse period independent, and low operating voltage is achieved [13]. The reason of poorer programming speed of FBASEI (comparing with PASHEI) is that the less gate pulse period makes fewer electrons injected into the floating gate.

0 V

_G

emitting collecting

floating

S D

FG

CG

V _G

V _G

B

V _S

(b)

V

_wr

V

_e

(a)

Fig. 4.6 The programming setup and pulse pattern of PASHEI in n-channel flash cells.

-D (n+)

(b) V

_D

=V

_e

=-1

h

⁺

e

-D (n+)

(c)V

_D

=V

_wr

=6 e

-+

D (n+)

(a) V

_D

=0

B (p)

Fig. 4.7 The injection mechanism of PASHEI in n-channel flash cells. Substrate electron current inject to floating gate by the effect of vertical electric field.

floating

S D

FG

CG

V _G

B

(b) (a)

0 V

_G

emitting collecting

V _G V _S

V

_D-High

V

_D-Low

Fig. 4.8 The programming setup and pulse pattern of FBASEI in n-channel flash cells. The substrate (p)-drain (n) diode in emitting period is in forward bias and is in reverse bias in collecting time.

1E-7 1E-6 1E-5 1E-4 1.0

1.5 2.0 2.5 3.0 3.5

4.0 CHE

PASHEI FBASEI

Threshold Voltage, V

th

(V)

Program Time (sec)

Fig. 4.9 The characteristics of transient program of CHE, PASHEI and FBASEI in n-channel flash cells.

4.4 Mechanism of Forward Bias Assisted Drain Hot Electron Injection in P-channel Flash Cell

In this section, we will first discuss the difference of mechanism of forward bias assisted hot electron injection in P and N Channel cells. Second, we define the gate current components under different program schemes. Finally, we compare the characteristics with the assistance of forward bias at different operation conditions.

The injection mechanism and performance of the forward bias assisted programming scheme in P-channel cells is quite different from the in N-Channel cells. Fig. 4.10 (a) shows the programming setup and pulse pattern of this program scheme. The concept is similar to N-Channel ones. First, a moderate positive bias is applied on the P-type drain side, and the junction is under forward bias. When changing the mode to reverse bias, deep depletion region is created and carriers in this region suffer strong electric field. Impact Ionization occurs and much energetic carrier is generated and injected into the floating gate. Please refer to Fig. 4.10 (b) for the detailed mechanism. The difference of the scheme in N-Channel ones is the carrier generated in the drain depletion region, so it is Drain Electron Injection and can be called Forward Bias Assisted Drain Hot Electron Injection (FBADHE).

The injection mechanism and performance of the forward bias assisted programming scheme in P-channel cells is quite different from the in N-Channel cells. Fig. 4.10 (a) shows the programming setup and pulse pattern of this program scheme. The concept is similar to N-Channel ones. First, a moderate positive bias is applied on the P-type drain side, and the junction is under forward bias. When changing the mode to reverse bias, deep depletion region is created and carriers in this region suffer strong electric field. Impact Ionization occurs and much energetic carrier is generated and injected into the floating gate. Please refer to Fig. 4.10 (b) for the detailed mechanism. The difference of the scheme in N-Channel ones is the carrier generated in the drain depletion region, so it is Drain Electron Injection and can be called Forward Bias Assisted Drain Hot Electron Injection (FBADHE).

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