Chapter 4 Mechanism and Characteristics of Forward Bias Assisted Drain
4.7 Comparison of Program/Erase Performance with Different Doped Poly
Which poly gate has better performance is an interesting issue to investigate, and is an easier way to improve the performance of flash cells. Fig. 4.23 shows the transient program characteristics with difference doped poly gate. In this figure, in order to identify which has larger threshold voltage shift, we operate the devices with smaller drain voltage, -5.8V for reverse bias. We can see the p+ gate show the better performance. It is because the work function difference of p+ doped gate is larger than n+ ones. It is noted that the initial threshold voltage of above two devices is adjusted to be the same. So that for the given gate and drain voltage, the electric field is also the same. The larger work function difference of p+ doped gate makes electrons easier t to be stored in the floating gate and make the larger threshold voltage shift. The phenomenon is also confirmed in other study [15] [25]. For erase operation, p+ gate suppress the electron injection from the control gate and result the larger threshold voltage shift. Fig. 4.24 shows the transient erase result.
10
-710
-610
-510
-40.5
1.0 1.5 2.0 2.5 3.0 3.5
V
G= 6V V
D-High= 1V V
D-High= -5.8V Floating Gate
p
+doped n
+doped
T hreshold Voltage Shif t, ∆ V
th(V )
ProgramTime (sec)
Fig. 4.23 Transient program characteristics of FBADHE with different doped poly gate.
10
-510
-410
-310
-20.0
0.5 1.0 1.5 2.0 2.5 3.0
V
G= -10V V
B= 5V Floating Gate
p
+doped n
+doped
Threshold Voltage Shift, ∆ V
th(V)
EraseTime (sec)
Fig. 4.24 Transient erase characteristics of FBADHE with different doped poly gate.
Chapter 5 Reliability of FBADHE in P-channel Cells
5.1 Introduction
In this Chapter, we will investigate the reliability of FBADHE. First, we compare the P/E cycling endurance between BBHE and FBADHE. Both of the erase method is Channel F-N erase. And then, we measure the charge loss at room temperature and 80。C respectively to observe its data retention ability. Finally, the Gate/Drain/Read disturb issues are investigated.
5.2 Program/Erase Cycling Endurance
In this section, we compare the cycling endurance of BBHE and FBADHE programming scheme. Both of the erase schemes are Channel-FN. The drain disturb of DAHE is too serious so that we do not compare it with the other programming schemes.
Fig. 5.1 shows the measured endurance of FBADHE and BBHE in P-channel flash with p+ doped gate. The operational condition of BBHE is: VG= 11V, VD=-5V and programming time is 20μs. For FBADHE is: VG= 6V, VD=1 to -5.9V and programming time is 1μs. The erase setup is: VG= -10V, VB=-6V and erase time is 10ms. The window doesn’t change after cycling (~2.3V) but the threshold voltage is slightly decreasing during cycling. An explanation is the pileup of positive charge in the tunnel oxide during erase operation, and the cycling induced interface state (Nit) or oxide trap charge (Qox) causes the degradation of flash cells. In this sample, the endurance performances of FBADHE is a little bit better than BBHE
Next, we compare the endurance of FBADHE with different poly gate doping, as shown in Fig. 5.2. The endurance in n+ gate flash cell is better than p+ gate ones. The program/erase window of FBADHE with p+ poly gate is a little larger than n+ ones with different poly gate and doesn’t show much significant difference. It is because the work function difference, as described in Section 4.6. The main injection mechanism is avalanche induced hot electron and the inter-poly ONO and tunnel oxide is very thick (165Å and 90Å respectively). Thus the electric field difference due to potential difference caused by poly gate doping (~1eV) across the oxide is small so that the performance with different doped gate is close. Furthermore, in our experience, the uniformity of devices also plays an important role on programming/erase window.
Many measurements can be used to investigate the generation of interface state (Nit) and oxide trapped charge (Qox), such as, Charge pumping, GIDL, subthreshold characteristics and Gated Diode. Fig. 5.3 shows the subthreshold characteristics of different program schemes.
Interface state (Nit) can be estimated by measuring the subthreshold slope. The slope doesn’t show significant difference. Previous researches identified that the injection of hot hole is the major factor to degrade the device performance. During FBADHE or BBHE, impact ionization or Band-to-Band tunneling induced hot holes are attracted by the drain, which is applied an appropriate negative voltage, and flow to the p+ drain. At the same time, the gate voltage is positive and will stop hot holes to inject into the floating gate. So that in P-channel flash cells, program operation can eliminate the injection of holes and has better reliability.
10
010
110
210
310
4-5
-4 -3 -2 -1 0
BBHE FBADHE T hreshold Voltage
,V
th(V)
P/E Cycles
Fig. 5.1 Cycling endurance of BBHE and FBADHE in p-channel flash cells. Experimental setup: BBHE: VG= 11V, VD=-5V, programming time is 20μs; FBADHE is: VG= 6V, VD=1 to -5.9V, programming time is 1μs; Erase setup is: VG= -10V, VB= 6V and erase time is 10ms.
10
010
110
210
310
4-3
-2 -1
Floating Gate
p+ doped n+ doped
Thres hold Voltage
,V
th(V)
P/E Cycles
Fig. 5.2 Cycling endurance of FBADHE with different doped gate in p-channel flash cells.
Experimental setup: FBADHE is: VG= 6V, VD=1 to -5.9V, 1μs; Erase setup is: VG= -10V, VB=5V, 10ms
-8 -7 -6 -5 -4 -3 -2 -1 10
-1510
-1310
-1110
-910
-710
-510
-310
-1BBHE (fresh)
BBHE (10
4Cycles) FBADHE (fresh)
FBADHE (10
4Cycles) DrainCurrent, I
D(A)
Gate Voltage,V
G(V)
Fig. 5.3 Subthreshold characteristics comparison of fresh and cycled cells with different programming scheme. The subthreshold slope doesn’t show significant difference.
5.3 Data Retention Characteristics
The other important reliability issue of flash memory cells is data retention ability. Fig.
5.4 shows the data retention characteristics of BBHE and FBADHE respectively at program state at the temperature of 80。C. With the benefit of thick inter-poly ONO and tunnel oxide, the data retention ability is excellent.
5.4 Disturb Characteristics
In this section, we investigate the disturb characteristic before and after cycling. Disturb is a one of the main reliability issue on flash memory cells. We will measure the disturb characteristics and try to improve the performance of reliability to achieve high performance.
There are several kinds of disturbing phenomenon in flash memory cells. Fig. 5.5 shows the type of disturbance effect in a conventional NOR array. WL is Word Line, which connects the gates, and BL is Bit Line, which connects the drains. In order to save the space of chip, the adjacent two cells along the bit line direction share a source line. When we program the cell of the cross-over point of WL1 and BL1, the cells along the WL1 will suffer gate disturb (solid circle in this figure), and the cells along the BL1 suffer gate disturb (dashed circle in this figure). Besides, during read operation, read disturb also occurs. The origin of read and gate disturb failures is the stress induced leakage current [27], and the mechanism of drain disturb is due to Band-to-Band tunneling (BBHE) or Channel Hot Hole (CHH) induced hot electron injection [21]. All of the disturb phenomenon will give rise to the threshold voltage shift, so it is a major concern of the reliability of flash memories.
Fig. 5.6 shows the gate disturb characteristics before and after 10k cycling respectively.
At this figure, we compare the disturb characteristic of BBHE (VG= 11V) and FBADHE (VG= 6V). At BBHE operation, performance before and after cycling shows more significant difference than FBADHE operation. In BBHE, threshold voltage shift of cycled cell after 1000 second stress is about 0.45V. On the contrary, the gate disturb performance of FBADHE shows much less threshold voltage shift, even after 10k cycled. It is an advantage of FBADHE. Fig. 5.7 shows the read disturb characteristic of 10k cycled cells. At read condition (VG= -3V and VD= -1V), threshold voltage doesn’t shift even at a long stress time. It is because the inter-poly ONO and tunnel oxide is thick enough
The gate disturb makes the threshold voltage shift but is not the major concern of reliability because the gate voltage during programming is small and doesn’t make significant threshold voltage shift. Besides, Drain Disturb is well known of the most important reliability issue in p-channel Flash memories [21]. Fig. 5.8 shows the drain disturb characteristics of different program schemes. First we compare the difference with difference drain voltage.
The Vth shift at BBHE operation (VD= -5V) is much smaller than is avalanche operation (VD= -6V) by about 2 orders. This is because the larger drain voltage causes the more generated carriers due to impact ionization and band-to-band tunneling and has sufficient energy to inject into floating gate. Besides, comparing the influence of forward bias, we find that the cells with forward bias assisted suffers serious drain disturb. The reason is the same as above description. More impact ionization and band-to-band tunneling fastens the programming speed, but the same mechanism degrades the reliability of cells. Fig. 5.9 shows the comparison of drain disturb with fresh and cycled cells of BBHE and FBADHE respectively.
The conclusion is the same as Fig. 5.8: the drain disturb of BBHE is much better than FBADHE. It is a trade-off between reliability and programming speed. In above two figures, with FBADHE operation, threshold voltage start to shift at stress time= 10us in fresh cell and 1us in 10k cycled cell. It is unacceptable for industrial requirement so we must find other
A possible solution is to change the array architecture. Since Drain Disturb is the major issue on reliability of P-channel Flash cells in most of the programming schemes (i.e., BBHE, DAHE, FBADH etc), some researches propose new array architecture to improve the drain disturb performance. DINOR structure is one of the solutions used to eliminate drain disturb [26] [21] [5]. During programming operation, by setting all the other select transistors off except for the one which is in the programming mode, maximum drain disturb time can be reduced to 7 times the programming time from the cells connecting to the same sub bit line.
But at FBADHE operation, Drain Disturb is so severe at cycled cells (please refer to Fig. 5.9) that drain disturb can not be solved even DINOR is adopted. Other structure must be developed.
Since the main injection mechanism of FBADHE is forward bias induced impact ionization of the p-n junction, to reduce the impact ionization of junction is the simplest way to mitigate the drain disturb. During programming, -6V is applied on the whole bit line, so we propose to apply an additional moderate negative substrate bias (~ -3V) to the cells along the bit line. It can reduce the junction reverse bias from -6V (VD= -6V; VB= 0V) to -3V (VD= -6V;
VB= -3V). Junction breakdown is prevented such that drain disturb is improved. Therefore, triple well is needed to provide individual substrate bias. Fig. 5.10 shows the improved structure of triple well NOR array. The well line is parallel to the word line. When programming the cell on the node of BL1 and WL1, well line 1 is grounded and -3V is applied at the other well lines. Thus the reverse bias of unselected cells is moderate and won’t cause impact ionization. On the other hand, due to the triple well interconnection, additional isolation and contact area is needed to apply substrate bias and enlarges the cell size. Besides, additional substrate bias induces the other disturb phenomena: substrate disturb. Fig. 5.11 shows the substrate disturb characteristic of unselected cells. Fortunately, moderate substrate bias does not make threshold voltage shift even under long time stress such that the reliability issue of FBADHE operation can be solved by the improved structure. On the other hand, this
structure will make drain-substrate junction along the well line at forward bias mode and causes additional power consumption. So it is a tradeoff between reliability and power consumption. As a result, we suppose the DINOR-like structure (maybe four cells with a select transistor) is the better solution in this operation scheme.
10
210
310
4-5.0
-4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
Program State at 80 ° C
BBHE FBADHE Thres hold V oltage
,V
th(V)
Retention time (sec)
Fig. 5.4 Data retention characteristics of FBADHE and BBHE at 80。C in p+ poly gate flash cells. By the benefit of thick interpoly ONO and tunnel oxide, the data retention ability is excellent even in room temperature or high temperature (80。C).
WL4 WL1
WL2
WL3
BL1 BL2 BL3
SL1
SL2 G.D.
D.D.
PGM!!
Fig. 5.5 Types of disturb in conventional NOR array. D.D. represents the drain disturb, which is along the Bit Line (BL1). G. D. represents the gate disturb, which is along the Word Line (WL1).
1 10 100 1000 0.0
0.1 0.2 0.3 0.4 0.5
V
G= 11V V
G= 6V
fresh
10
4Cycled
Threshold Voltage Shift, ∆ V
th(V)
Disturb Time (sec)
Fig. 5.6 Gate disturb characteristics with different gate voltage in p-channel flash cells.
0.1 1 10 100 1000 -3.5
-3.0 -2.5 -2.0 -1.5 -1.0
Floating Gate p+ doped n+ doped
Thr es hold V olta ge , V
th(V)
Disturb Time (sec)
Fig. 5.7 Read disturb characteristics with different doped floating gate in p-channel flash cells after 10k cycling. Read disturb is very small due to the thick dielectric layer.
10
-710
-610
-510
-410
-310
-210
-110
010
110
20
1 2 3 4 5
V
D-High= 1V V
D-Low= -6V
V
D= -6V
V
D= -5V T hres hold Voltage Shift, ∆ V
th(V)
Disturb Time (sec)
Fig. 5.8 Drain disturb characteristics with different gate voltage in fresh p-channel flash cells.
10
-710
-610
-510
-410
-310
-210
-110
010
110
20
1 2 3 4 5 6
Solid: fresh
Hollow: 10k cycled FBADHE BBHE
Threshold Voltage Shift, ∆ V
th(V)
Disturb Time (sec)
Fig. 5.9 Drain disturb characteristics with different drain voltage before and after 10k cycling in p-channel flash cells.
WL4 WL1
WL2
WL3
BL1 BL2 BL3
SL1
SL2
Well Line1 (-3V)
Well Line3 GND
Well Line3 GND
Well Line4 GND
PGM!!
Fig. 5.10 Improved NOR array with triple well technology for applying the substrate bias.
10 100 1000 -4.0
-3.5 -3.0 -2.5 -2.0 -1.5
Thre shold V oltage, V
th(V)
Disturb Time (sec) Floating Gate
p+ doped n+ doped
Fig. 5.11 Substrate disturb characteristics with different doped floating gate after 10k cycling in p-channel flash cells.
Chapter 6 Summary and Conclusions
Based on the experimental results, several issues have been addressed in this thesis. A novel programming scheme used in p-channel flash memories is proposed. i.e., Forward Bias Assisted Drain Hot Electron injection (FBADHE). The mechanism is to apply a forward bias on drain-substrate junction and then change the mode of p-n junction to reverse bias. Forward bias induced carrier flowing will generate more impact ionization under the reverse bias condition and more energetic electrons will be injected into the floating gate.
Then, we compare the characteristic of FBADHE. BBHE and DAHE. DAHE has the fastest programming speed, and BBHE has the lowest drain voltage. By comparing the transient characteristic, we can clarify the injection mechanism of FBADHE which involves band-to-band tunneling and drain avalanche induced hot electron, and the later one is the main injection component.
The advantage of FBADHE is fast programming speed (~1μs) and low operating voltage (~6V). Even in flash cells with thick tunnel oxide and inter-poly, low operating voltage can achieve large window. It means that the data retention performance will be excellent. Comparing to BBHE, the higher gate voltage (~10V) limits the programming speed by the gate disturb phenomenon. The disadvantage of FBADHE is the severe drain disturb. It is also the major reliability concern of p-channel flash memories. We can improve the drain disturb performance by adopting a new array structure, which is described in Chapter 5.
Although larger cell area is needed in new structure, the low voltage and high speed programming are suitable for the applications.
References
[1] F. Masuoka, M. Asano, H. Iwahashi, T. Lomuro and S. Tanaka, “A New flash
EEPROM cell using triple polysilicon technology,” in IEDM Tech. Dig., pp. 464-467, 1984.
[2] N. Tsuji, N. Ajika, K. Yuzuriha, Y. Kunori, M. Hatanaka, and H. Miyoshi, “New Erase Scheme for DINOR Flash Memory Enhancing Erase/Write Cycling Endurance Characteristics,” in IEDM Tech. Dig., pp. 53-56, 1994.
[3] C. Y. Hu, D. L. Kencke, and S. K. Banerjee, “Substrate-current-induced hot electron (SCIHE) injection: a new convergence scheme for flash memory,” in IEDM Tech.
Dig., pp. 283-286, 1995.
[4] J. D. Bude, M. Mastrapasqua, M. R. Rinto, R. W. Gregor, P. J. Kelley, R. A. Kohler, C. W. Leung, Y. Ma, R. J. McPartland, P. K. Poy, and R. Singh, “Secondary Electron Flash – a High Performance, Low Power Flash Technology for 0.35um and Below,”
in IEDM Tech., Dig., pp. 279-282, 1997.
[5] T. Ohnakado, K. Mitsamaga, M. Nunoshita, H. Onoda, K. Sakakibara, N. Tsuji, N.
Ajika, M. Hatanada, and H. Miyoshi, “Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a P-channel Cell,” in IEDM Tech. Dig., pp. 279-282, 1995.
[6] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A Frommer, and D. Finzi, “NROM: A novel localized trapping, 2-bit nonvolatile memory cell,” in IEEE Electron Device Letters, Vol. 21, no. 11, 2000.
[7] I. C. Chen, D. J. Coleman, and C.W. Tang, “Gate current injection initiated by electron band-to-band tunneling in MOS devices,” in IEEE Electron Device Letters, vol. 10, no. 7, pp. 297, 1989.
[8] K. Komori, K. Kuroda, S. Meguro, K. Nagasawa, M. Fukuda, K. Uchibori and T.
Hagiwara, “A high performance memory cell technology for mega bit EEPROMs,” in
[9] P. Pavan, R. Bez, P. Olivo and E. Zanoni, “Flash Memory Cells-An Overview,”
Proceedings of the IEEE, vol. 85, pp.1248, 1997.
[10] P. Pavan, L. Larcher and A. Marmiroli, Floating Gate Devices: Operation and Compact Modeling, Kluwer Academic, 2004.
[11] S. M. Sze, Physics of semiconductor devices, 2nd Ed. Wiley-Interscience, New York, p. 440, 1981.
[12] T. Y. Chan, J. Chen, P. K. Ko and C. Hu, “The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling,” in IEDM Tech. Dig., pp. 718, 1987.
[13] Z. Liu and T. P. Ma, “A New Programming Technique for flash memory devices,” in VLSI TSA, pp.195-198, 1999.
[14] T. Endoh, H. Iizuka, S. Aritome, R. Shirota and F. Masuoka, “New write/erase operation technology for flash EEPROM cells to improve the read disturb characteristics,” in IEDM Tech. Dig., pp. 603-606, 1992.
[15] H. W. Tsai, P. Y. Chiang, S. S. Chung, D. S. Kuo and M. S. Liang, ”The performance and Reliability of ETOX P-channel Flash EEPROM Cell With P-Doped
Floating-Gate,” in VLSI TSA, pp.36-39, 2003.
[16] A. T. Wu, T. Y. Chen, P. K. Ko and C. Hu,, ”A source-side injection erasable programmable read-only-memory (SI-EEPROM) device,” IEEE Electron Device Letters, vol. 7, no. 9, pp.540-542, 1986.
[17] T. E. Chang, C. Huang, and T. Wang, “Mechanism of Interface Trap-Induced Drain Leakage Current in Off-State N-MOSFET’s” IEEE Trans. on Electron Devices, vol.
42, no. 4, pp738-743, 1995.
[18] R. S. Scott and D. J. Dumin, “The Charging and Discharging of High-Voltage Stress-Generated Traps in Thin Silicon Oxide,” IEEE Trans. Electron Devices, vol.
43, pp. 130-136, 1996.
[19] J. Chen, T. Y. Chen, I. C. Chen, P. K. Ko and C. Hu, “Subbreakdown Drain Leakage Current in MOSFET,” IEEE Electron Device Letter, vol. 8, no. 11, pp.515-517, 1987.
[20] S. Yamada, T. Suzuki, E. Obi, M. Oshikiri, K. Naruke, and M. Wada, “A
self-convergence erasing scheme for a simple stacked gate flash EEPROM,” in IEDM Tech. Dig., pp. 307-310, 1991.
[21] S. Chung, S. T. Liaw, C. M. Yih, Z. H. Ho, “N-Channel versus P-channel Flash EEPROM- Which one has better reliabilities,” in Proc. IRPS, pp. 67-72, 2001.
[22] K. T. San, C. Kaya, and T. P. Ma,”Effects of Erase Source Bias on Flash EEPROM Device Reliability,” IEEE Trans. Electron Devices, vol. 42, no. 1, pp. 150-159, 1995.
[23] Ben. G. Streetman, Sanjay Banerjee, Solid State Electronic Devices, Prentice Hall, 1995.
[24] D. A. Neaman, Semiconductor Physics and Devices: Basic Principles, McGraw Hill, 1997.
[25] Victor. C. W. Kuo, C. M. Chao, C. K. Kang, L. E. Liu, L. T. Kuo, S. H. Chen, H. C.
Wei, H. P. Hwang, and S. Pittikoun, “Detailed Comparisons of Program, Erase and Data Retention Characteristics between P+- and N+-Poly SONOS NAND Flash Memory,” in MTDT, pp. 77-79, 2006.
[26] H. Onoda, Y. Kurori, S. Kobayashi, M. Ohi, A Fukumoto, N. Ajika, and H. Miyoshi,
“A novel cell structure suitable for a 3V volt operation, sector erase flash memory,”
in IEDM Tech. Dig., pp. 599-602, 1992.
[27] K. Naruke, S. Taguchi, and M. Wada, “Stress Induced Leakage Current limiting to scale down EEPROM tunnel oxide thickness,” in IEDM Tech. Dig., pp. 560-563, 1987.