In this thesis, experimental process and electrical parameters extraction are shown in chapter 2. In chapter 3, the performance of FSA-TFTs (in-situ doped gate) and that of control TFT are compared. At the same time, the performance of FSA-TFTs (un-doped gate) and that of control TFTs are compared. Some more detailed electrical characteristics of FSA-TFTs are discussed. In chapter 4, the conclusions of this thesis and the future works are given.
Chapter 2
Experimental process and electrical parameters extraction
2.1 Fabrication of poly-Si thin-film transistors (poly-Si TFTs)
In this section, the process flow of poly-Si thin-film transistor is described, including the process flows of the FSA-TFTs and the control TFTs.
2.1.1 Fabrication of the FSA-TFTs
The process flows of devices are showed in Fig.2-1. First, a 550-nm thick oxide was deposited on the 6-in wafers. Then, a 40-nm thick a-Si layer was deposited as the active layer in a LPCVD system using SiH4 as source at 550°C. The a-Si was crystallized to poly-Si by solid phase crystallization (SPC) process at 600°C for 24 hours. Then the wafers were subjected to photolithography for active region definition.
A 50-nm thick TEOS oxide layer and a 50-nm a-Si layer were deposited. A 150-nm nitride was deposited by LPCVD as hard mask. Then the nitride layer and the a-Si layer were etched by the oxide dry etcher (TEL-5000) and poly-Si dry etcher (TCP- 9400), respectively. The wafers were ion implanted by phosphorous. The energy and the dose of implantation were 45 keV and 5×1015 cm-2, respectively. A 300-nm thick TEOS oxide was deposited, then the spacer was formed by TEL5000 to avoid bridge
effect between gate and S/D. The 150-nm thick nitride layer was stripped by H3PO4. After a HF-dip for 10-sec, a 40-nm thick Ni and a 10-nm thick TiN were deposited on the wafer by Metal-PVD. NiSi was formed in the gate and S/D region by rapid- thermal annealing (RTA) at 550°C for 30 seconds. The unreacted TiN and Ni were selectively removed by H2SO4.
2.1.2 Fabrication of control TFTs
Besides the fabrication of FSA-TFTs, control TFTs were also fabricated for comparison. In fast, the process flow of the control TFTs is nearly the same as that of FSA-TFTs. So, the process flow of the control TFTs is described briefly. First, a 550-nm thick oxide was deposited on the 6-in wafers. Then, a 40-nm thick a-Si layer was deposited as active layer in a LPCVD system. The a-Si was crystallized to poly-Si by SPC process at 600°C for 24 hours. Then the wafers were subjected to photolithography for active region definition. A 50-nm thick TEOS oxide layer and a 50-nm in-situ doped a-Si layer were deposited in a vertical furnance. A 150-nm nitride was deposited by LPCVD as the hard mask. Then the nitride layer and the in-situ doped a-Si layer were etched by the TEL-5000 and TCP-9400, respectively. The wafers were ion implanted by phosphorous. The energy and the dose of implantation were 45 keV and 5×1015 cm-2, respectively. A 300-nm thick TEOS oxide was
deposited, then the spacer is formed by TEL5000. The 150-nm thick nitride layer was etched by H3PO4. Next, 300-nm passivation oxide was deposited by PECVD and patterned for contact holes opening. A 500-nm thick Al was immediately thermal evaporated, followed by lithography for Al pad pattern definition.
2.2 Electrical parameters extraction
In this section, the methods of parameter extraction used in this study are described. These parameters include parasitic resistance (RP), threshold voltage (VTH), subthreshold swing (S.S.), field-effect mobility (µFE), ON current (ION), OFF current (IOFF), ON/OFF current ratio (ION/IOFF).
2.2.1 Parasitic resistance (R
P)
The device parasitic resistances are extracted from their output characteristics. It is known that when devices are operated under low drain voltage and high gate voltage their measured resistance (Rm) can be expressed as
where Rch and Rp represent channel resistance and parasitic resistance. COX is the gate dielectric capacitance per unit area and W, L, VTH are device channel width, length and threshold voltage, respectively. The parasitic resistance Rp can be extracted by plotting Rm versus L for varying gate voltages.
2.2.2 Threshold voltage (V
TH)
The threshold voltage VTH is an important parameter required for the channel length-width and series resistance measurements. However, VTH is not unique defined.
Various definitions exist and the reason for this can be found in the ID-VG curves. One of the most common threshold voltage measurement technique is the linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of 50~100 mV typically to ensure operation in the linear MOSFET region.
However, in this thesis, the threshold voltage is defined at a fixed drain current ID=IDN×(W/L) where IDN is a normalized drain current. Here, IDN is 100 nA and the same for all devices.
2.2.3 Subthreshold swing (S.S.)
The drain current in the saturation region(VD>VG-VTH) is expressed as the equation. In reality, there is still some drain conduction current below threshold, and this is known as the subthreshold conduction. This current is due to the weak inversion in the channel between flat-band and threshold, which leads to a diffusion
current from source to drain.
The subthreshold swing (S.S.) is defined as the reciprocal of slope of the ID-VG
curve in weak inversion region. It is the amount of gate voltage required to increase/
decrease drain current by one order of magnitude. It is a typical parameter to describe the control ability of gate toward channel.
In this thesis, the subthreshold swing is defined as one-third of the gate voltage required to decrease the threshold current by three orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to threshold voltage.
2.2.4 Field effect mobility (µ
FE)
The field effect mobility (
µ
FE) is extracted from the maximum value of transconductance (gm) at low drain voltage. The drain current in linear region (VD＜VG − VTH) can be approximated as the following equation: L is the channel length, VTH is the threshold voltage,
Cox is the gate oxide capacitance per unit area.
Therefore, the field-effect mobility is
0
2.2.5 ON/OFF current ratio
A poly-Si TFT with good characteristics should have not only high ON state driving current but also low OFF state leakage current. For pixel transistors, the OFF state is frequently encountered in normal operation. Therefore, ON/OFF current ratio is obviously a better evaluation parameter compared with ON state current alone.
The leakage current mechanism in poly-Si TFTs is not like that in MOSFET. In MOSFET, the channel is composed of single crystalline Si and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. However, in poly-Si TFTs, the channel is composed of poly crystalline Si. A large amount of trap densities in grain structure attribute a lot of defect states in energy band gap to enhance the tunneling effect. Therefore, the leakage current due to the tunneling effect is much larger in poly-Si TFTs than that in MOSFET. Considering large negative gate bias VG is applied, a hole channel forms under the gate. In principle, little current flows because the junction between the hole
channel and the drain is reverse-biased. However, due to the existing numerous trap states in the polysilicon film and the large electric field, electron and hole emission from trap states becomes a strongly increasing function of electric field. Here, a trap could be modeled by a potential well. For large electric fields, it is possible for electrons to escape the potential well by quantum mechanical tunneling. The tunneling rate increases strongly with electric field because the barrier thickness decreases. The effect is a rapid increase in leakage current. The tunneling rate depends upon the total electric field, and consequently the leakage current is highest when both drain and gate voltages are large.
In this thesis, take n-channel poly-Si TFTs for examples, the ON current is defined as the drain current when gate voltage equals to 15 V and drain voltage is 0.5 V. The OFF current is specified as the minimum current when drain voltage equals to 0.5 V.
(1) 550-nm thick buried oxide and 40-nm thick a-Si were deposited.
(2) 600°C annealing for 24-hr and active region definition.
(3) 50-nm thick TEOS oxide , 50-nm thick a-Si and 150-nm thick nitride layer.
(4) Gate definition.
a-Si
Buried oxide
poly-Si
Buried oxide
TEOS a-Si Nitride
Buried oxide
poly-Si
TEOS a-Si
Buried oxide
poly-Si Nitride
(5) Phosphorous implantation.
(6) TEOS spacer formation.
(7) Nitride layer was etched by H3PO4.
(8) Ni and TiN deposition.
(9) NiSi formation by RTA 550°C.
Fig. 2-1 Process flows of fully Ni-salicidation TFTs.
TEOS
Buried oxide
poly-Si
Ni-salicided TEOS
a-Si
Buried oxide
poly-Si N+
N+
TiNNi
Chapter 3
Electrical Characteristics of the Fully Ni-Salicided TFTs
At first, the cross-section TEM of FSA-TFTs (un-doped gate RTA 550°C 30-sec) is shown in Fig.3-1. Thicknesses of channel film, TEOS oxide and gate are shown in Fig.3-2. In this chapter, the electrical characteristics of control TFTs and FSA-TFTs (in-situ doped gate) with RTA 550°C 30-sec are compared at first in 3.1. Then the electrical characteristics of control TFTs and FSA-TFTs (un-doped gate) with RTA 550°C 30-sec are compared in 3.2. Device parameters including parasitic resistance (RP), threshold voltage (VTH), subthreshold swing (S.S.), field-effect mobility (µFE), ON current (ION), OFF current (IOFF), and ON/OFF current ratio are all extracted. Next step, we will explain the electrical characteristics of control TFTs and FSA-TFTs. We found that S/D fully salicidation resulted in the reduction of VTH、kink effect、
threshold voltage roll off、subthreshold swing roll off and Gate-Induced-Drain- Leakage (GIDL) enhancement current.
3.1 Basic electrical characteristics of FSA-TFTs (in-situ doped gate)
Figure 3-3 shows the parasitic resistance (RP) of the control TFTs. The extracted
value of RP is 7.521 kΩ. Figure 3-4 shows the parasitic resistance (RP) of the FSA-TFTs. The extracted value of RP is 0.7965 kΩ. Obviously, the RP of the FSA-TFTs is significantly lower than that of the control TFTs.
Figure 3-5 exhibits ID-VG and field-effect mobility characteristics of control TFTs with W/L=10 µm/10 µm and Tox=500 Å. The drain bias is 0.5 V and 5.0 V. The ON current (ION) at VD=0.5 V and VG=15 V of control TFTs is 12.68 µA. The OFF current (IOFF，the minimum value of drain current) of control TFTs is 1.25 pA. So, the ON/OFF current ratio (ION/IOFF) is 1.01×107. The maximum mobility of control TFTs is 29.58 cm2/V-s.
Figure 3-6 exhibits ID-VG and field-effect mobility characteristics of the FSA-TFTs with W/L=10 µm/10 µm and Tox=500 Å. The drain bias is 0.5 V and 5.0 V.
The ON current at VD=0.5 V and VG=15 V of FSA-TFTs is 14.44 µA. The OFF current of FSA-TFTs is 0.1 pA. So, the ON/OFF current ratio is 1.444×108. The maximum mobility of the FSA-TFTs is 33.96 cm2/V-s. Based on the above electrical results, significant improvements can be found for the FSA-TFTs. All devices’
parameters of the control TFTs and the FSA-TFTs are listed in the Table 3-1.
Figure 3-7 shows the comparison of ID-VG characteristics at VD=0.5 V between control TFTs and FSA-TFTs with W/L=10 µm/10 µm. Figure 3-8 shows the comparison of mobility between control TFTs and FSA-TFTs with W/L =10 µm/10
µm. Fully Ni-salicidation remarkably improves the mobility of TFTs. From Table 3-1, FSA-TFTs give smaller threshold voltage, higher mobility, higher ON current and higher ON/OFF current ratio.
Figure 3-9 show ID-VD characteristics of control TFTs and FSA-TFTs with W/L
=10 µm/10 µm (VG-VTH=3.0 V, 4.0 V, 5.0 V, 6.0 V). The output current of FSA-TFTs is obviously larger than that of control TFTs. The low parasitic resistance by fully Ni- salicidation greatly boosts the output current.
Figure 3-10 shows ID-VD output characteristics of control TFTs and FSA-TFTs with W/L=10 µm/0.8 µm. The output characteristics exhibit in fact an anomalous current increase in the saturation region. The kink effect [31-32] is observed. The detailed explanation about the kink effect is shown in 3.3.2.
Figure 3-11 exhibits VTH roll off characteristics of control TFTs and FSA-TFTs.
All threshold voltages of control TFTs and FSA-TFTs are summarized in Table 3-2.
The threshold voltage roll off from 10 µm to 0.8 µm of control TFTs at VD=0.5 V is 1.402 V. The threshold voltage roll off from 10 µm to 0.8 µm of FSA-TFTs at VD=0.5 V is 0.37 V. Obviously, threshold voltage roll off phenomenon of control TFTs is more severe than that of FSA-TFTs. Because the floating body effect of control TFTs is more severe than that of FSA-TFTs. So, VTH roll off phenomenon of control TFTs is more severe.
Figure 3-12 exhibits subthreshold swing (S.S.) roll off characteristics of control TFTs and FSA-TFTs. The drain bias is 5 V. The channel width is 10 µm. The S.S. roll off from 10 µm to 0.8 µm of control TFTs at VD=5 V is 295.84 mV/dec. The S.S. roll off from 10 µm to 0.8 µm of FSA-TFTs at VD=5 V is 148.04 mV/dec. Table 3-3 shows detailed data about subthreshold swing from 10 µm to 0.8 µm. Obviously, S.S. roll off phenomenon of control TFTs is more severe than that of FSA-TFTs.
Figure 3-13 shows the mobility of control TFTs and FSA-TFTs when the channel length is 10 µm and 0.8 µm. The channel width is 10 µm. Table 3-4 shows detailed data about maximum mobility. The maximum mobility of FSA-TFTs are 33.96 cm2/ V-s and 32.01 cm2/V-s when the channel length is 10 µm and 0.8 µm. The degradation of mobility from 10 µm and 0.8 µm is 1.95 cm2/V-s. The maximum mobility of control TFTs is 29.58 cm2/V-s and 23.03 cm2/V-s when the channel length is 10 µm and 0.8 µm. The degradation of mobility from 10 µm and 0.8 µm is 6.55 cm2/V-s.
Clearly, the mobility degradation of control TFTs is more severe than that of FSA- TFTs. This can be explained from Fig. 3-14. Where A is the channel length, B is the S/D regions. When channel length is decreased, the serious S/D resistance becomes prominent. This will result in the across voltage of the channel region becomes smaller. When the lateral electrical field becomes smaller, the mobility becomes smaller. But fully Ni-salicidation can result in the decrease of parasitic resistance. So,
the mobility roll off of FSA-TFTs from 10 µm to 0.8 µm is not severe.
The off-state leakage currents in n-type device are measured for channel length of 10 µm and 0.8 µm at VG=-5 V as shown in Fig. 3-15. Obviously, the leakage current of FSA-TFTs from 10 µm to 0.8 µm has little variation. However, the leakage current of control TFTs from 10 µm to 0.8 µm increases very quickly at VD=8 V. This is because the fully Ni-salicidation can suppress parasitic BJT effect, the FSA-TFTs do not have severe GIDL enhancement current. About GIDL enhancement current is explained clearly in section 3.3.3.
3.2 Basic electrical characteristics of FSA-TFTs (un-doped gate)
In this section, the electrical characteristics of control TFTs and FSA-TFTs (un-doped gate) with RTA 550°C 30-sec are compared.
The parasitic resistance (RP) of the control TFTs is 7.521 kΩ. Figure 3-16 shows the parasitic resistance (RP) of the FSA-TFTs. The value of RP is 0.7224 kΩ.
Obviously, the RP of the FSA-TFTs with un-doped gate is much lower than that of the control TFTs.
Figure 3-17 exhibits ID-VG and field-effect mobility characteristics of the FSA-TFTs with W/L=10 µm/10 µm and Tox=500 Å. The drain bias is 0.5 V and 5.0 V.
The ON current at VD=0.5 V and VG=15 V of FSA-TFTs is 13 µA. The OFF current of FSA-TFTs is 0.1 pA. So, the ON/OFF current ratio is 1.3×108. The maximum mobility of the FSA-TFTs is 32.36 cm2/V-s. All devices’ parameters of the control TFTs and the FSA-TFTs are listed in the Table 3-5. Similar to the results of device with doped gate, ON current, ON/OFF current ratio, the maximum mobility of FSA-TFTs with un-doped gate is higher than those of control TFTs.
Figure 3-18 shows the comparison of ID-VG characteristics at VD=0.5 V between control TFTs and FSA-TFTs with W/L=10 µm/10 µm. Figure 3-19 shows the comparison of mobility between control TFTs and FSA-TFTs with W/L =10 µm/10 µm. The fully Ni-salicidation remarkably improves the mobility of TFTs.
Figure 3-20 show ID-VD characteristics of control TFTs and FSA-TFTs with W/L= 10 µm/10 µm (VG-VTH=3.0 V, 4.0 V, 5.0 V, 6.0 V). The output current of FSA- TFTs is obviously larger than that of control TFTs.
Figure 3-21 shows ID-VD output characteristics of control TFTs and FSA-TFTs with W/L=10 µm/0.8 µm. The kink effect is observed.
Figure 3-22 exhibits VTH roll off characteristics of control TFTs and FSA-TFTs.
All threshold voltages of control TFTs and FSA-TFTs are summarized in Table 3-6.
The threshold voltage roll off from 10 µm to 0.8 µm of control TFTs at VD=0.5 V is 1.402 V. The threshold voltage roll off from 10 µm to 0.8 µm of FSA-TFTs at VD= 0.5
V is 0.48 V. Obviously, threshold voltage roll off phenomenon of control TFTs is more severe than that of FSA-TFTs.
Figure 3-23 shows subthreshold swing (S.S.) roll off characteristics of control TFTs and FSA-TFTs. The drain bias is 5 V. The channel width is 10 µm. Table 3-7 shows detailed data about subthreshold swing from 10 µm to 0.8 µm. The S.S. roll off from 10 µm to 0.8 µm of control TFTs at VD=5 V is 295.84 mV/dec. The S.S. roll off from 10 µm to 0.8 µm of FSA-TFTs at VD=5 V is 172.17 mV/dec. Obviously, S.S. roll off phenomenon of control TFTs is more severe than that of FSA-TFTs.
Figure 3-24 shows the mobility of control TFTs and FSA-TFTs when the channel length is 10 µm and 0.8 µm. The channel width is 10 µm. Table 3-8 shows detailed data about maximum mobility. The maximum mobility of FSA-TFTs is 32.36 cm2/V-s and 29.46 cm2/V-s in the channel length of 10 µm and 0.8 µm. The degradation of mobility from 10 µm and 0.8 µm is 2.9 cm2/V-s. The degradation of mobility from 10 µm and 0.8 µm is 6.55 cm2/V-s in the control TFTs. Clearly, the mobility degradation of control TFTs is more severe than that of FSA-TFTs.
The off-state leakage currents in n-type device are measured for channel length of 10 µm and 0.8 µm at VG=-5 V as shown in Fig. 3-25. Obviously, the leakage current of FSA-TFTs from 10 µm to 0.8 µm has much less variation. However, the leakage current of control TFTs from 10 µm to 0.8 µm increases significantly at VD=8
V. So, the FSA-TFTs does not have severe GIDL enhancement current.
Figure 3-26 shows the GIDL enhancement current for in-situ doped gate and un-doped gate FSA-TFTs with W/L=10 µm/10 µm. The gate voltage is -5 V. The GIDL enhancement current of FSA-TFTs (un-doped gate) is higher than that of FSA -TFTs (in-situ doped gate). The doping of the poly-Si gate prior to complete gate silicidation affects the NiSi workfunction. The different dopant’s amount can tune the work function of NiSi [29]. Different work function of NiSi results in the larger leakage for FSA-TFTs with un-doped gate.
3.3 Analysis of the poly-Si TFT’s electrical characteristics
In this section, some electrical characteristics of devices will be discussed, including the reduction of VTH using the S/D fully salicidation processes, kink effect, Gate-Induced-Drain-Leakage (GIDL) enhancement current.
3.3.1 The reduction of V
THusing the S/D fully salicidation processes
Fully Ni-salicidation in the S/D region can result in the reduction of the threshold voltage. In the following, a equivalent circuit model is used to explain this phenomenon in Fig.3-27 [33]. A source resistance RS and a drain resistance RD are assumed to connect an intrinsic TFT to the external terminals where VDS and VG are applied. The internal voltages are V’DS and V’G for the intrinsic TFT. The following
relations are :
V’DS=VDS-(RS+RD)IDS--- (Eq. 3.1) V’G=VG-RS×IDS--- (Eq. 3.2) As shown in Fig. 3-27, an actual device with parasitic resistance is equivalent to an intrinsic TFT with a grounded source, with V’G and V’DS at the gate and the drain terminals, and with a negative bias –RSIDS on the substrate. A negative bias on the substrate leads to the body effect. This phenomenon results in the higher threshold voltage.
Fully Ni-salicide in the S/D region can result in the drastic decrease of the series resistance RS and RD. Therefore, the negative bias on the substrate is decreased and the body effect is alleviated. So, the threshold voltage of TFTs could be reduced by the Ni-salicidation process.
3.3.2 Kink effect
The output characteristics exhibit an anomalous current increase in the saturation region. The kink effect is observed. The kink effect in TFTs is showed in Fig. 3-28.
The short gate length and high drain bias result in the lateral electric field becomes stronger. The stronger lateral electric field causes impact ionization near the drain, generating more electron-hole pairs. Due to impact ionization occurring at the drain end of the channel, holes are injected into the floating body. The presence of these
The short gate length and high drain bias result in the lateral electric field becomes stronger. The stronger lateral electric field causes impact ionization near the drain, generating more electron-hole pairs. Due to impact ionization occurring at the drain end of the channel, holes are injected into the floating body. The presence of these