Chapter 1 Introduction
1.3 Organization of the Thesis
There are four chapters in this thesis. In chapter 1, we describe the background of Flash memory, its applications and development, advantages and disadvantages, challenges and motivation for semiconductor nanorcryatal nonvolatile memories.
In chapter 2, we use Dual E-Gun Evaporation System to deposit thin PrO2 layer, the wafer was subjected to RTA treatment to form nanocrystal, subsequently. The electrical characteristics of nanocrystal memory devices by using PrO2 as nanocrystal material are investigated.
In chapter 3, we use Dual E-Gun Evaporation System to deposit thin LaAlO3 layer, the
wafer was subjected to RTA treatment to form nanocrystal, subsequently. The electrical characteristics of nanocrystal memory devices by using Lanthanum aluminate (LaAlO3) as nanocrystal material are investigated.
Finally, in chapter 4, the conclusions are made and the recommendation describes the topics which can be further researched.
Table 1.1 Performance comparison between volatile memory (DRAM &
SRAM) and nonvolatile memory (Flash, FRAM, and PCM) devices. Flash
memory exhibits the best performance except the disadvantages of high
programming voltage and slow program/erase speed.
Fig. 1.1 MOS memory tree.
VG
Si-substrate
Source Drain
Dielectric Floating Gate Control Gate
Dielectric
Fig. 1.2 The structure of the conventional floating gate nonvolatile memory
device. Continuous poly-Si floating gate is used as the charge storage element.
Fig. 1.3 Comparison between the poly-silicon floating gate memory and SONOS memory.
(a) Energy band diagram during retention in the poly-Si FG memory device. φ0 = 3.15 eV. (b) Energy band diagram during retention in the nitride trap-based memory. A typical Et value is between 0.8 to 1.1 eV below Ec . φ0 = 3.15 eV.
CHAPTER 2
Characteristics of Nanocrystal Flash Memory by Using PrO
2high- κ Material
2.1 Introduction
In this chapter, we try to fabricate nanocrystal nonvolatile memory by using a high-κ material which is praseodymium oxide (PrO2) as charge trapping centers. Now, PrO2 has investigated as an alternative high-κ gate dielectric material for silicon integrated circuits, which has outstanding dielectric properties. Some excellent characteristics can be summarized as follows: First, an effective dielectric constant value of around 30, independent of the substrate doping type. Second, relative low leakage current density with respect to HfO2 or ZrO2 film with the same effective oxide thickness (EOT), which can be explained by heavy electron masses in the oxide due to localized electrons forming the lowest conduction bands.
Third, PrO2 exhibits symmetrical band offsets larger 1 eV to Si. Fourth, praseodymium oxide exhibits excellent reliability characteristics based on measurements of current density as a function of gate voltage and stress induced leakage current (SILC), even after stresss-induced electrical breakdown. Fifth, there is no serious degradation in structural and electrical properties after annealing in CMOS typical process. For these superior characteristics better than other high-κ materials, making praseodymium oxide an attractive candidate as gate dielectric for next generation.
In this work, we have successfully fabricated a nonvolatile memory embedded PrO2
nanocrystals for the first time. This material provides high trapping state density, therefore large operation window can be achieved. The use of high-k material as nanocrystals can
reduce tunneling oxide and blocking oxide thickness, thus the operation voltage can be decreased and maintains superior retention characteristic, and improves memory device scaling down. It has good characteristics in terms of considerably large memory window, high program/erase speed, good endurance, and good disturbance.
2.2 Experimental Details
Figure 2.1 schematically describes the process flow of the PrO2 nanocrystal nonvolatile memory. The fabrication process of this memory device was started with LOCOS isolation process on a p-type, 5-10 Ω‧cm, (100) 150 nm silicon substrate. For the first step, a 2-nm-thick tunnel oxide was thermally grown at 925℃ in furnace system. A praseodymium oxide layer was subsequently deposited on the oxide by Dual E-gun Evaporation System with Praseodymium oxide targets. The deposition of praseodymium layer is a critical process to decide the size of the nanocrystal. E-gun deposition rate is relied on adjustment of the current magnitude by a remote control. After that, the wafer was subjected to RTA treatment in O2
ambient at 900℃ for 1 minute. When the film is RTA treated to provide enough energy and surface mobility, the thin Praseodymium oxide will self-assemble into a lower-total-enough state. An 15 nm blocking oxide was then deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) followed by a N2 densification process at 800℃ for 1 min. A 200-nm-thick poly-Si was deposited succeeding by LPCVD to serve as gate electrode.
Subsequently, gate patterning, S/D implanting, and the remaining standard CMOS procedures were completed to fabricate the PrO2 nanocrystal nonvolatile memory devices.
2.3 Results and Discussions
In this thesis, all devices described had dimensions of L/W = 1/10 µm, and the threshold voltage is defined when the Ids current reach 10-7 A in Ids-Vds curves.
2.3.1 Characteristics of Flash Devices
Figure 2.2 shows the Ids-Vds curve of the PrO2 nanocrystal nonvolatile memory device under fresh, programmed and erased states. Channel hot-electron injection and band-to-band hot-hole injection were employed for programming and erasing, respectively. The programming and erase time are both 10 ms, and a memory window of about 2V can be clearly observed. For Vg=Vd=10V, program time is also 10 ms, a memory window larger than 4V can be easily achieved. During programming, a small fraction of electrons in the substrate obtain enough energy from applied voltage Vd to surmount the barrier between oxide and silicon conduction band edges. These electrons can be trapped in PrO2 nanocrystals and the threshold voltage shift to right. When erasing, we applied a positive drain voltage Vd to generate hot hole in the subject and a large enough negative gate voltage to across the energy barrier. It reduces the threshold voltage and causes the Ids-Vds curve shift to left. We use this mechanism of adjust threshold voltage by different applied voltages to obtain memory characteristics.
The program and erase speed is shown in Fig. 2.3. The “Vt Shift” is defined as threshold voltage difference between the program state and erase state. Gate and drain terminals were biased equally from 7 to 10V. Both source and substrate terminals were biased at 0V. As shown in Fig. 2.3(a), program characteristics as a function of pulse width. With Vg and Vd
increasing, the Vth shift increases and the program speed becomes faster. The program time can be short as 1ms and a memory window of about 3V can be achieved for Vg=Vd=9V. Fig.
2.3(b) shows the erase characteristics of the PrO2 nanocrystal nonvolatile memory for different conditions: Vg=-3, -4, -5, -6V with the same Vd=7V. We can easily find similar phenomenon like programming, the Vth decrease faster as the applied gate voltage be more negative biased. Excellent erase speed of around 1ms can be obtain for Vg=-6V, Vd=7V. A more important thing must be mentioned, there is almost no over-erase situation took place.
This is owing to the fact that the vertical electric field decreases with decreasing amount of trapped electrons in the trapping layer during erasing and the hole injection into the trapping layer will reduce significantly [26].
Fig. 2.4 illustrates the retention characteristics of PrO2 nanocrystal memory devices for comparing different temperature (T=25℃、85℃ and 125℃). The retention time can be up to 108 seconds for 20% charge loss at room temperature, which is belived to be related to the deep trap energy level in the high-k nanocrystal [27]. Furthermore, the quality of the tunneling oxide plays a significant role in charge retention. It’s a pity that the retention go worst as the temperature increased [28]-[32].
The endurance characteristics after 105 P/E cycles of the PrO2 nanocrystal memory devices are shown in Fig. 2.5. The programming and erasing conduction are Vg=Vd=7V for 10ms, Vg=-6, Vd=9V for 10ms, respectively. Small amount increase of the threshold voltages in programmed and erased state can be observed. This is due to the mismatch between the localized spatial distributions for injected electron and holes by using channel hot-electron programming and band-to-band hot-hole erasing. The uncompensated electrons cause to increase the threshold voltage in erase state over P/E cycling [33]. For another reason, This may be the stress-induced electron traps generated in the tunneling oxide during cycling [34].
The cycling retention is also an important issue for memory. Fig. 2.6 shows the retention characteristics compare with fresh and 100K P/E cycled at 25℃. We can find that the charge loss behavior of the devices with 100K cycling is more serious than the other. This means the tunneling oxide damaged after 100K P/E cycling, thus stress-induced electron trapping in the tunneling oxide increases and the charge storage capability decreases, the retention characteristics go worst.
2.3.2 Characteristics of 2-bit Operation
Fig. 2.7 demonstrates the feasibility of 2-bit operation for the PrO2 nanocrystal memory devices. From the Ids-Vgs curves, we can employ forward and reverse reads for detecting the information stored in programmed bit1 and bit2, respectively. Table 3.1 summarizes suggested bias conditions for the 2 bits per cell operation. The retention characteristics for 2-bit operation is shown in Fig. 2.8. A memory window larger than 1.5 V until 108 seconds can be observed. Furthermore, we discovered that charge loss occurred both for programmed bit-1 and erased bit-2, it was represented that there is a vertical migration of the trapped electron [35].
2.3.3 Disturbance Measurement
Fig. 2.9 shows the programming drain disturb characteristics of the PrO2 memory. Drain disturbance may influence programmed memory to reduce the threshold voltage during programming. In our measurement, three different drain voltages (Vd=5, 7 and 9V) and Vg=Vs=Vb=0V were applied in the programming drain disturbance measurement at room temperature (T=25℃). We found that even after stressed at Vd=9V for 1000s, the program drain disturbance is not obvious (△Vt ＜ 1V).
Fig. 2.10 shows the gate disturb characteristics in the erasing state. While a cell is being programmed, gate disturbance may occur for the cells sharing a common word line. The applied gate voltage attracts electrons in the substrate to tunnel to the PrO2 nanocrystal, thus induce the threshold voltage to shift rightward. In this experiment, three different gate voltages (Vg=7, 8 and 9V) were applied to simulate the program situation which the cell unselected. A threshold voltage shift of only 0.3V at Vg=9V for 1000s was observed, it means that gate disturbance almost can be negligible.
Fig. 2.11 shows the read disturb characteristics in the erase state. For two bit operation,
the applied bit line voltage in reverse read must be sufficiently large (> 2V in our samples) to be able to “read through” the trapped charge in the neighbor bit. The voltage during read operation could cause unwanted electron injection, called “soft-programming” [36], induces erase state threshold voltage to convert into program state of the neighbor bit by the cumulative low level injections. There are two major factors causing the threshold voltage instability: the voltages of the word line and the bit line. The word line voltage during reading may enhance room temperature drift in the neighbor bit, and the bit line voltage during reading may cause unwanted channel hot electron injection and result in the threshold voltage shift subsequently. In our measurements, the gate voltage was applied at 4V, the drain voltages were applied at 2, 3 and 4V, respectively, both the source and the substrate were grounded. No apparent read disturbance is observed (△Vt ＜ 0.4V) for samples after stressing 1000s at 25℃.
2.4 Summary
In this chapter, we have investigated the memory effects and performance of the PrO2
nanocrystal memory devices. From our discussion, the memory has good characteristics in terms of large memory windows, low applied voltages, high program/erase speed, good retention at room temperature, excellent endurance, 2-bit operation and fine disturbances.
Consequently, PrO2 is a potential candidate for nanocrystal material in nanocrystal memory devices.
Fig. 2.1 Schematic cross section of the PrO2 nanocrystal memory device.
Ids-Vgs Curves
Vg (V)
0 2 4 6 8
Id (A)
1e-13 1e-12 1e-11 1e-10 1e-9 1e-8 1e-7 1e-6 1e-5 1e-4
Fresh
Program state Vg=7V, Vd=7V, 0.01s Erase state Vg=-6V, Vd=7V, 0.01s Program state Vg=10 V, Vd=7V, 0.01s
Fig. 2.2 Ids-Vds curves of the PrO2 memory. A memory window of larger than 2V can be achieved with Vg=Vd=7V programming operation.
Programming Speed
Programming Time (sec)
1e-7 1e-6 1e-5 1e-4 1e-3 1e-2 1e-1 1e+0
Vt Shift (V)
1e-7 1e-6 1e-5 1e-4 1e-3 1e-2 1e-1 1e+0
Vt Shift (V)
Fig. 2.3 (a) Program characteristics with different programming conductions. The program time can be short as 1ms and a memory window of about 3V can be achieved for Vg=Vd=9V.
(b) Erase characteristics for different erase conductions.
Retention Characteristics
Time (sec)
100 101 102 103 104 105 106 107 108
Normalized Vt shift (%)
0 20 40 60 80 100 120
250C 850C 1250C
Fig. 2.4 Retention characteristics of the PrO2 nanocrystal memory devices at T=25℃、85℃
and 125℃.
Endurance Characteristics
Cycles
100 101 102 103 104 105
Vt (V)
1 2 3 4 5 6
Erase state Vg = -6 V, Vd = 9 V, t = 10 ms Program state Vg = 7 V, Vd = 7 V, t = 10 ms
Fig. 2.5 Endurance characteristics of the PrO2 nanocrystal memory devices. Memory window maintains about 2.5V after 105 P/E cycles.
Retention Characteristics
Time (sec)
100 101 102 103 104 105 106 107 108
Normalized Vt shift (%)
0 20 40 60 80 100 120
Fresh 250C
100K P/E Cycled 250C
Fig. 2.6 Retention characteristics of PrO2 nanocrystal memory devices with fresh and 100K P/E cycled at 25℃.
Ids-Vgs Curves
Fig. 2.7 Ids-Vgs curves of the PrO2 nanocrystal memory devices in 2-bit per cell operation, forward read and reverse read for programmed bit 1 and programmed bit 2.
Program Erase Read
Table. 2.1 Suggested bias conditions for the 2 bits/cell memory operation of the PrO2
nanocrystal memory condition.
Retention Characteristics for 2-bit operation
Time (sec)
100 101 102 103 104 105 106 107 108
Vt (V)
2 3 4 5
Programmed bit-1 Erased bit-2 T = 25 0C
Fig. 2.8 Retention characteristics of the PrO2 nanocrystal memory devices for Programmed bit-1 and erased bit-2 at room temperature.
Drain Disturbance Characteristics
Fig. 2.9 Drain disturbance characteristics of the PrO2 nanocrystal memory devices. After 1000s stress at 25℃, only less than 1V drain disturbance be observed for Vd=9V condition.
Gate Disturbance Characteristics
Fig. 2.10 Gate disturbance characteristics of the PrO2 nanocrystal memory devices. After 1000s stress at 25℃, only less than 0.5V gate disturbance be observed for Vg=9V condition.
Read Disturbance Characteristics
Time (sec)
1 10 100 1000
Erase state Vt-shift (V)
-2 -1 0 1 2
Vg=4 Vd=2 Vg=4 Vd=3 Vg=4 Vd=4
Fig. 2.11 Read disturbance characteristics of the PrO2 nanocrystal memory devices. After 1000s stress at 25℃, only less than 0.4V read disturbance be observed for Vg=4V, Vd=4V condition.
CHAPTER 3
Characteristics of Nanocrystal Flash Memory by Using LaAlO
3high- κ Material
3.1 Introduction
The scaling down of silicon integrated circuits has pushed conventional SiO2 gate dielectric films close to its physical limit. When the SiO2 physical thickness becomes thinner than about 3 nm, direct tunneling through the dielectric barrier dominates the leakage current.
Substitution of silicon dioxide with high dielectric constant thin films as the gate dielectrics for sub-100 nm CMOS devices has received increasing attention [37]. Numerous materials are being considered as replacements for SiO2 as the gate dielectric in future MOSFETs. The materials most commonly proposed to replace SiO2 are metal oxides such as Ta2O5 [38], ZrO2
[39], HfO2 [40], TiO2 [41], etc. Unfortunately, until to now, none of the materials can meet all the requirements of alternative gate dielectric [37].
Lanthanum aluminate (LaAlO3) has been extensively used as the substrate and buffer layer for high-temperature superconductors [38]. It is well known that La2O3 has a high-dielectric constant and Al2O3 has a good thermal stability. LaAlO3, as a compound of La2O3 and Al2O3, may combine their desirable chemical and electrical properties while eliminating the deficiencies of each material. It seems that LaAlO3 may have a great potential as an alternative gate dielectric material to replace SiO2 in next-generation MOSFET application.
In this work, we have successfully fabricated a nonvolatile memory embedded LaAlO3
nanocrystals for the first time. This material provides high trapping state density, therefore large operation window can be achieved. The use of high-κ material as nanocrystals can
reduce tunneling oxide and blocking oxide thickness, thus the operation voltage can be decreased and maintains superior retention characteristic, and improves memory device scaling down. It has good characteristics in terms of considerably large memory window, high program/erase speed, good endurance, and good disturbance.
3.2 Experimental Details
Figure 3.1 schematically describes the process flow of the LaAlO3 nanocrystal nonvolatile memory. The fabrication process of this memory device was started with LOCOS isolation process on a p-type, 5-10 Ω‧cm, (100) 150 nm silicon substrate. For the first step, a 2-nm-thick tunnel oxide was thermally grown at 925℃ in furnace system. A lanthanum aluminate (LaAlO3) film was subsequently deposited on the oxide by Dual E-gun Evaporation System with lanthanum aluminate targets. The deposition of lanthanum aluminate is a critical process to decide the size of the nanocrystal. The deposition rate of Dual E-gun Evaporation System is relied on adjustment of the current magnitude by a remote control. After that, the wafer was subjected to RTA treatment in O2 ambient at 900℃ for 1 minute. When the film is RTA treated to provide enough energy and surface mobility, the thin lanthanum aluminate film will self-assemble into a lower-total-enough state. An 15 nm blocking oxide was then deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) followed by a O2
densification process at 800℃ for 1 min. A 200-nm-thick poly-Si was deposited succeeding by LPCVD to serve as gate electrode. Subsequently, gate patterning, S/D implanting, and the remaining standard CMOS procedures were completed to fabricate the LaAlO3 nanocrystal nonvolatile memory devices.
3.3 Results and Discussion
In this thesis, all devices described had dimensions of L/W = 1/10 µm, and the threshold
voltage is defined when the Ids current reach 10-7 A in Ids-Vds curves.
3.3.1 Characteristics of Flash Devices
Figure 3.2 shows the Ids-Vds curve of the LaAlO3 nanocrystal nonvolatile memory device under fresh, programmed and erased states. Channel hot-electron injection and band-to-band hot-hole injection were employed for programming and erasing, respectively. The programming and erase time are both 1 ms, and a memory window of about 4V can be clearly observed. For Vg=Vd=10V, program time is also 1 ms, a memory window larger than 5.5V can be easily achieved. During programming, a small fraction of electrons in the substrate obtain enough energy from applied voltage Vd to surmount the barrier between oxide and silicon conduction band edges. These electrons can be trapped in LaAlO3 nanocrystals and the threshold voltage shift to right. When erasing, we applied a positive drain voltage Vd to generate hot hole in the subject and a large enough negative gate voltage to across the energy barrier. It reduces the threshold voltage and causes the Ids-Vds curve shift to left. We use this mechanism of adjust threshold voltage by different applied voltages to obtain memory characteristics.
The program and erase speed is shown in Fig. 3.3. Gate and drain terminals were biased equally from 7 to 10V. Both source and substrate terminals were biased at 0V. As shown in Fig. 3.3(a), program characteristics as a function of pulse width. With Vg and Vd increasing, the Vth shift increases and the program speed becomes faster. The program time can be short as 0.1ms and a memory window of about 3V can be achieved for Vg=Vd=9V. Fig. 3.3(b) shows the erase characteristics of the LaAlO3 nanocrystal nonvolatile memory for different conditions: Vd=6, 7 ,8V with the same Vg=-3V. We can easily find similar phenomenon like programming, the Vth decrease faster as the applied drain voltage be more positive biased.
Excellent erase speed of around 0.1ms can be obtain for Vg=-3V, Vd=8V. The same phenomenon mentioned in the preceding chapter can be observed, the over-erase situation
don’t take place. The smaller voltage be applied at the gate terminal of the LaAlO3
nanocrystal memory devices, the vertical electric field decreases with decreasing amount of trapped electrons in the trapping layer during erasing and the hole injection into the trapping layer will reduce significantly.
Fig. 3.4 illustrates the retention characteristics of LaAlO3 nanocrystal memory devices for comparing different temperature (T=25℃、85℃ and 125℃). The retention time can be up to 108 seconds for 20% charge loss at room temperature, which is belived to be related to the deep trap energy level in the high-k nanocrystal [27]. Furthermore, the quality of the tunneling oxide plays a significant role in charge retention.
The endurance characteristics after 104 P/E cycles of the LaAlO3 nanocrystal memory devices are shown in Fig. 3.5. The programming and erasing conduction are Vg=Vd=7V for 0.1ms, Vg=-7, Vd=8V for 1ms, respectively. Small amount increase of the threshold voltages in programmed and decrease of those in erased state can be observed. This is due to the mismatch between the localized spatial distributions for injected electron and holes by using channel hot-electron programming and band-to-band hot-hole erasing. The uncompensated electrons cause to increase the threshold voltage in erase state over P/E cycling [33]. For another reason, This may be the stress-induced electron traps generated in the tunneling oxide during cycling [34].
The cycling retention is also an important issue for memory. Fig. 3.6 shows the retention characteristics compare with fresh and 10K P/E cycled at 25℃ and 85℃, respectively. We can
The cycling retention is also an important issue for memory. Fig. 3.6 shows the retention characteristics compare with fresh and 10K P/E cycled at 25℃ and 85℃, respectively. We can