Chapter 1 Introduction
1.5 Organization of the Thesis
In thr Chapter 1, an introduction about the general background and the scaling challenge of nonvolatile memory devices are described. Moreover, we also introduce the alternative structures (ex. SNOS, SONOS, Nano-crystal memory, TANOS and BE-SONOS) for the purpose of the scaling limits and of the conventional FG. At last, we introduce the motivation of our study.
In the Chapter 2, we report the process of TFT-NVSM with different morphology, channel thickness, and crystal condition. In addition, the measurement condition (such as programming, erasing, retention and disturbance) and the parameter definitions are also presented in this chapter.
In the Chapter 3, the detail study about the TFT-SONOS devices with different morphology, channel thickness, and crystal condition. First, we discuss the P/E efficiency, second the Transistor Performance (Id-Vg, Id-Vd, threshold voltage, transconductance and subthreshold swing), at last we analyze the leakage current.
In the Chapter 4, we study the reliability issues such as retention, gate disturbance and drain disturbance with different morphology, channel thickness, and crystal condition.
Finally, in the Chapter 5, conclusions of this dissertation and recommendation for further research are presented.
8
Table 1.1 The application of NVSM
9
Table 1.2 The NVSM technology requirements for NAND-type Flash memory in ITRS 2011 [1.9]
Table 1.3 The NVSM technology requirements for NOR-type Flash
memory in ITRS 2011 [1.9]
10
Fig 1.1 Cross-section view of the first non-volatile semiconductor memory with a floating gate in 1967.
Metal Gate
Insulator
Insulator
Silicon Substrate
e -e
-e- e- e- e
-Floating Gate
Source Drain
Fig. 1.2 Market share of three NVSM products from year
2000 to 2011, and projected to 2020 [1.8].
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Fig 1.3 Current-voltage curves of a floating-gate memory device when there is no charge stored in the floating-gate (curve A) and when a negative charge Q is stored in the floating-gate (curve B).
Fig 1.4 Current-voltage curves of a floating-gate memory device
when there is no charge stored in the floating-gate (curve A) and
when a negative charge Q is stored in the floating-gate (curve B).
12
Fig. 1.5 Design space analysis for floating gate NOR-type Flash.
(a) Design space vanishes for 90nm node device. (b) Design space
vanishes for 45nm node devise. [1.4]
13
Fig. 1.6 Silicon-nitride-oxide-silicon (SNOS).
Poly-Silicon Gate
Nitride Oxide
Silicon Substrate
Source Drain
Fig. 1.7 Silicon-Oxide-Nitride-Oxide-Silicon (SONOS).
Fig. 1.8 Nanocrystals memory
Oxide Poly-Silicon Gate
Oxide
Silicon Substrate
Source Drain
Nanocrystals
Oxide Poly-Silicon Gate
Nitride Oxide
Silicon Substrate
Source Drain
14
Fig. 1.10 Band-gap engineered SONOS (BE-SONOS)
TaN Gate
Nitride Oxide
Silicon Substrate
Source Drain
Al2O3
Fig. 1.9 TaN gate- Al
2O
3blocking-oxide-nitride-tunneling oxide-silicon (TANOS)
Oxide
O
O N
Poly-Silicon Gate
Nitride
Silicon Substrate
Source Drain
Ultra-thin ONO
15
Chapter 2
Device Fabrication and Experimental Setup
2.1 Introduction
In the previous chapter, we presented the invention of nonvolatile memory and alternative structures of FG memory. In order to realize the system-on- panel (SOP) and system-on-chip (SOC), integrating NVSM into the thin film transistor (TFT) digital circular is necessary. Unlike single crystal NVSM, TFT device has the poly-Si channel and rougher interface morphology, but it had been not completely studied in literature. In this chapter, we report the process of TFT with different morphology, channel thickness, and crystal condition. Moreover, the measurement condition such as programming, erasing, retention and disturbance are also presented in this chapter.
2.2 Experimental Procedure
Fig. 2.1 shows the fabrication process of the devices for this work. A 6-in (100) silicon wafer was adopted as the base substrate. First, the 500-nm thermal oxide was grown on silicon wafer by standard furnace. The a-Si layer was deposited by low-pressure chemical vapor deposition (LPCVD) with the thickness 50, 100, 150-nm (Fig. 2.1-(a)), and then wafers were annealed for 24 hour at 580, 600 and 620 °C(Fig. 2.1-(b)). Some samples were grown dry-oxide 10, 20 and 40-nm, and removed it by HF solution. After defining the active regions (Fig. 2.1-(c)), the ONO tri-layer were formed by LPCVD with the tunneling oxide 13-nm, nitride 14-nm and blocking oxide 24-nm. Next, 150-nm n+ polysilicon as the gate electrode was deposited and implanted with phosphorous (40keV at 5×1015 cm-2) (Fig.
2.1-(d)). After gate electrode patterning (Fig. 2.1-(e)), source/drain were implanted with phosphorous (20keV at 5×1015 cm-2) by self-aligned method and activated at 600 °C for
16
24-hr annealing in an N2 ambiance (Fig. 2.1-(f)). The 500-nm TEOS oxide as the passivation layer was deposited (Fig. 2.1-(g)), and the contact hole was patterned. Finally, the 600-nm Al-Si-Cu pad was deposited and patterned to finish the process of TFT-SONOS fabrication. The TFT-SONOS memory structure cross section is illustrated in Fig. 2.1-(h). All process splits are showed in the Fig. 2.2.
Furthermore, in order to discuss the memory characteristic with different morphology, the different thickness dry oxide were grown and removed by HF. Because of the material characteristics, dry oxide would be grown along grain boundaries. As a result, we could get different morphology by growing different thickness dry oxide and removing it. The process is illustrated in Fig. 2.3.
2.3 Measurement and Equipment Setup
The measurement setup of this TFT-SONOS device is illustrated in Fig. 2.4, including the electrical characterization system characterization system (KEITHLEY 4200), two channel pulse generator (Agilent 81110A), low leakage current switch mainframe (KEITHLEY 708A) and the probe station.
KEITHLEY 4200 equipped with programmable source-monitor units (SMU) and provides a high current resolution to pico-ampere range to facilitate the current measurement. Agilent 81110A with two pulse channels provides the high timing resolution pulse for the P/E characterization of nonvolatile memory. KEITHLEY 708A configured a 10-input×12-outpute switching matrix, that can switches the signals from the KEITHLEY 4200 and Agilent 81110A when the devise is measured in probe station. Moreover, the C++
language is used to achieve the control of the devise measurement instruments.
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2.4 Method of Device Parameter Extraction
In this section, the definition of electrical parameters are introduced, including the threshold voltage (Vth), subthreshold swing (S.S), and maximum transconductance (Gm,max).
2.4.1 Threshold Voltage
In this thesis, by fixing drain current method Id=Idn×(W/L) where Idn is a normalized drain current, the threshold voltage (Vth) is defined as Vg when Idn=10nA. This definition can avoid the ambiguity associated with devices where the effective mobility depends strongly on the gate bias, based on the surface bend bending on the identical gate bias of all devices are the same.
2.4.2 Subthreshold Swing
Depending on the gate and source-drain voltages, the MOSFET Id-Vg curve can be identified as three regions, including the sub-threshold region, saturation region and linear region. In the sub-threshold region, the most important parameter is sub-threshold swing, because it describes how a MOSFET device switches off.
The sub-threshold swing (S.S.) is defined as the reciprocal of slope of the logarithmic scale Id-Vg curve in the sub-threshold region and as the amount of gate voltage required to upgrade drain current by one order of magnitude. The previous study had reported that S.S.
is closely related to the trap states located near the mid-gap (deep states), which originate from dangling bonds and the mobility is associated with the trap states near the band edge (tail state) [2.1-2.2]. Therefore, the S.S and mobility properties are effective to determine the deep state density and tail state density, respectively.
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2.4.3 Transconductance
Transconductance (Gm) is the guide to obtain the field effect mobility. There are three stages for Gm-Vg curve (Vd=constant). First stage is drain current in the saturation region (Vg>Vt and Vd>Vd,sat=Vg-Vt), which is proportional to quadratic of Vg-Vt as the eq. 2-1, so interface, so that the mobility would degradation by surface roughness scattering. As this result, Gm has the maximum at the transition between linear region and saturation region (Vd=Vd,sat=Vg-Vt) as shown in eq. 2-5.
Gm,max ≡∂V∂Id
g =WLμFECoxVd ………...………..(eq. 2-5) In this work, KEITHLEY 4200 is adopted to extract gm. By finding out the Gm,max, we can compare the field effect mobility of all samples as eq. 2-5.
2.5 Operation and Characteristic of Memory
Generally, non-volatile memory device interprets the programmed state “1” and the erase state “0” by threshold voltage. Data was stored successfully by trapping charges in the floating gate, and the definition of memory window is the change of threshold voltage between the programmed state and erased state as show in Fig. 2.5. This section we will
19
introduce P/E mechanism and characteristics of retention.
2.5.1 Program Mechanism
There are wide varieties of program principles of NVM. Fowler-Nordheim (FN) injection [2.3]-[2.5] and channel-hot electron (CHE) injection [2.6]-[2.8] are prevailing in modern nonvolatile industry. For FN tunneling programming, the positive bias is applied to the gate terminal during the programming and the voltage drop across the tunneling oxide make the electric field more than 6MV/cm. The electrons would be injected from channel into trapping layer. The main drawback of FN tunneling mechanism is slower programming speed, compared to CHE, due to lower tunneling current [2.9].
On the other hand, for the CHE, the carriers are accelerated by the horizontal electric field in the channel and obtain high energy in the program process. Therefore, impact ionization would generate electron-hole pairs near drain side, and then the high energy hot electron could be injected into trapping layer by the vertical electric field. Compare to the FN mechanism, CHE has faster program speed and smaller program voltage, but CHE injection causes the tunneling oxide damage near the drain side.
In this thesis, we adopted the FN injection to program. Because the voltage of channel are identical in the inversion mode, the programming condition (Vg=20 V, Vs=Vd=-15V) is identical to Vg = 35 V as shown in the Fig. 2.6.
2.5.2 Erase Mechanism
SONOS-type NVM device has two common kinds erasing mechanism:
Fowler-Nordheim (FN) tunneling and band to band hot holes (BTBHH) injection. For FN tunneling erasing, the negative bias is applied to the control gate and the electron would detrap from the trapping layer. Like programming, the drawback of FN tunneling erasing is the slower erase speed [2.9].
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There is another common erasing method, Band-to-Band tunneling Hot-Hole (BTBTHH). The negative bias and positive bias are applied to control gate terminal and drain terminal during the erasing, respectively. When the negative gate bias is large enough, the band banding of the drain would become sufficient to generate electrons and holes.
Then, the generated holes gain enough energy due to high electrical field and would inject to the trapping layer. BTBHH erasing mechanism has faster erase speed than FN erasing mechanism, but the high energy hot holes injection would cause tunneling oxide reliability issues.
There is another prevailing erasing method, called substrate transient Hot-Hole (STHH) injection. The STHH injection mechanism makes electron/hole pair by changing the junction bias of source/drain-substrate into reverse bias instantaneously. When the junction of S/D and substrate are switch to the reverse bias, a fast discharge and hot carriers are generated by the transient avalanche junction breakdown. Afterward, the hot holes would be extracted with negative gate bias and injection into trapping layer [2.10].
To obtain more uniform holes injection and high erasing speed and avoid gate injection, we adopt the erasing condition (Vg=-9V, Vs=Vd=15V) as shown in Fig.2.7. There are three mechanisms FN, BTBHH and STHH used in our erase condition. First, smaller negative bias can avoid gate injection but degrade FN efficiency. As a result, we apply the positive bias to the source/drain terminal, BTBHH injection would help to erase efficient.
Moreover, STHH injection occurs significantly as source/drain bias be applied.
2.5.3 Characteristic of Retention
For SONOS-type NVM, data retention is an important reliability issue. The previous study had reported that retention capability of SONOS memories has to be checked by using accelerated test such that high electric fields or high temperature [2.11]. In this work, we discuss data retention characteristic after programming with three different
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temperatures, 25 °C, 75 °C and 125 °C. By way of measure the Vt variation, we can find out the amount of the excess trapping electrons.
2.5.4 Disturb Characteristics
Fig. 2.11 schematically shows the array of NAND architecture. In order to execute programming and erasing with our condition, the common source lines are adopted into this NAND architecture, and the common source voltage is called Vcs. It is known from the literature that the disturbance problems including program disturbance, erase disturbance and read disturbance [2.12][2.13]. The disturbed phenomenon of programming happened to the common word-line device called gate disturbance makes the electrons tunneling into the trapping layer and causes threshold voltage fluctuation. Another gate disturbance situation is that the trapped electrons tunnel from the trapping layer to the control gate via the defects located in the blocking oxide, while the applying voltage of gate terminal is large.
On the other hand, the read disturbance happened to the common bit-line device is called drain disturbance. The drain bias may force electrons to inject into the trapping layer, resulting in unacceptable threshold voltage increase.
In this thesis, the disturbance problems are shown in Fig 2.8. In cell B, high gate voltage stress is generated by the common word-line during the programming of cell A (VWLn =Vg =20 V and VBLi =Vd =Vcs =Vs = -15 V), resulting in the gate disturbance.
Moreover, the cell C meets the drain disturbance by the common bit-line during the erasing of cell A (VWLn =Vg =-9 V and VBLi=Vd =Vcs =Vs =20 V). Because the reading drain bias (Vd=0.1) is far less than erasing drain bias, we would not discuss the drain disturbance during the reading state.
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(a) Thermal oxide was grown on silicon wafer and the a-Si layer was deposited by low-pressure chemical vapor deposition (LPCVD) with thickness 50, 100, 150-nm.
(b) SPC annealed for 24 hour at 580, 600 and 620
°C.
(c) Defining the active regions.
(d) The ONO tri-layer were formed by LPCVD and
150-nm n+ polysilicon as the gate electrode was
deposited and implanted with phosphorous (40keV
at 5×10
15cm
-2).
23
(f) Source/drain were implanted with phosphorous.
(e) Gate electrode patterning.
(g) TEOS oxide as the passivation layer was deposited.
24
Fig. 2.1 Schematic of the experimental processes for fabricating TFT-nonvolatile memory.
Fig. 2.2. Schematic of the fabrication process.
Thermally oxidized wafer
(h) Cross-section of TFT-SONOS memory structure.
25
Fig. 2.3. The schematic of the oxidation and HF wet etching
process. (a) The original channel film. (b) After oxidation
process. (c) After HF wet etching process.
26
Fig. 2.5 Current-voltage curves of a NVSM device, when there is no charge stored in the floating-gate (curve A) and when the negative charges are stored in the floating-gate (curve B).
Fig. 2.4 The experimental setup of each apparatus for pulse generator
and I-V characteristics measurement of memory cell.
27 Si-Substrate
Wet-Oxide Poly-Si-Channel
Blocking-Oxide
Gate
Drain Sorce
Tunneling-Oxide Nitride
e
-e
-e
-e
-e
-e
-e
-V
g(+20)
V
d(-15) V
s(-15)
Fig. 2.7 The schematic mechanism of our erasing condition, purple lines are FN hole injection, green lines are band-to-band-hot-hole injection and blue lines are substrate-transient-hot-hole injection.
Fig. 2.6 The schematic mechanism of FN tunneling by our programming
condition.
28
Fig. 2.8 The equivalent circuits schematic of the memory cell. During Cell
A is programmed, the gate disturbance takes place in Cell B and the drain
disturbance takes place in Cell C.
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Chapter 3
Characteristics of TFT Nonvolatile Memory
3.1 Introduction
The significant demands of nonvolatile memory device are the programming/erasing efficiency and data retention. However, the studies of poly-TFT nonvolatile memory with different channel condition are investigated rarely. In this chapter, the P/E efficiency and electrical characteristics of poly-TFT with different channel condition were studied. First, we discuss the effect of interface morphology by oxidation process. Second, the poly-silicon channel thickness dependence would be reviewed, too. At last, the effect of annealing temperature would be discussed. The P/E conditions are showed in Table 1 and all splits of fabrication processes are showed in Table 2.
3.2 Interface Morphology Dependence 3.2.1 Atomic Force Microscopy (AFM) Analysis
In order to investigate the relation between interface morphology and P/E efficiency, dry-oxide (10, 20 and 40-nm) were grown and removed by HF. The morphology of poly-Si channel after removing dry-oxide is shown in Fig. 3.1. Root-Mean-Square (Rms) of samples is 0.375-nm, 0.788-nm, 1.013-nm and 1.647-nm, respectively. Obviously, the thicker the dry oxide grown on poly-Si initially, the rougher the morphology becomes.
This is due to thermal oxide would grow along the grain boundary, leading to the rougher morphology after removing the dry-oxide. As a result, different oxidation conditions can effectively alter the poly-Si channel property.
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3.2.2 Program/Erase Characteristics
Fig. 3.2 show the memory programming speed at Width/ Length = 10μm/ 10μm, and the programming voltage were at Vg =20 V and Vs= Vd= -15 V. As it expected, rougher morphology enhances the memory program speed. This is attributed to that the rougher morphology leads to a smaller conduction area and higher localized electric field, subsequently causing a higher electron trapping rate [3.1]-[3.2].
Fig. 3.3 show the memory programming speed at Width/ Length = 10μm/ 10μm, and the programming voltage were at Vg = -9 V and Vs= Vd= 20 V. Unlike programming, the trend for the erase state was not observed. This is attributed to the different barrier height and effective mass of the electron and hole are responsible for the different trend of P/E speed induced by morphology.
3.2.3 Transistor Performance
Fig. 3.4 shows the Id-Vg and Gm-Vg characteristics with different oxidation thickness and the electrical parameters are showed in Table 3.3. Fig. 3.5 shows the drain current–
drain voltage (Id-Vd) characteristics with different oxidation thickness for different Vg
overdrive voltage (0, 3, 6 and 9 V). These results indicate that sample B has the smallest threshold voltage, steepest subthreshold swing and highest on-state current. In addition, the electrical analyses such as Vth, subthreshold swing, and maximum Gm were performed and shown in Fig. 3.6, 3.7 and 3.8, respectively.
Sample B exhibits the better performance (S.S., Vth and Gm,max) than the control sample due to the additional oxidation step which causes the secondary grain growth [3.3]-[3.4], that reduces both interface and intra-grain defects. However, as the oxidation time is increased for sample B and C, the roughness scattering would counteract the secondary grain growth and degrades the mobility. Moreover, the rougher morphology
31
causes more interface defects, so that the subthreshold swing became poorer. These results were similar to previous reports [3.5]. On the other hand, it is observed that sample A and B have more obvious kink current than sample C and D in Fig.3.5. This observation can be possibly ascribed to that the thicker oxidation sample has the thinner poly-silicon channel.
Thus, the thinner poly-Si channel exhibits relatively fully deplete at saturation operation, leading to suppress kink effect [3.6].
3.2.4 The Comparison of Off-Leakage
We investigated the relation between minimum current and drain bias in Fig. 3.9 and Fig. 3.10. In this work, Vg,min represents the gate voltage that causes the minimum drain current (Id,min). The strong observed dependence of the leakage on Vg,min and Vd implies that trap assisted GIDL dominates the leakage current.
Fig. 3.9 shows sample A has higher Vg,min, meaning it’s more easy to generate GIDL current at the low voltage drop Vdg. Moreover, we also observed that Id,min would become lower by enhancing the oxidation thickness in Fig. 3.10. This observation can be possibly ascribed to that oxidation samples (sample B, C and D) have the extra secondary grain growth step, reducing the inter grain defect as well as trap assisted GIDL effect. Therefore, sample D has the lowest Id,min and Vg,min.
3.3 Channel Thickness Dependence 3.3.1 X-ray Diffraction (XRD) Analysis
Fig. 3.11 shows the X-ray diffraction (XRD) results of poly-silicon channel with different channel thicknesses (50, 100 and 150 nm)
.
As the results, poly-Si grain size would be enhanced by using thicker a-Si channel based on the same thermal budget. This is attributed to that thicker a-Si channel has larger space for grain growth.32
3.3.2 Program/Erase Characteristics
Fig. 3.12 and 3.13 show the P/E speed with different poly-silicon channel thickness. It was showed that no significant difference in the program state; However, the sample- G with the thinnest poly-Si thickness has the slowest erase speed.
This observation can be possibly ascribed to the different mechanisms of programming and erasing. For the programming state, the programming condition as FN-programming (Vg=20 V, Vs=Vd=-15V), is only dependent on the intensity of vertical electrical. Thus, we believe that although thicker poly-silicon channel devices with larger grain size can exhibit the higher horizontal electrical field, but no significant different vertical electrical fields at the interface based on the result. Therefore, there are no significant differences for the programming speed.
On the other hand, there are three different mechanisms of our erasing condition (Vg=-9V, Vs=Vd=15V), including FN, BTBHH and STHH, are shown in Section 2.5.2.
FN-erasing efficiency depends on the vertical electrical field, BTBHH-erasing efficiency is dominate by the voltage-drop between gate and drain terminal, and STHH-erasing efficiency is dependent on the junction bias between the source/drain and substrate. Using the same doping and S/D annealing condition, thicker channels would have deeper junction depth, resulting higher quantity of electron-hole pair generation of the substrate transient effect. Therefore, thicker channel devices have higher erasing speed by STHH mechanism.
However, the erasing speed have no significant differences between sample H and A, meaning that these samples exhibit the comparable junction depth. In other words, the effective junction depth may be saturated, as the channel thickness we adopted beyond a critical thickness.
3.3.3 Transistor Performance
Fig. 3.14 shows the Id-Vg and Gm-Vg characteristics with different channel thickness
33
and the electrical parameters are showed in Table 3.4. Fig. 3.15 shows the drain current–
drain voltage (Id-Vd) characteristics for different Vg overdrive voltage (0, 3, 6 and 9 V).
Obviously, sample A has the best drain current in saturation range and the largest maximum transconductance.
Fig. 3.16, 3.17 and 3.18 show the electrical characteristics for samples with different channel thickness. The thicker the channel film of the device, the higher trans-conductance would be observed (Fig. 3.18). This observation can be possibly ascribed to that thicker polysilicon has larger grain size. It not only reduces grain boundary density but also decreases the grain-barrier height [3.7]. Also, there are two mechanisms that could explain the Vth and subthreshold swing degradation related to sample-H. The first mechanism is related to the fully depletion below 100-nm [3.8]. The second possible mechanism is related to the larger grain size above 100-nm. On the other hand, thinner channel device (sample G and H) can reduce kink effect current significantly and the results are shown in Fig. 3.15 [3.9].
3.3.4 The Comparison of Off-Leakage
Fig. 3.19 and Fig. 3.20 show the characteristics of minimum current with different channel thickness. The gate voltage corresponding to minimum current at fixed drain bias for sample G is higher than others, meaning that thin channel device possesses smaller grain size and higher inter grain defects.
However, there is another mechanism affecting Id,min. The thicker the channel thickness of device, the deeper junction depth would be obtained by the same junction annealing temperature. Therefore, although thicker channel device has larger grain size that reduce the inter grain defects, but the deeper junction would result higher leakage current.