Chapter 4 Reliability of TFT Nonvolatile Memory
4.3 The Comparison of Disturbance Characteristics
The disturbance phenomena happen in memory array operation. Generally disturbance issues are classified for two category, word line disturbance (gate disturbance) and bite line disturbance (drain disturbance).
Fig. 4.5-4.10 show the gate and drain disturbance characteristics. The result indicates that threshold voltage diversification for gate disturbance has two steps, Electrons detrap from the blocking oxide for 100-101 sec and electrons inject into trapping layer by FN-tunneling through the tunneling oxide for 101-102 sec. On the other hand, drain disturbance also has two steps, band-to-band-hot-holes inject from the tunneling oxide into
57
the trapping layer at 100-101 sec and gate injection electrons pass the blocking oxide at 101-102 sec. This observation can be possibly ascribed to the poor blocking oxide quality of devices that makes to trap-assistance electrons turn out (or in) of trapping layer and results in different impacts on gate and drain disturbance.
Fig. 4.5 and Fig. 4.6 show the gate and drain disturbance characteristics for different interface morphology devices
.
Significantly, rougher interface morphology causes the severe gate disturbance issue by both trap-assistance electrons loss and FN-tunneling injection range. This is attributed to the rougher morphology causes higher vertical electron filed, enhancing the probability of electron tunneling (injection or losing). On the other hand, the slight drain disturbance has the similar phenomenon for gate disturbance. This is attributes to the hole injection mechanism is band-to-band tunneling injection, only depended on the vertical electron filed for the overlap range between drain and gate.Therefore, the gate disturbance issue is more significant than drain disturbance issue for rougher interface morphology.
Fig. 4.7 and Fig. 4.8 show the gate and drain disturbance characteristics for different channel thickness devices. Fig. 4.9 and Fig. 4.10 show the gate and drain disturbance characteristics for different SPC temperature devises. There are no significant differences between all of these devices. This observation can be possibly ascribed to that disturbance charge injection/loss efficiency is dominated by vertical electron field. As the examination of chapter 3, the dependence of grain size and vertical electron field is not significant.
Therefore, we can’t find significant difference here.
4.4 Summary
In this chapter, we discuss the characteristics of retention, word line disturbance (gate disturbance) and bite line disturbance (drain disturbance). In section 4.2, we observe that
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rougher morphology cause the degraded oxide quality by higher electron field in program state, resulting in the degradation of retention. Moreover, the relationship between SPC temperature and device retention is not found in this work. On the other hand, thicker channel devices show the slightly degraded retention issue (advanced studies are planned).
In the section 4.3, we discuss the disturbance issue and explain the mechanisms of gate/drain disturbance for our TFT-NVSM devices. These results indicate that rougher interface morphology causes the more obvious disturbance issue. On the other hand, we don’t observe significant difference of the disturb issues for changing channel thickness and SPC temperature.
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Table 4.1 Voltage conditions utilized during the reliability analysis of the
TFT nonvolatile memory.
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Fig. 4.1 Retention characteristic for different morphologies at different temperature (a)25 °C, (b)75 °C, and (c)100 °C.
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channel thicknesses at different temperature (a)25
°C, (b)75 °C, and (c)100 °C.
62
Wet-Oxide
W
ONO G
Si
Wet-Oxide
W
ONO G
Si (a)
(b)
Fig. 4.3 The schematic of the channel edge damage. (a) The
device with channel film 50 nm. (b) The device with channel
film 150 nm.
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Fig.4.4 Retention for samples with different annealing
temperature at different temperature (a)25 °C, (b)75 °C, and
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Fig.4.5 Gate disturbance for different interface morphologies.
Fig.4.6 Drain disturbance for different interface morphologies.
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Fig.4.7 Gate disturbance with different channel thicknesses
Fig.4.8 Drain disturbance with different channel thicknesses.
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Fig.4.10 Drain disturbance with different annealing temperature.
Fig.4.9 Gate disturbance with different annealing temperature.
10
-710
-610
-510
-410
-310
-210
-110
010
110
267
Chapter 5
Conclusions and Future Work
5.1 Conclusions
In this thesis, we have completely studied the impacts of interface morphology, channel thickness and SPC temperature for TFT-nonvolatile memory. In addition, we successfully make the different morphology by the oxidation process and found that thicker poly-silicon channel has the larger grain by SPC process based on the AFM result.
Rougher morphology device enhances the programming efficiency, but resulting in the reliability issue and worse electrical characteristics. Moreover, the extra oxidation process improves the electrical characteristics by reducing inter grain defects. However, we don’t find any significant difference for the erasing efficiency. (Table 5.1)
Thicker channel device enhances the erasing efficiency but makes no significant improvement on the programming efficiency and reliability issues. On the other hand, thicker channel device effectively enhances the performance by larger grain size but results in higher off-leakage by deeper junction. (Table 5.2)
Furthermore, lower SPC temperature (580
°C
) exhibits the best electron characteristics by larger grain size. However, SPC temperature exhibits lower impacts on the nonvolatile memory. As a result, optimizing SPC temperature is a promising way to improve LTTFT performance without any degradation of NVSM. (Table 5.3)5.2 Future Work
In this work, we clarify the impacts of oxidation on transistors and nonvolatile memory. However, this experiment is not based on the same thermal budget. Thus, we find the difficulties decoupling the intrinsic roughness effect from different grain size generated
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by different thermal budget. Therefore, in order to investigate roughness effect more systematically, we will study the roughness effect based on the same thermal budget.
Moreover, floating gate application currently is still a prevailing for industry application, although SONOS has the potential to improve the retention characteristics. Thus, we will study the impacts of roughness on nonvolatile memory for SONOS and floating gate structure.
Moreover, plasma discharge and hydrogen-rich nitride capping are promising method to optimize TFT. However, a conclusive understanding of the impacts of these methods on nonvolatile memory is missing. Thus, investigating the hydrogen that can alter the P/E speed, retention, and disturbance are interesting.
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Table 5.1 The comparison of different interface morphology devices.
Table 5.2 The comparison of different channel thickness devices.
Table 5.3 The comparison of different SPC temperature devices.
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