Chapter 1 Introduction
1.4 Organization of the Thesis
In the following sections, we will show our research efforts.
In Chapter 2, the fabrication process and electrical characteristics of poly-Si TFTs using a buffer a-Si layer beneath the channel and devices with anneal procedure after gate oxide deposition will be proposed. Experimental results reveal that the
performance and reliability of our devices have remarkable improvement in comparison with conventional TFTs. Additionally, we made a detail discussion to explain the results of our experiment.
In Chapter 3, we discuss the reliability issues of p-channel TFTs and n-channel TFTs under NBTI and PBTI, respectively. Experimental results reveal that the mechanisms of NBTI and PBTI are quite different from each other. NBTI and PBTI also caused different degradation on p-TFTs and n-TFTs, respectively. We will make a detail discussion between the NBTI and PBTI.
In Chapter 4, the passivation phenomenon under dynamic negative-bias temperature stress (DNBTS) will be investigated by applying different stress gate biases, different stress frequencies, and different passivation voltages under different temperatures. Then, we will analyze the degradation and passivation mechanisms under DNBTI from our experimental results.
In the end of this thesis, we will make conclusions in Chapter 5.
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Chapter 2
Characteristics of Low Temperature Poly-Si TFTs Using a Bi-layer Poly-Si channel
2.1 Introduction
In recent years, polycrystalline silicon thin-film transistors (poly-Si TFTs) have been used to realize the integration of driving circuits and pixel switching elements on a single glass substrate in active matrix liquid crystal displays (AMLCDs) [1]-[3], and also attracted much attention for the potential to accomplish the System-on-Panel (SOP) [4]. Both high-performance and high-reliability poly-Si TFTs are required to accomplish this goal. However, it is known that trap states in poly-Si channel lead to lower carrier mobility and higher off-state leakage current. As a result, it is need for the number of trap states to be as low as possible. For example, Solid-Phase-Crystallization (SPC) [5]-[9] and Excimer Laser Annealing (ELA) [10]-[13] has been utilized in enlarging the grain size of the poly-Si to reduce trap states, leading to an excellent device performance.
It was found that with the increasing concentration of oxygen in the amorphous Si (a-Si) layer, the re-crystallization mechanism in it would be suppressed [14]. With the use of an optimized condition to form an oxygen-rich a-Si film before the deposition of the a-Si layer, we could derive larger grain size and less grain boundaries in poly-Si channel after SPC.
In this chapter, we used the method mentioned above to form the poly-Si channel to enlarge the grains, combing with the use of anneal with oxygen ambient
after the deposition of gate oxide to mend the defects in it. It was found that our devices have better electrical characteristics and stress immunization from Hot-Carrier Stress (HCS) than conventional poly-Si TFTs. We enhanced the transform characteristics in higher driving current and field effect mobility, and less leakage current, leading to a higher ON/OFF ratio, and also better reliability. We will make a detail discussion in the following sections.
2.2 Device Fabrication
Fig 2-1 schematically depicts the process flow and the cross-sectional view of the proposed n-channel poly-Si TFTs. First, a 550nm-thick thermal oxide layer was grown on the 6-in Si wafer with a furnace system. All the experimental devices in this study were fabricated on thermally oxidized Si wafers. Then, 100-nm amorphous Si layer was deposited on the thermally oxidized wafers as the control one and two, denoted as C1 and C2 later, with a low-pressure chemical vapor deposition (LPCVD) system at 550 oC and 100 mTorr in pressure, while the other one, denoted as Bi-layer later, deposited a 10-nm amorphous Si layer as the buffer layer under 500 oC and 15 mTorr before a 90-nm amorphous Si deposited under the environment as the controls without venting the system. Then, we checked the thicknesses of them respectively with n&k system to make sure they had almost the same thickness. Then, we used solid-phase-crystallization (SPC) method to recrystallize the amorphous Si films into poly-Si ones at 600 oC for 24 hours in N2 ambient. The poly-Si films were patterned into active regions by transformer couple plasma (TCP) etching system using mixture gases of Cl2 and HBr.
After RCA cleaning procedure, we deposited 50-nm TEOS oxide on them by TEOS and O2 gases at 695 oC with LPCVD system to form the gate insulators. After
the deposition, we annealed C2 and Bi-layer by furnace with O2 ambient at 700 oC for 1hr, while no treatment was done with C1. Then 200-nm amorphous Si was deposited with LPCVD system followed by SPC at 600 oC for 24 hours to serve as the poly-Si gate electrodes. Then, the poly-Si films were patterned by TCP etching system to form the gate electrodes and the gate oxides on source/drain were removed with dilute HF solution. The regions of sources, drains, and gates were doped by a self-aligned phosphorous ion implantation at the dosage and energy of 5E15 ions/cm2 and 20 KeV, respectively. The dopants were activated at 600 oC for 12 hours by furnace system, and 400-nm passivation oxide layers were deposited with plasma-enhanced CVD (PECVD) system at 300 oC. After the definition of contact holes with BOE solution, 500-nm Al layers were deposited by sputter and patterned as metal pads. Finally, we passivated them by NH3 plasma treatment for 1 hour at 300 oC.
2.3 Methods of Device Parameter Extraction
In this thesis, all of the electrical characteristics of proposed poly-Si TFTs were measured by HP 4156B-Precision Semiconductor Parameter Analyzer.
Many methods have been proposed to extract the characteristic parameters of poly-Si TFTs. In this section, those methods are described.
2.3.1 Determination of Threshold Voltage
Threshold voltage (Vth) is an important parameter required for the channel length-width and series resistance measurements. However, Vth is not defined uniquely. Various definitions have been proposed and reasons can be found in ID-VGS
curves. One of the most common techniques is the linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of
50~100mV to ensure operation in the linear region [15]. The drain current is not zero when VGS below threshold voltage and approaches zero asymptotically. Hence the IDS
versus VGS curve can be extrapolated to ID=0, and the Vth is determined from the extrapolated intercept of gate voltage (VGSi) by
2 Equation (1.1) is strictly only valid for negligible series resistance. Fortunately series resistance is usually negligible at the low drain current when threshold voltage measurements are made. The IDS-VGS curve deviates from a straight line at gate voltage below Vth due to subthreshold current and above Vth due to series resistance and mobility degradation effects. It is common practice to find the point of maximum slope of the IDS-VGS curve and fit a straight line to extrapolate to ID=0 by means of finding the point of maximum of transconductance (Gm).
In this thesis, we use a simpler method to determinate the Vth called constant drain current method. The voltage at a specified threshold drain current is taken as the Vth. This method is adopted in the most studied papers of poly-Si TFTs. It can be given a threshold voltage close to that obtained by the complex linear extrapolation method. Typically, the threshold current is specified at (W/L)×10nA for VDS=0.1V and (W/L)×100nA for VDS=5V, where W and L are channel width and channel length, respectively.
2.3.2 Determination of Subthreshold Swing
Subthreshold swing (S.S.) is a typical parameter to describe the control ability of gate toward channel, which reflects the turn on/off speed of a device. It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude.
The S.S. should be independent of drain voltage and gate voltage. However, in reality, the S.S. increases with drain voltage due to channel shortening effect such as charge sharing, avalanche multiplication and punchthrough effect. The subthreshold swing is also related to gate voltage due to undesirable and inevitable factors such as the serial resistance and interface states.
In this thesis, the S.S. is defined as one-third of the gate voltage required to decrease the threshold current by three orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to threshold voltage.
2.3.3 Determination of Field Effect Mobility
Usually, field effect mobility (μ ) is determined from the maximum value of eff transconductance (Gm) at low drain bias. The transfer characteristics of poly-Si TFTs are similar to those of conventional MOSFETs, so that the first order of I-V relation in the bulk Si MOSFETs can be applied to poly-Si TFTs. The drain current in linear region (VDS＜VGS－Vth) can be approximated as the following equation:
( )
⎥⎦⎤--e W and L ar--e chann--el width and chann--el l--ength, r--esp--ectiv--ely. Cox is the gate oxide capacitance per unit area and Vth is the threshold voltage. Thus, the transconductance is given by
DS
Therefore, the field-effect mobility is
( ) →0 DS
oxWV C
--- (Eq.1.4)
2.3.4 Determination of ON/OFF Current Ratio
= max
VDS
m
eff L g
μ
On/off current ratio is one of the most important parameters of poly-Si TFTs since
d off-current. In this chapter, take n-cha
a high-performance device exhibits not only a large on-current but also a small off-current (leakage current). The leakage current mechanism in poly-Si TFTs is not like that in MOSFET. In MOSFET, the channel is composed of single crystalline Si and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. However, in poly-Si TFTs, the channel is composed of poly-Si. A large amount of trap state densities in grain structure attribute a lot of defect states in energy band gap to enhance the tunneling effect.
Therefore, the leakage current is much larger in poly-Si TFTs than in MOSFET. When the voltage drops between gate voltage and drain voltage increases, the band gap width decreases and the tunneling effect becomes much more severe. Normally we can find this effect in typical poly-Si TFTs’ IDS-VGS characteristics where the magnitude of leakage current will reach a minimum and then increase as the gate voltage decreases/increases for n/p-channel TFTs.
There are a lot of ways to specify the on an
nnel poly-Si TFTs for examples, the on-current is defined as the drain current when gate voltage at the maximum value and drain voltage is 5V. The off-current is
nnel poly-Si TFTs for examples, the on-current is defined as the drain current when gate voltage at the maximum value and drain voltage is 5V. The off-current is