Methods of Device Parameter Extraction

In this thesis, all of the electrical characteristics of proposed poly-Si TFTs were measured by HP 4156B-Precision Semiconductor Parameter Analyzer.

Many methods have been proposed to extract the characteristic parameters of poly-Si TFTs. In this section, those methods are described.

2.3.1 Determination of Threshold Voltage

Threshold voltage (Vth) is an important parameter required for the channel length-width and series resistance measurements. However, Vth is not defined uniquely. Various definitions have been proposed and reasons can be found in ID-VGS

curves. One of the most common techniques is the linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of

50~100mV to ensure operation in the linear region [15]. The drain current is not zero when VGS below threshold voltage and approaches zero asymptotically. Hence the IDS

versus VGS curve can be extrapolated to ID=0, and the Vth is determined from the extrapolated intercept of gate voltage (VGSi) by

2 Equation (1.1) is strictly only valid for negligible series resistance. Fortunately series resistance is usually negligible at the low drain current when threshold voltage measurements are made. The IDS-VGS curve deviates from a straight line at gate voltage below Vth due to subthreshold current and above Vth due to series resistance and mobility degradation effects. It is common practice to find the point of maximum slope of the IDS-VGS curve and fit a straight line to extrapolate to ID=0 by means of finding the point of maximum of transconductance (Gm).

In this thesis, we use a simpler method to determinate the Vth called constant drain current method. The voltage at a specified threshold drain current is taken as the Vth. This method is adopted in the most studied papers of poly-Si TFTs. It can be given a threshold voltage close to that obtained by the complex linear extrapolation method. Typically, the threshold current is specified at (W/L)×10nA for VDS=0.1V and (W/L)×100nA for VDS=5V, where W and L are channel width and channel length, respectively.

2.3.2 Determination of Subthreshold Swing

Subthreshold swing (S.S.) is a typical parameter to describe the control ability of gate toward channel, which reflects the turn on/off speed of a device. It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude.

The S.S. should be independent of drain voltage and gate voltage. However, in reality, the S.S. increases with drain voltage due to channel shortening effect such as charge sharing, avalanche multiplication and punchthrough effect. The subthreshold swing is also related to gate voltage due to undesirable and inevitable factors such as the serial resistance and interface states.

In this thesis, the S.S. is defined as one-third of the gate voltage required to decrease the threshold current by three orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to threshold voltage.

2.3.3 Determination of Field Effect Mobility

Usually, field effect mobility (μ ) is determined from the maximum value of _eff transconductance (Gm) at low drain bias. The transfer characteristics of poly-Si TFTs are similar to those of conventional MOSFETs, so that the first order of I-V relation in the bulk Si MOSFETs can be applied to poly-Si TFTs. The drain current in linear region (VDS＜VGS－Vth) can be approximated as the following equation:

( )

--e W and L ar--e chann--el width and chann--el l--ength, r--esp--ectiv--ely. Cox is the gate oxide capacitance per unit area and Vth is the threshold voltage. Thus, the transconductance is given by

DS

Therefore, the field-effect mobility is

( ) →0 DS

oxWV C

--- (Eq.1.4)

2.3.4 Determination of ON/OFF Current Ratio

= max

VDS

m

eff L g

μ

On/off current ratio is one of the most important parameters of poly-Si TFTs since

d off-current. In this chapter, take n-cha

a high-performance device exhibits not only a large on-current but also a small off-current (leakage current). The leakage current mechanism in poly-Si TFTs is not like that in MOSFET. In MOSFET, the channel is composed of single crystalline Si and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. However, in poly-Si TFTs, the channel is composed of poly-Si. A large amount of trap state densities in grain structure attribute a lot of defect states in energy band gap to enhance the tunneling effect.

Therefore, the leakage current is much larger in poly-Si TFTs than in MOSFET. When the voltage drops between gate voltage and drain voltage increases, the band gap width decreases and the tunneling effect becomes much more severe. Normally we can find this effect in typical poly-Si TFTs’ IDS-VGS characteristics where the magnitude of leakage current will reach a minimum and then increase as the gate voltage decreases/increases for n/p-channel TFTs.

There are a lot of ways to specify the on an

nnel poly-Si TFTs for examples, the on-current is defined as the drain current when gate voltage at the maximum value and drain voltage is 5V. The off-current is specified as the minimum current when drain voltage equals to 5V.

V

2.3.5 Extraction of Grain Boundary Trap State Density

ory established by Le

llowing:

The Trap State Density (Nt), which can be determined by the the vinson et al. [16], which is based on Seto’s theory [17].

For poly-Si TFTs, the drain current IDS can be given as fo

⎟⎟

This expression, first developed by Levinson et al., is a standard MOSFET’s equation with an activated mobility, which depends on the grain-boundary barrier height. Levinson et al. assumed that the channel thickness was constant and equal to the thickness of the poly-Si film (t). This simplifying assumption is permissible only for very thin film (t<10nm). The trap-state density can be obtained by extracting a straight line on the plot of ln(IDS/VGS) versus 1/VGS at low drain voltage and high gate voltage.

Proano et al. [18] thought that a barrier approximation is to calculate the gate induced carrier channel thickness by solving Poisson’s equation for an undoped material and to define the channel thickness (Lc) as a thickness in which 80% of the total charges were induced by the gate. Doing so, one obtains

(

)

which varies inversely with (VGS−Vfb). This predicts, by substituting Eq.2.7 into Eq.1.6, that ln[IDS/(VGS−Vfb)] versus 1/(VGS−Vfb)². We use the gate voltage at which

minimum leakage current occurs as flat-band voltage (Vfb). Effective trap-state density (Nt) can be determined from the square root of the slope.