Summary

We used an anneal procedure after gate oxide deposition to improve the transfer characteristics and reliability of poly-Si TFTs. With the deposition of a buffer a-Si layer under low-temperature and low-pressure condition, we fabricated high-performance poly-Si TFTs with enhanced reliability. The characteristics of the

proposed TFTs have great improvement, such as higher On-state current, higher field effect mobility, lower subthreshold swing, suppressed GIDL current, and better reliability. With an optimized deposition condition of the buffer a-Si layer, the proposed TFTs would be candidates in high performance TFTs application.

References:

[1] Y. Oana, “Current and future technology of low-temperature poly-Si TFT-LCDs,”

Journal of the SID, vol. 9, pp. 169-172, 2001.

[2] S. Morozumi, K. Oguchi, S. Yazawa, Y. Kodaira, H. Ohshima, and T. Mano, “B/W and color LC video display addressed by poly-Si TFTs,” SID Dig., pp.156, 1983.

[3] R. E. Proano, R. S. Misage, D. Jones, and D. G. Ast, “Guest-host active matrix liquid-crystal display using high-voltage polysilicon thin film transistors,” IEEE Trans. Electron Devices, vol. 38, pp. 1781, 1991.

[4] K.Werner, “The flowering of flat displays,” IEEE Spectrum, vol. 34, pp. 40–49, May 1997.

[5] A. Nakamura, F. Emoto, E. Fujii and A. Tamamoto, “A high-reliability, low-operation-voltage monolithic active-matrix LCD by using advanced solid-phase growth technique,” in IEDM Tech. Dig., pp.847, 1990.

[6] R. B. Iverson and R. Reif, “Recrys tallization of amorphized polycrystalline silicon films on SiO2: temperature dependence of the crystallization parameters,”

J. Appl. Phys., vol. 62, no. 5, pp. 1675-1681, 1987.

[7] R. B. Iverson and R. Reif, “Stochastic model for grain size versus dose in implanted and annealed polycrystalline silicon films on SiOz,” J. Appl. Phys., vol.

57, p. 5169, 1985.

[8] T. Noguchi, H. Hayashi, and T. Ohshima, “Advanced superthin polysilicon film obtained by Si+ implantation and subsequent annealing,” J. Electrochem. Soc., vol.

134, p. 1771, 1987.

[9] M. K. Hatalis and D. W. Greve, “Large grain polycrystalline silicon by low-temperature annealing of low-pressure chemical vapor deposiited amorphous silicon films,” J. Appl. Phys., vol. 63, p. 2260, 1988.

[10] N. Kudo, N. Kusumoto, T. Inushima, and S. Yamaza ki, “Characterization of polycrystalline-Si thin-film transistors fabricated by excimer laser annealing method,” IEEE Trans. Electron Devices, vol. 41, no. 10, pp. 1876-1879, 1994.

[11] T. Sameshima, S. Usui and M. Sekiya, “XeCl excimer laser annealing used in the fabrication of poly-Si TFT’s,” IEEE Electron Device Lett., vol. 7, no. 5, pp.

276-278, 1986.

[12] D. H. Choi, E. Sadauyki, O. Sugiura and M. Matsumra, “Excimer-laser crystallized poly-Si TFT’s with mobility more than 600 cm2/V.s,” IEEE Trans.

Electron Devices, vol. 40, no. 11, pp. 2129, 1993.

[13] Noguchi, T., Tang, A.J., Tsai, J.A., Reif, R., “Comparison of effects between large-area-beam ELA and SPC on TFT characteristics,” Electron Devices, IEEE Transactions, Vol 43, Issue 9, pp.1454 – 1458, 1996

[14] M. K. Ryu, J. Y. Kwon, and K. B. Kim, “SOLID PHASE CRYSTALLIZATION (SPC) BEHAVIOR OF AMORPHOUS Si BILAYER FILMS WITH

DIFFERENT CONCENTRATION OF OXYGEN: Surface vs.

Interface-nucleation,” Mat. Res. Soc. Symp. Proc. Vol. 621, 2000.

[15] Dieter K. Schroder, “Semiconductor Material and Device Characterization,”

Wiley-INTERSCIENCE, 1998

[16] J. Levinson, G. Este, M. Rider, P. J. Scanlon, F. R. Shepherd, and W. D.

Westwood, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys., vol. 53, no. 2, pp. 193, 1982

[17] J. Y. W. Seto, “The electrical properties of polycrystalline silicon films,” J. Appl.

Phys., vol. 46, no. 12, pp. 5247, 1975

[18] R. E. Proano, R. S. Misage, D. Jones, and D. G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin film transistors,” IEEE Trans.

Electron Devices, vol. 36, no. 9, pp. 1915, 1989.

Si Wafer Buffer Oxide

(a) Thermal oxidation grown by furnace.

a-Si (~90nm) a-Si (~10nm) Buffer Oxide

Si Wafer

(b) Bi-layer amorphous Si (a-Si) deposited by LPCVD.

Buffer Oxide Poly-Si 90nm Poly-Si 10nm

Si Wafer

(c) Recrystallization of a-Si film into poly-Si channel by SPC, followed by active region definition.

Gate oxide

Buffer Oxide Poly-Si 90nm

Poly-Si 10nm

Poly-Si gate

Si Wafer

(d) Deposition of TEOS gate oxide by LPCVD and poly-Si gate by LPCVD, gate electrode defined.

P+ ion implantation

(e) Self-aligned phosphorous ion implantation.

Poly-Si gate

Gate oxide Poly-Si 90nm

Poly-Si 10nm

Buffer Oxide

Si Wafer

(f) Dopants activated by furnace.

(g) Deposition of passivation oxide by PECVD.

n+

Gate oxide

Buffer Oxide Poly-Si 90nm

n+ n+

Poly-Si 10nm

Si Wafer

n+

Gate oxide

Buffer Oxide Poly-Si 90nm

n+ n+

Poly-Si 10nm

Si Wafer

n+

Buffer Oxide Poly-Si 90nm

Poly-Si 10nm

Si Wafer

n+

n+

Gate oxide

(h) Contact holes opened and metal pads formation.

Fig. 2-1 Schematic diagram of fabrication process for bi-layer poly-Si TFTs.

10

^-10

Drain Current, I

DS

(A) Fi e ld- Eff e c t M o b il it y (c m

2

/V*s )

Gate Voltage, V

G

(V)

V

DS

= 5 V

V

DS

= 0.1 V

W/L = 10um/1um

Fig. 2-2 Transfer characteristics of the poly-Si TFTs with and without an anneal procedure after the deposition of gate oxide.

Table 2-1 Comparison of device characteristics of the poly-Si TFTs with and without an anneal procedure after the gate oxide deposition (W/L=10um/1um).

Without Anneal With Anneal

V

_th

(V) 4.02 1.76

S. (V/dec.) 1.07 0.90

μ

_FE

(cm

²

/V*s) 19.8 22.5

I

_on

@ V

_G

=10 V, V

_D

= 5 V (A)

7.72 x 10

^-4

8.71 x 10

^-4

I

_off

@ V

_G

=-10V, V

_D

= 5V (A)

6.92 x 10

^-9

2.58 x 10

^-9

I

_on

/I

_off

1.12 x 10

⁵

3.38 x 10

⁵

N

_t

(cm

^-2

) 7.31 x 10

¹²

3.47 x 10

¹²

-1 -0.5 0 0.5 1 1.5 2 2.5 3

0.1 1 10 100 1000

With Anneal Without Anneal

V

th

shi ft (V )

Stress Time (s)

W/ L = 10um/10um V

G

=-20V

V

D

= V

G

=0V

at 100

^o

C

Fig. 2-3(a) Threshold voltage (Vth) shift versus stress time of n-TFTs with and without gate oxide anneal under static gate bias VG=-20V while S/D were grounded at 100^oC.

-1.5 -1 -0.5 0

0.1 1 10 100 1000

With Anneal Without Anneal

V

th

shi ft(V )

Stress Time(s)

W / L = 10um/10um V

G

=20V

V

D

=V

S

=0V at 100

^o

C

Fig. 2-3(b) Threshold voltage (Vth) shift versus stress time of n-TFTs with and without gate oxide anneal under static gate bias VG=20V while S/D were grounded at 100^oC.

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

0.0001 0.001

-10 -5 0 5 10

Bi-layer Control

Drain C u rren t (A)

Gate Voltage (V)

V

D

= 5 V

W / L = 1um/0.8um

Fig. 2-4(a) Transfer characteristics of the Control and the Bi-layer poly-Si TFTs with VDS=5V.

-10 0 10 20 30 40 50

-10 -5 0 5 10 15

Bi-layer Control

Fiel d Effect M o bi li ty ( (cm

2

/V*s))

Gate Voltage (V)

V

D

= 0.1V

W / L = 1um/0.8um

Fig. 2-4(b) Field effect mobility of the Control and the Bi-layer poly-Si TFTs with VDS=0.1V.

-14 -13.5 -13 -12.5 -12 -11.5

0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045

Bi-layer

Control

y = -11.657 - 38.588x R= 0.99345 y = -11.734 - 55.526x R= 0.99311

ln[I

Fig. 2-5 Trap state density extraction of the Control and the Bi-layer poly-Si TFTs.

DS

/(V -V )]

1/(V

GS

-V

FB

)

²

(V

^-2

)

N

t

= 2.68127x10

¹²

cm

^-2

N

t

= 3.21634x10

¹²

cm

^-2

(O

-1

)

FBGS

-1 10^-5 0 1 10^-5 2 10^-5 3 10^-5 4 10^-5 5 10^-5 6 10^-5 7 10^-5

0 1 2 3 4 5

Bi-layer (V

G-V

th = 4~7 V) Control (V

G-V

th = 4~7 V)

Drain Current (A)

Drain Voltage (V)

W / L = 1um/0.8um

Fig. 2-6 Output characteristic of the Control and the Bi-layer poly-Si TFTs.

Table 2-2 Comparison of device characteristics of the Control and the Bi-layer poly-Si TFTs.

Control Bi-layer

V

th

(V) 0.48 0.26

S (V/dec.) 1.05 0.71

μ

FE

(cm

²

/V*s) 38 45

I

_on

@ V

_G

=10 V, V

_D

= 5 V (A)

1.07 x 10

^-4

1.33 x 10

^-4

I

off

@ V

G

=-10V, V

D

= 5V (A)

1.05 x 10

^-8

3.84 x 10

^-9

I

on

/I

off

1.02 x 10

⁴

3.46 x 10

⁴

N

_t

(cm

^-2

) 3.22 x 10

¹²

2.68 x 10

¹²

0 Fig. 2-7 (a) Threshold voltage and (b) subthreshold swing degradation versus the

stress time under hot-carrier stress at room temperature

0

Fig. 2-8 (a) Threshold voltage and (b) subthreshold swing degradation versus the stress time under hot-carrier stress at 100 ^oC.

Chapter 3

Degradation Mechanisms of NBTI and PBTI in Low-Temperature Poly-Si Thin-Film Transistors

3.1 Introduction

Recently, low temperature polycrystalline silicon thin-film transistors (LTPS TFTs) have attracted much attention due to the high potential of realizing system on panel (SOP) [1], the possibility of realizing the integration of peripheral circuit, and applications in active matrix liquid crystal displays (AMLCDs)[2][3]. Inevitably, the stability of poly-Si TFTs is of significant importance from the fabrication technology point of view and as a long-term reliability concern [2]. In p-channel MOSFETs, negative bias temperature instability (NBTI) has been found to be an important reliability concern [3][4][5], while positive bias temperature instability (PBTI) been found to be an important problem to n-channel MOSFETs. Both the influences of NBTI to p-channel MOSFETs and PBTI to n-channel MOSFETs have been widely investigated. It was found that the degradation mechanisms for NBTI and PBTI were quite different. The degradation due to NBTI is mainly responsible for the generation of interface states and fixed oxide charge, as a result, NBTI could be thermally and electrically activated by elevated stress temperature and voltage [6]. Unlike NBTI, n-channel MOSFETs with high-k gate insulators have attracted much attention. PBTI only exist in the formation of donor-like interface states and charge de-trapping from the gate insulators [7].

In LTPS TFTs, due to the poor thermal conductivity of the glass substrates and high operation voltages, we supposed NBTI and PBTI would be important in the

reliability of LTPS TFTs. Additionally, the LTPS TFT driving circuit is designed using the CMOSFET structure, we speculate that the effects of NBTI and PBTI will degrade the reliability of p-channel and n-channel TFTs, respectively. Some researches have pointed out BTI stress caused the performance degradation in poly-Si TFTs as well as in MOSFETs [8]. Moreover, the degradation mechanism of BTI stress in poly-Si TFTs, due to the grain boundaries in the channel region, may be different from MOSFETs.

Some studies have indicated that BTI stress on poly-Si TFTs may generate trap states in the grain boundaries [9]. However, the effects of NBTI and PBTI on the reliability of LTPS TFTs have not been explored.

In this chapter, the reliability of the LTPS TFTs was studied by applying NBTI and PBTI stress on TFTs. The NBTI stress was applied to the p-channel LTPS TFTs, while the PBTI stress was applied to the n-channel LTPS TFTs. By varying the stress voltages and temperatures, the basic devices parameters were extracted and analyzed to explain the degradation mechanisms.

3.2 Experimental

The p- and n-channel LTPS TFTs were fabricated on glass substrates. A 40nm-thick amorphous-Si layer was first deposited by PECVD on a buffer layer and crystallized into poly-Si film by excimer laser annealing. For the p-channel TFTs, the gate dielectric was deposited with an equivalent 100nm-thick SiO2 layer after defining the active region. Mo was then deposited and patterned as the gate electrode.

Self-align source/drain was formed by plasma doping. Fig. 3-1 shows the schematic diagram of fabrication process. For the n-channel devices, the source and drain were first formed after defining the active region. The gate dielectric and metal film were deposited and patterned as the gate electrode. Following that, self-aligned

lightly-deped soruce and drain were formed. Then, the inter-layer dielectric was deposited on all the devices and densified. The dopants were activated during the densification of the inter-layer dielectric. Finally, inter-connection metal was deposited and patterned. The channel length (L) and channel width (W) of the device used in this study were 10 and 20 µm, respectively.

During NBTI stress, the glass substrate was heated to the stress temperature ranging from 25 to 150^oC, and the stress voltage in the range of -15 to -30 V was applied the gate with the source/drain grounded. The schematic cross-section diagrams of the LTPS TFTs and stress setup is shown in Fig. 3-2. The stress was periodically stopped to measure the basic characteristics of the device to characterize the NBTI effect. All the measurements were taken at the stress temperature. Fowler-Nordheim current was not pronounced at these bias conditions; therefore, the extra trap state generation and device instability caused by the small current can be neglected.

3.3 Results and Discussion

Fig. 3-3(a) and 3-3(b) show the influence of NBTI and PBTI stress on the transfer characteristics of the p- and n-channel TFTs, respectively. In both case, the absolute values of threshold voltages (|Vth|) increase after NBTI or PBTI stress. The subthreshold swing (S) degrades after NBTI stress for p-channel TFT, wihle it remains almost unchanged after PBTI stress for n-channel TFT. This indicates that NBTI stress generate more interface trap states in the deivce. Besides, the field-effect mobily (µFE) is found to decrease under NBTI stress; however, it is worth notint that the µFE increases after PBTI stress.

Fig. 3-4(a) and 3-4(b) show the time dependence of the threshold voltage shift (ΔVth) of the p- and n-channel TFTs, respectively. The stress was performed at 150^oC

with various stress gate voltages. In our study, the gate voltage at a specified threshold drain current (IDS), ± (W/L) × 10 nA for VDS = ±0.1 V, is taken as the threshold voltage. In both cases, the |ΔVth| increases as the absolute value of the stress gate voltage increases, indicating that both NBTI and PBTI can be electrically activated.

Besides, the |ΔVth| shows a power law dependence on the stress time (|ΔVth| ~ t ⁿ). The exponent factor n is around 0.25 to 0.30 for p-channel TFTs under NBTI stress, which is similar to the results previously reported for poly-Si TFTs [10][11] and bulk MOSFETs [10]. It has been reported that the exponent factor between 1/3 to 1/4 can be explained by the diffusion-controlled electrochemical reactions [7][12]. However, for the n-channel TFT under PBTI stress, the n value is below 0.12, indicating the PBTI-degradation mechanism is different to that of NBTI.

Fig. 3-5(a) and 3-5(b) show the time dependence of the |ΔVth| of p- and n-channel TFTs, respectively, under various stress temperatures with stress gate voltage of -30 V.

As the stress temperature increases, the |ΔVth| increases under NBTI stress; however, it shows almost temperature independent under PBTI stress. It has been reported that the NBTI-degradation in MOSFETs is mainly attributed to the generation of interface trap states and fixed oxide charges, and it can be thermally and electrically activated [3][5][6]. However, the PBTI-degradation mechanism is generally explained by the charge trapping in the gate dielectric. Therefore, the NBTI- and PBTI-degradation show different dependent on the stress temperature.

Fig. 3-6(a) and 3-6(b) show the µFE variation as a function of the stress voltage for p- and n-channel TFTs, respectively. It has been reported that the subthreshold swing is more closely related to the trap states located near the midgap (deep states), while the mobility is more associated with the trap states located near the band edge (tail states) [11]. For the p-channel TFTs, the NBTI stress rarely changes the µFE, indicating that the generation of the tail states can be neglected under NBTI stress. For

the n-channel TFTs, the µFE increases with the stress voltage or temperature, implying that the tail states can be passivated during PBTI stress.

Fig. 3-7(a) and 3-7(b) show the drive current degradation as a function of the stress voltage for p- and n-channel TFTs, respectively. For the p-channel TFTs, the drive current degrades as the stress voltage or temperature increases. This is because that NBTI can be electrically or thermally activated, leading to the Vth shift and drive current degradation. For the n-channel TFTs, the drive current variation exhibits two regimes: in the low stress voltage regime, the drive current increases with the stress voltage; in the high stress voltage regime, the drive current decreases as the stress voltage increases. In the low stress voltage regime, the drive current increase is due to the µFE enhancement. In the high stress voltage regime, the ΔVth becomes so large that the effect of mobility enhancement is screened; therefore, the drive current decreases with the stress voltage. The comparison of the effects of NBTI and PBTI on the TFT performance is shown in Table 3-1.

3.4 Summary

In this study, the mechanisms of NBTI and PBTI in LTPS TFTs were analyzed.

The |ΔVth| increases with the stress gate voltage. However, as the stress temperature increase, the |ΔVth| increases under NBTI stress but almost unchanged under PBTI stress. Furthermore, the µFE is rarely changed under NBTI stress but increases under PBTI stress. From our analysis, the NBTI-degradation mechanism in p-channel LTPS TFTs is attributed to the diffusion-controlled electrochemical reactions, while the PBTI-degradation in n-channel LTPS TFTs is arisen from the charge trapping in the gate dielectric.

REFERENCES:

[1] T. Serikawa, S. Shirai, A. Okamoto and S. Suyama, “Low-temperature fabrication of high-mobility poly-Si TFT’s for large-area LCD’s,” IEEE Trans. Electron Devices, vol. 36, pp. 1929-1933, 1989.

[2] I W. Wu, W. B. Jackson, T. Y. Huang, A. G. Lewis and A. Chiang, “Mechanism of device degradation in n- and p-channel polysilicon TFT’s by electrical stressing,”

IEEE Electron Device Lett., vol. 11, pp. 167-170, 1990.

[3] C. E. Blat, E. H. Nicollian and E. H. Poindexter, “Mechanism of negative-bias-temperature instability,” J. Appl. Phys., vol. 63, pp. 1712-1720, 1991.

[4] J. F. Zhang and W. Eccleston, “Positive bias temperature instability in MOSFET’s,” IEEE Trans. Electron Devices, vol. 45, pp. 116-124, 1998.

[5] N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. T. Liu, R. C. Keller and T.

Horiuchi, “NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.1-μm gate CMOS generation,” in Symp. VLSI Tech. Dig., pp. 92-93., 2000.

[6] Kousuke Okuyama, Katsuhiko Kubota, Takashi Hashimoto, Shuji Ikeda and Atsuyosi Koike, “Water-Related Threshold Voltage Instability of Polysilicon TFTs,” in IEDM Tech. Dig., pp. 527-530, 1993.

[7] S. Maeda, S. Maegawa, T. Ipposhi, H. Nishimura, T. Ichiki, J. Mitsuhashi, M.

Ashida, T. Muragishi and T. Nishimura, “NEGATIVE BIAS TEMPERATURE INSTABILITY IN POLY-Si TFTs ,” in Symp. VLSI Tech. Dig., pp. 29-30, 1993.

[8] D. K. Schroder and J. A. Babcock, “Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing,” J. Appl. Phys., vol. 94, pp. 1-18, 2003.

[9] S. Ogawa and N. Shiono, “Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface,” Phys. Rev. B, vol. 51, pp. 4218-4230, 1995.

[10] K. Okuyama, K. Kubota, T. Hashimoto, S. Ikeda and A. Koike, “Water-related threshold voltage instability of polysilicon TFTs,” in IEDM Tech. Dig., 1993, pp.

527-530.

[11] S. Maeda, S. Maegawa, T. Ipposhi, H. Nishimura, T. Ichiki, J. Mitsuhashi, M.

Ashida, T. Muragishi and T. Nishimura, “Negative bias temperature instability in poly-Si TFTs ,” in Symp. VLSI Tech. Dig., 1993, pp. 29-30.

[12] N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai and T. Horiuchi,

“The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling,” in Symp. VLSI Tech. Dig., 1999, pp. 73-74.

[13] T. J. King, M. G. Hack and I W. Wu, “Effective density-of-states distributions for accurate modeling of polycrystalline-silicon thin-film transistors,” J. Appl.

Phys., vol. 75, pp. 908-913, 1994.

[14] K. O. Jeppson and C. M. Svensson, “Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices,” J. Appl. Phys., vol. 48, pp.

2004-2014, 1977.

Buffer Layer Glass

(a) Buffer layer deposition on glass substrate.

a-Si Buffer Layer

Glass

(b) Amorphous Si (a-Si) deposited by PECVD.

Poly-Si Channel Buffer Layer

Glass

(c) Crystallization of a-Si film into poly-Si film by excimer laser annealing, and active region defined.

Gate Oxide Poly-Si Channel

Buffer Layer Glass

(d) Deposition .of gate oxide by PECVD

Metal Gate

Gate Oxide Poly-Si Channel

Buffer Layer Glass

(e) Deposition Mo as the gate electrode.

Plasma Doping

(f) Self-align Source/Drain was formed.

(g) Interface layer deposition and dopant activation.

Glass Buffer Layer Poly-Si Channel

Metal Gate

Gate Oxide

Glass Buffer Layer Poly-Si Channel

Metal Gate

Gate Oxide

P

^P+

P

^P+

(h) Contact holes were opened and inter-connection metal was deposited and patterned.

Fig. 3-1 Process flow of the poly-Si TFT.

Glass Buffer Layer Poly-Si Channel

Gate Oxide Metal Gate

P

^P+

P

^P+

Fig. 3-2 Schematic cross-section diagram of LTPS TFT and NBTI stress setup. The stress temperature was performed from 25^oC to 150^oC, and the stress gate voltage was applied in the range of -15V to -30V with source and drain grounded.

10^-14 Temperature = 150^oC Stress Time = 1000s VG = -30V

W/L=20um/10um

Fig. 3-3 (a) Transfer characteristics of LTPS TFT before and after 1000sec NBTI stress at 100^oC with the stress voltage of -30V.

10^-14

Temperature = 150^oC Stress Time = 1000s VG = 30V

W/L=20um/10um

Fig. 3-3(b) Output characteristics of LTPS TFT before and after 1000sec NBTI stress at 100^oC with the stress voltage of -30V.

0.001 0.01 0.1 1 10

0.1 1 10 100 1000

VG = -15V, n = 0.25 VG = -20V, n = 0.30 VG = -25V, n = 0.25 VG = -30V, n = 0.28

-V

th

S h if t (V )

Stress Tim e (s)

W /L = 20um /10um Tem perature = 150^oC

Fig. 3-4(a) Dependences of threshold voltage shift on the stress time of LTPS TFTs under various stress conditions

0.001 0.01 0.1 1 10

0.1 1 10 100 1000

VG = 15V, n = 0.09 VG = 20V, n = 0.07 VG = 25V, n = 0.12 VG = 30V, n = 0.05

V

th

S h ift ( V )

Stress Time (s)

W/L = 20um/10um Temperature = 150^oC

Fig. 3-4(b) Dependences of threshold voltage shift on the stress voltage of LTPS TFTs under various stress conditions

0 .01 0 .1 1 1 0

0 .1 1 1 0 1 00 1 00 0

2 5^oC 5 0^oC 1 00^oC 1 50^oC

- V th Shift (V)

S tre s s T im e (s )

W /L = 2 0 u m /1 0u m S tre s s V o lta g e , V

G = -30 V

Fig. 3-5(a) Time dependence of the ΔVth of p-channel and under various stress temperatures.

0.01 0.1 1 10

0.1 1 10 100 1000

25^oC 50^oC 100^oC 150^oC

V

th

Sh if t ( V )

Stress Tim e (s)

W /L = 20um /10um Stress Voltage, V

G = 30V

Fig. 3-5(b) Time dependence of the ΔVth of n-channel TFTs under various stress temperatures..

-20 0 20 40 60 80 100

-35 -30 -25 -20 -15 -10

25^oC 50^oC 100^oC 150^oC

μ

FE

Var iat io n ( % )

Stress Gate Voltage, V

G

(V)

Stress Time = 100s

Fig. 3-6(a) Correlation between the degradation of subthreshold swing, and threshold voltage shift of p-channel LTPS TFTs after NBTI stress.

-2 0 0 2 0 4 0 6 0 8 0 1 00

1 0 1 5 2 0 2 5 3 0 3 5

2 5^oC 5 0^oC 1 00^oC 1 50^oC

μ

FE Variation (%)

S tre s s G a te V o lta g e , V

G

(V )

S tre s s T im e = 1 00 s

Fig. 3-6(b) Correlation between the degradation of maximum transconductance, and threshold voltage shift of n-channel LTPS TFTs after NBTI stress.

-6 0 -4 0 -2 0 0 2 0 4 0

2 5^oC 5 0^oC 1 0 0^oC 1 5 0^oC

-3 5 -3 0 -2 5 -2 0 -1 5 -1 0

I

ON

D e g rad at ion ( %)

S tre s s G a te V o lta g e , V

G

(V )

W /L = 2 0 um /1 0u m S tre s s T im e = 1 00 0 s

IO N = I

D S @ V

G S = -6V , V

D S = -5V

Fig. 3-7 (a) Drive current variation as a function of the stress voltage for p-channel LTPS TFTs.

-60 -40 -20 0 20 40

10 15 20 25 30 35

25^oC 50^oC 100^oC 150^oC

I

ON

V a ri at ion ( % )

Stress Gate Voltage, V

G

(V)

ION = I

DS @ V

GS = 7V, V

DS = 5V W /L = 20um/10um

Stress Tim e = 1000s

Fig. 3-7 (b) Drive current variation as a function of the stress voltage for n-channel LTPS TFTs.

Table 3-1 Comparison of the effects of NBTI and PBTI on the TFT performance.

PBTI NBTI

|ΔV

th

| μ

FE

I

ON

|ΔV

th

| μ

FE

I

ON

︱Vg︱↑ ↑ ↑ ↑↓ ↑ ＝ ↓

T↑ ＝ ↑ ＝ ↑ ＝ ↓

n 0.05~0.12 0.25~0.30

Chapter 4

Dynamic Negative Bias Temperature Instability of Low-Temperature Poly-Silicon Thin-Film

Transistors

4.1 Introduction

Low temperature poly-Si thin film transistors (LTPS TFTs) are now widely investigated for their potential application in active matrix liquid crystal displays (AMLCDs) [1]-[3] and realization of system on panel (SOP) [4]. For the LTPS TFTs to be used for advanced analog and mixed signal circuit, the electrical stability becomes an important issue. In the pervious studies, NBTI induced device parameter degradation is a serious reliability concern in advanced analog and mixed signal technologies [5]-[8]. NBTI induced threshold voltage shifts in p-channel TFTs is a critical issue for these analog circuits. To determine maximum threshold voltage (Vth) shift in an analog circuit over its operating lifetime, several factors that influence the conventional DC lifetime projection method have been widely investigated. With the continuous scaling of the dimensions of transistors, negative bias temperature instability (NBTI) stress in p-MOS transistors has become one of the most critical reliability issues which determine the lifetime of CMOS devices [9]-[12]

A negative bias applied to the gate electrode of p-MOSFET at elevated temperatures with grounded source and drain was performed in conventional NBTI research. However, p-MOSFETs for a CMOS inverter application, the applied gate bias is alternating from “high” to “low”, followed by “low” to “high” over and over.

Therefore, it is necessary to investigate the dynamic pulse condition of application.

Former researches show that there was a passivation mechanism during “high” bias condition, and this passivation mechanism would prolong the lifetime of the p-MOSFET of CMOS inverter [13]-[16]. It was found that a large portion of interface states generated during “low” state would be passivated during “high” state. With this passivation effect, p-MOSFET operating in CMOS inverters would have prolonged lifetime.

In this chapter, we assumed that former researches upon static NBTI effect on

In this chapter, we assumed that former researches upon static NBTI effect on

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