Organization of this Thesis

There are five parts in this thesis. Chapter 1 is the introduction, and we describe the motivation and organization of this thesis. In Chapter 2, we show the device fabrication and equipment setup used in this experiment. The mechanisms for low resistance state and high resistance state will be illustrated.

In Chapter 3, we discuss the reliability issues of this device, and then in Chapter 4, we discuss the switching mechanism from the point view of operation procedures. Finally, the summary and conclusions are given in Chapter 5.

Chapter 2

Device Fabrication and Theory of Space Charge Limited Current

2.1 Introduction

There are three parts in this chapter. First, we describe the device fabrication, and the equipment set up in this thesis. And then, we will discuss the switching mechanism Space-Charge-Limited-Current

（SCLC）, which is fitted in the low resistance state（LRS）. Finally, we discuss the concept of oxygen vacancy, which is the previously reported possible mechanism for the high resistance state.

2.2 Device Fabrication & Equipment Setup

2.2.1 Device Fabrication

There are two kinds of RRAM used in this thesis. The first one consists of only one RRAM cell

（1R）. The other one consists of one RRAM cell and one Transistor（1T1R）as the current limiter . The structure of RRAM was the TiN / TiOx / HfOx / TiN stack, which was deposited on the Ti / SiO2 / Si substrate. The HfO2 thin film was deposited by atomic layer deposition（ALD）, while all the other thin films were deposited by sputtering methods. The transistor in 1T1R structure was fabricated by 0.18 um CMOS technology on 8-inch wafer with post metal alloying（PMA）. Due to the well known ability of Ti to absorb oxygen atom[2.1], oxygen atoms diffuse from the HfO2 layer to the Ti, which resulting in the formation of HfOx (x~1.4) with a large amount of oxygen deficiency and the oxidation of Ti. The corresponding XTEM image made by the XPS examination is presented in Fig 2.1[2.2].

2.2.2 Equipment Setup

The whole experimental setup for the I-V and pulse characteristics measurement of RRAM is illustrated in Fig. 2.2. Based on the PC controlled instrument environment by HP-IB (GP-IB, IEEE-488 Standard) interface, the complicated and long-term characterization procedures during analyzing the behaviors in RRAM cells can be easily achieved. As shown in Fig. 2.2, the equipments, including the semiconductor parameter analyzer (HP 4156C), low leakage switch mainframe (HP 5250A Switching Matrix), pulse generator (HP 81110A), and probe station, were used for our measurements on RRAM.

Programs written by HT-Basic were used to execute the measurement via HP-IB interface.

The HP 4156C provides a high current resolution up to pico-ampere range, and is equipped with four programmable source/monitor units. Two source units, and two monitor units for supplying or monitoring the voltage and the current. The pulse generator HP 81110A with high timing resolution provides for P/E cycling endurance and transient characterization. The HP 5250A switching matrix equipped with an 8-input x 12-input switching matrix switches the signals from the HP 4156C and HP 81110A to device under test in probe station automatically.

In order to control the pulse timing of HP 81110A during transient and P/E cycling endurance characteristics precisely, we select the triggered pattern mode to achieve this goal. Fig. 2.3 (a) and Fig.

2.3 (b) show the program and erase schemes on the RRAM respectively. For example, by taking the program timing program as shown in Fig. 2.3, the triggered pattern mode can be explained as follows.

In Fig. 2.3 (a), the VSMU1 of HP 4156C generated a voltage signal which is equal to the low voltage level of HP 81110A. This triggered pattern mode method can provide a substrate bias during programming, and prevent additional stress to device during P/E cycling endurance operation. The pattern mode defined as 01000 in Fig. 2.3 (a) from HP 81110A is then sent and the program or erase

2.3 The Theory of Space-Charge-Limited-Current

Space charge means that the electric charge is distributed as continuum in a region, rather than distinct point-like charge and usually observed in dielectrics, like oxides. When the dielectric is stressed with a high electrical field, the electric charges are injected into the region near the electrode, forming the space charge regions. The space charge in the dielectric is often said to be the main source of contribution to the dielectric breakdown. The sign of space charge can be either positive or negative depending on the dielectric materials [2.2].

If a solid material with unfilled deep-level traps, then the so called space charge limited current (SCLC) [2.3] will be significantly lowered from the trap-free case by a ratio θ. The ratio θ is determined by the trap density （Nt） and trap depth （ΔEt）as the relationship θ α exp（ΔEt/kT）/N, where T is the absolute temperature in K and k is the Boltzmann constant. From this theory, if the current increase dramatically , it means that the deep level traps are filled under this operation voltage, called traps-filled-limited voltage （VTEL）which is determined by the unfilled deep trap density. In semiconductor, the space-charge effect is said to occur, when the injected n or p carrier concentration is larger than the equilibrium values and the doping concentration [2.4]. There are three equations used to identify the SCLC effect[2.5]： 3、In the ballistic region （Child-Langmuir law）

And, from our experimental data, we could identify whether the switching mechanism in high resistance state or low resistance state which are related to the SCLC or not.

2.4 Oxygen Vacancy

Depending on the ability of Ti to absorb the oxygen atoms as mentioned in section 2.2.1, the oxygen vacancies is believed to play an important role of the transition metal oxide based resistive switching mechanism. In oxide materials, oxide vacancy is a special kind of point like defect. And, for a long time, it has been the invisible agent of oxide surface [2.6]. The nature of oxygen vacancy in different oxides is quite different as a result of different electronic structure and bonding state in these materials. For example, the oxygen vacancy is highly ionic in MgO, but covalent polar in SiO2 [2.6]. In the metal/oxide/metal capacitor like structure, the oxygen vacancy is believed to be positively charged [2.7].

Fig. 2.1 XPS depth profile of TiN/Ti/HfO2/TiN stack layers after alloying

01000

Probe Station Personal Computer

HP 81110A Pulse Generator

Parameter Analyzer HP 4156C

Switch Matrix HP 5250 A

Fig. 2.2 The experimental setup of the current-voltage and the P/E cycling endurance characteristics measurement in RRAM.

Automatic controlled characterizations system was setup based on the PC controlled instrument environment.

Fig. 2.3 The timing diagram of the triggered pattern mode method during (a) program (b) erase operation.

Chapter 3

Reliability Issues on Resistive Random Access Memory

3-1 Introduction

In this chapter, we will show the standard measurement procedure of resistive random access memory and introduce some related definitions. Also, we will investigate the reliability of it. Regarding the reliability, we measure the area dependence of several operation parameters, and then we use the sweep mode to show the possibility of multi-level operation. Then, we measure the resistance loss at 85 , to ob℃ serve its data retention characteristic. After that, we compare the Program/Erase cycling endurance between 1R and 1T1R device structures, where the HP4156C and transistor are used as the current limiter respectively. Finally the stress and temperature effects are investigated.

3.2 Measurement Procedure of RRAM

3.2.1 Compliance Current

The purpose for setting the compliance current is to prevent the RRAM from dielectric hard breakdown. There are two steps needed to be set for the compliance current. One is the step for

“forming”; the other is the “set”. Generally speaking, the value of compliance current of “forming” is a few higher than that of “set”. This is because in the forming step, the conductive paths have to be formed. In this thesis, we set the compliance current through two different methods. In the 1R device, the compliance current is achieved by HP 4156C via the HT-BASIC language. And in the 1T1R device, the compliance current is achieved by the transistor through different gate voltage. In 1R device, the effect of limiting the current flow through the resistive random access memory is not ideal; because the

In contrast, the 1T1R structure is more reliable for conventional use as a result of excellent ability to limit the current flow through the resistive random access memory precisely.

3.2.2 The Predominant Step Before Resistive Switching - Forming

Before we start to operate the resistive switching random access memory correctly, we need to execute the so-called “forming” procedure first, as shown in Fig. 3.1. We add a ramped voltage on the top TiN electrode which is near the Ti buffer layer, and measure the corresponding current by HP 4156C semiconductor parameter analyzer. When the voltage is larger than the value which was determined by the thickness of HfO2, the current rushs to the value of compliance current, and the forming step is accomplished, as shown in Fig. 3.2.

3.2.3 The Resistive Switching Characteristics - Uni-Polar and Bi-Polar

After the “forming” process, this device switches to LRS（Low Resistance State）. The following step is to turn off it, which means to switch the RRAM from LRS to HRS（High Resistance State）.

There are two terminologies to identify the switching type of RRAM [3.1]. As shown in Fig. 3.3 and Fig. 3.4, one is uni-polar, and the other one is bi-polar. Uni-polar means that the turn on voltage and turn off voltage are in the same polarity, where the turn on voltage is usually larger than turn off voltage.

The cell remains “ON” state until the sweep voltage exceeds the turn off voltage. The cell remains

“OFF” state until the sweep voltage exceeds the turn on voltage. The uni-polar switching characteristic had been observed from many different switching materials. For example, D. Choi et al.[3.2] presented the uni-polar characteristic for the SrTiOx thin film. C. Rohde et al. [3.3] demonstrated the uni-polar characteristic for the TiO₂ thin film. On the other hand, the bi-polar means that the turn on voltage and turn off voltage are in opposite polarities. The bi-polar switching characteristic had been observed from many different switching materials, too. For example, K. Szot, W. Speier, et al. [3.4] demonstrated the

bi-polar characteristic for the SrTiO3 thin film. L. E. Yu et al. [3.5] presented the bi-polar characteristic for the TiOx thin film. The illustrations of sweep operation in this thesis are shown in Fig. 3.5.and Fig.

3.6 and obviously our device is switched through bi-polar type.

3.2.4 The Pulse Operation of RRAM

Besides the sweep operation, there is still another operate method for RRAM- pulse operation, and this kind of operation method is more practical for conventional use, as shown in Fig. 3.7 and Fig. 3.8.

The pulse width we used in this thesis is about 10 ns.

3.2.5 The Switching Parameter Definitions of RRAM

The main parameters used in our thesis are shown in Fig. 3.9. When the device is switched to LRS, we define Vset as the turn on voltage, and Iset as the corresponding current. When the device is switched to HRS, we define Vreset as the turn off voltage and Ireset as the corresponding current. We also define the maximum negative sweep voltage as Vstop.

There is still one question which has not been mentioned yet. How do we define the resistance of this device? In general, we read the current at 0.1V, and use the Ohm Law V = IR to obtain the resistance of this device. The “Forward Read” and “Reverse Read” technique are applied to RRAM, as we used popularly for the conventional memory device. Reading at voltage 0.1V stands for “Forward Read”, while reading at -0.1V means “Reverse Read”.

3.3 Reliability Issue

3.3.1 Effect of Electrode Area on Resistive Switching Properties

As shown in Fig. 3.10, the “Forming” voltage is dependent on the thickness of HfO₂. V_forming is about 2.5V for HfO2 thickness 5 nm while Vforming is about 3V if the thickness is 10 nm. Once the thickness is down to 3 nm, the “Forming” procedure is ignored. Fig. 3.11 indicates that the V_forming, V_set and Vreset are all independent of the cell size. This characteristic of independency of the cell area is one of the advantages of RRAM.

3.3.2 Multi-Level Operation of RRAM

The multi-level operation is one of the other advantages of RRAM. Fig. 3.12 and Fig. 3.13 show the possibility of multi-level operation. If we change the Vstop, the corresponding Vset will be different.

If we change the Iset, the corresponding Ireset will be different too. Obviously, the corresponding resistance will be different .Multi-level operation will be helpful for cell size scaling, and this characteristic will help us design a cell with more selectivity.

3.3.3 Data Retention Characteristics of RRAM

The other important reliability issue of memory cells is its data retention ability. We can achieve the multi-level states by two operation methods. One is the sweep mode, just as we mentioned in section 3.3.2, and the other one is the pulse operation. For data retention characteristic, we achieved the different resistance levels by pulse operation, and the data writing for six level resistance states has been demonstrated by varying the amplitude of 10 ns voltage pulse. In Fig. 3.14, the multi-level is achieved by pulse operation at 85 , and we check the retention time for the 10 years line. As it shows, ℃

we can obtain six different levels on one cell, and it is still maintains distinct levels after 1,000 seconds.

3.3.4 Program/Erase Cycling Endurance

In this section, we compare the cycling endurance of 1R and 1T1R device structures, where the HP 4156C and transistor are used for the current limiter respectively. As shown in Fig. 3.15 and Fig.

3.16, we can see the program/erase cycling endurance for the 1T1R and 1R devices respectively. The operational condition of 1R device structure is positive pulse 2.5V, negative pulse -3.6V, and the pulse width being 20ns for positive pulse and 80 ns for negative pulse respectively. For 1T1R device structure, positive pulse is 2.V, negative pulse is -3V and the pulse width are both 10 ns for positive and negative pulse. The RRAM still behaves well and the window reaches three orders after at least 10⁴ cycle times. We also observe program/erase cycling endurance degradation for the 1R device.

It could be the dielectric breakdown induced by the overshooting current which is not limited well with Agilent 4156C. From this experiment, we can understand the importance of the transistor in RRAM. With different gate voltages, we can control the compliance current precisely through the transistor, which was fabricated with advanced 0.18 um CMOS technology.

3.3.5 Read Disturb Immunity and temperature effect on RRAM

Fig. 3.17 shows the read disturb immunity of the stored bit by constant voltage stress at 1V. As we can see, the resistance is still a constant after stress voltage 1V with 1,000 seconds. In this experiment, we did not set any compliance current.

For the last part in this chapter, we review the temperature effect on this device. Fig. 3.18 shows

can see, at higher temperature, the maximum stress voltage is degraded to 0.7V. In Fig. 3.19, we show the temperature effect for sweep mode. The parameters Vset、Vreset are almost the same. From these data, it is suggested that this device has only weak dependence on the temperature.

TiOx

HfOx

TiN Forming

TiN

Fig. 3.1 The cross section of transition metal oxide based resistive switching memory during forming process.

0.0 0.5 1.0 1.5 2.0 2.5 3.0 0

10 20 30 40 50 60

Current, I ( u Α )

Voltage, V (V)

Forming

Compliance Current

Fig. 3.2 Forming : The predominant step before resistive switching operation

ON

OFF

ON OFF

C.C

C.C SET

RESET

RESET

SET

Fig. 3.3 Unipolar switching- Sketch of the resistive switching characteristics in a voltage sweep experiment. C.C denotes the current compliance. The set voltage is always higher than the voltage at which reset takes place, and

RESET

SET

C.C

Fig. 3.4 Bipolar switching- Sketch of the resistive switching characteristics in a voltage sweep experiment. C.C denotes the current compliamce. The set operation takes place on one polarity of the voltage or current, the reset operation requires the opposite polarity.

Fig. 3.5 Scheme of the negative sweep (Reset) operation in transition metal oxide based resistive memory.

Fig. 3.6 Scheme of the positive sweep (Set) operation in transition metal oxide based resistive memory

Fig. 3.7 Scheme of the positive pulse (Erase) operation in transition metal oxide based resistive memory.

Fig. 3.8 Scheme of the negative pulse (Program) operation in transition metal oxide based resistive memory.

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.01

0.1 1 10 100 1000

Cur rent, I ( u Α )

Voltage, V (V)

V

_set

I

_set

V

_reset

I

_reset,max

V

_stop

C.C

Fig. 3.9 Typical current-voltage characteristics of TiN/Ti/HfO2/TiN thin film based resistive switching memory. C.C denotes the current compliance. Vstop denotes the maximum negative sweep voltage. V_reset or I_reset,max are the voltage or current at which reset takes place. V_set or I_set are the voltage or current at which set takes place.

0 2 4 6 8 10 12 0

2 4 6 8

Forming V o ltage, V

forming

(V )

HfO

2

thickness (nm)

Fig. 3.10 HfO2 thickness dependence of the forming voltage on TiN/TiOx/HfOx/TiN thin film based resistive switching memory device.

0.1 0.2 0.3 0.4

Fig. 3.11 Cell sizes dependence of various resistance switching parameters in 1R configuration. (a) Forming voltage (Vforming), (b) Set voltage (Vset) and Reset voltage (Vreset).

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 10

^-5

10

^-4

10

^-3

Current, I (A)

Voltage, V (V) D -1.5

C -1.1 B -0.8 A -0.6

B A D C

Fig. 3.12 The multi-level characteristics of Rhigh in TiN/TiOx/HfOx/TiN device by

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 10

^-6

10

^-5

10

^-4

10

^-3

Current, I (A )

Voltage, V (V)

A 0.1mA B 0.5mA C 1mA D 3mA A B C D

A B D C

Fig. 3.13 The multi level characteristics of RLow in TiN/TiOx/HfOx/TiN device by

100 1k 10k 100k 1M 10M 100M 10k

100k 1M 10M 100M

Level 6 Level 5 Level 4 Level 3 Level 2

Resistance, R ( Ω )

Time, t (sec)

Level 1

10 yr

Fig. 3.14 Data Retention properties of various states in multi level operation. The result predicts 10 years lifetime of each state.

0 2000 4000 6000 8000 10000 1E-3

0.01 0.1 1 10

Resistance, R

(

ΜΩ

)

P/E Cycle Number (Time) 1T1R

P_pulse = 2V N_pulse = -3V

Pulse Width= 10 ns

Fig. 3.15 Superior pulse dependent switching property in 1T1R configuration by 10ns pulse. There is no window degradation after 10⁴ cycles. The set pulse height is

0 2000 4000 6000 8000 10000 1E-3

0.01 0.1 1

Resi stance, R

(

ΜΩ

)

P/E Cycle Number (Time) 1R

P_pulse = 2.5V, 20 ns N_pulse = -3.6V, 80 ns

Fig. 3.16 Switching property in 1T1R configuration by 10ns pulse. There is a little window degradation after 10⁴ cycles. The set pulse height is 2.5V, while reset pulse height is -3.6V, respectively. And the pulse width

is longer than the pulse width in 1T1R configuration.

0 200 400 600 800 1000 0.0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Resistance, R ( ΜΩ )

Stress Time, t (second) Vstress = 1 V

Fig. 3.17 Read disturb immunity of RHigh by constant voltage stress of 1 V for 1,000 seconds.

0 200 400 600 800 1000 0.5

1.0 1.5 2.0 2.5 3.0 3.5 4.0

Resistan ce, R

(

ΜΩ

)

Stress Time, t (second)

V

stress

=0.7V T=85oC

Fig. 3.18 Read disturb immunity of RHigh by constant voltage stress of 0.7V at 85 for ℃ 1,000 seconds.

-1.5 -1.0 -0.5 0.0

Fig. 3.19 Typical I-V characteristic of the transition metal oxide thin film based resistive switching memory under different temperature. (a) Reset (b) Set.

Chapter 4

Switching Mechanism of 1R and 1T1R Resistive Memory

4.1 Introduction

In this chapter, we investigate the basic switching properties of RRAM from the point of the

“forming” process, which is like the phenomenon of the dielectric soft breakdown. With the known mechanism of SBD on High-κ MOSC （MOS Capacitor）, we will compare the difference between RRAM and MOSCs on resistive switching. It could be realized that the unique “forming” process of RRAM’s comes from its different electrodes between MOSC’s. Furthermore, with its resistance switching phenomenon, we could be able to explain and extinguish the “Multi–read” operation in RRAM. Besides, having the established RTN measurement procedure, the possible mechanism of its resistance switching could be more clear.

4.2 The Predominant Step Before Resistive Switching - Forming

4.2.1 The Resistive Switching Characteristics after Dielectric Soft Breakdown

Even the “forming” phenomenon is said like “Soft Breakdown”（SBD）which we are familiar under MOS device [4.1], there would be more complete explanation for its phenomenon on RRAM’s resistive switching. Fig. 4.1 is the definition of soft breakdown [4.2].

With the opaque relation between “forming” and SBD, we take exercise on a High–κ MOSC about its SBD. The physical thickness of its dielectric is 2 nm, and the stress condition is 2.4 V, 400 seconds. The SBD phenomenon is observed in Fig. 4.2. The resistance comes to 10¹² Ω, which is more like the “un-forming” sample of RRAM. If the “forming” procedure is performed on MOSC, the

resistance still reaches 10⁹ Ω (Fig. 4.3). The forming voltage is about 9.2 V which is larger than the

resistance still reaches 10⁹ Ω (Fig. 4.3). The forming voltage is about 9.2 V which is larger than the

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